System Verilog Introduction & Usage IBM Verification Seminar Author: Johny Srouji, Intel Corporation IEEE P1800 Chair SystemVerilog Introduction (1) Presentation Objectives • Provide a brief history and status update of SystemVerilog as a HW Design & Verification Language • Provide a high level overview of the language capabilities and usage aspects This is not meant to be a tutorial of the language Parts of this presentation are based on material which was presented in DAC SystemVerilog workshop by technical committees chairs SystemVerilog Introduction (2) Agenda • Background – HW Design Languages – Problem Statement – IEEE P1800 Activity • SystemVerilog Design Modeling • SystemVerilog for Verification – Extensions for Test-Bench Modeling – Assertions • SystemVerilog DPI • A Quiz • Conclusions SystemVerilog Introduction (3) HW Design Languages • Hardware Description Language (HDL) is used to describe digital hardware elements • Various levels of design abstractions are used: – Behavioral: flow control, arithmetic operators, complex delays – Register Transfer Level (RTL): Structural description of the registers and the signal changes between registers – Gate level: combinatorial logic gates (and, or, not,…) – Switch level: layout description of the wires, resistors and transistors (CMOS,PMOS, etc) • Two main subsets: – Synthesizable – reflecting HW / Silicon – Non-Synthesizable – reflecting instrumentation code SystemVerilog Introduction (4) The Problem! e What’s Next? z • Quest for Performance is driving up i S complexity n – Deeper pipelines, increase in logic g i functionality and complexity, power issues, s e explosion in flops D Verilog RTL • Explosion in lines of RTL Code making verification a lot harder Schematics • Low Abstraction level of the RTL is driving 80’s 90’s higher verification effort and lower simulation speed – Trillions of cycles per lead project and s Increasing rate g more pre-silicon bug escapes u b n • Verification effort is reaching 60% of the o c i l i total design cycle s - e r – Usage of different languages makes it even P harder: reference models in C/C++, RTL in # Verilog or VHDL, Test Benches, Assertions, Checkers, Coverage Lead Projects SystemVerilog Introduction (5) Verilog History Verilog-1995 SystemVerilog 3.0 Gateway started to First IEEE Verilog Accellera develop Verilog Standard Extensions to V2K 1984 1990 1995 2001 2002 2003 Cadence bought Verilog-2001 (V2K) SystemVerilog 3.1 Gateway, and Enhancement – 2nd Extensions to 3.0 started pushing IEEE Verilog Verilog Standard SSyysstteemmVVeerriilloogg IIEEEEEE SSttaannddaarrdd iiss eexxppeecctteedd ttoo bbeeccoommee aavvaaiillaabbllee bbyy OOcctt’’22000055 SystemVerilog Introduction (6) SystemVerilog SV3.1 Focus: design SystemVerilog 3.1 - HDVL language cleanup Queues Test Bench Assertions APIs OO Classes Semaphores & Lists SV3.0 Focus: enhance design System Verilog 3.0 language capabilities Data Types Structures Advanced Control Interfaces Casting & Enums & Unions Operators Flow Verilog2K Multi-D Arrays Generate Automatic Tasks Verilog95 Gate Level Modeling & Timing Hardware Concurrency SystemVerilog Introduction (7) SystemVerilog Components Transaction-Level Advanced V Full Testbench g e verification capability Veriolog h A r Language with il c s il for semiformal and r n se o Teestbench r g Coverage V tb t formal methods. s io e IEEE n The Assertion T Language Standard Verilog I for Verilog V 2001 P D e A e ri & c e lo I a s P rf ig g e n D t Design In Abstraction: Interface Direct C interface, semantics, abstract Assertion API and data types, Coverage API abstract operators and expressions SystemVerilog Introduction (8) IEEE P1800 Structure Chair - Johny Srouji Vice chair – Shrenik Mehta IEEE P1800 Secretary - Dennis Brophy SystemVerilog WG Program Mgr: Noelle Humenick Errata Chair: Karen Pieper LRM – Chair: TBD Stu Sutherland P1800 Errata 1364 Verilog Sub-WG Champions Sub-WG SV- SV- SV- SV-CC & BTF Encryption Errata BC EC AC PTF (transfer/merge) SystemVerilog Introduction (9) SystemVerilog Design Modeling SystemVerilog enhances Verilog for Design Modeling • Data Types • Capturing Design Intent – SystemVerilog Data Types – always_* Procedural blocks – Packed & Unpacked Arrays – Unique and Priority Case • Data Organization – Nets and Variables – Structures & Unions • Powerful Syntax – Type Casting – Copy / Buffering – Enumerated Data Types – Port Connections • C-like functionality SystemVerilog Introduction (10) Basic SV3.1 Data Types reg r; // 4-value Verilog-2001 single-bit datatype integer i; // 4-value Verilog-2001 >= 32-bit datatype bit b; // single bit 0 or 1 logic w; // 4-value logic, x 0 1 or z as in Verilog byte b; // 2 value, 8 bit signed integer int i; // 2-value, 32-bit signed integer shortint s;// 2-value, 16-bit signed integer longint l; // 2-value, 64-bit signed integer Make your own types using typedef Use typedef to get C compatibility typedef shortint short; typedef longint longlong; typedef real double; typedef shortreal float; SystemVerilog Introduction (11) Packed And Unpacked Arrays unpacked a0 bit a [3:0]; a1 array of u n u s e d a2 bits a3 packed array of bit [3:0] p; p 3 p 2 p 1 p 0 bits bit [15:0] memory [1023:0]; 1k 16 bit memory[i] = ~memory[i+1]; unpacked memory[i] [15:8] = 0; memory Packed indexes can be sliced 1k 16 bit Can operate on packed bit [15:0] [1023:0] Frame; entire memory always @ (posedge inv) memory Frame = ~Frame; SystemVerilog Introduction (12) Data Organization • Signals are Meaningful In Groups – Instructions: Operation, Operands • Verilog Provides Only Informal Grouping reg [47:0] PktSrcAdr; reg [31:0] Instruction; reg [47:0] PktDstAdr; `define opcode 31:16 reg [7:0] InstOpCde; Instruction[`opcode] reg [7:0] InstOpRF [127:0]; By Name By Vector Location • Better to organize data in explicit, meaningful relationships between data elements • SystemVerilog Structs, Unions & Arrays alone or combined better capture design intent SystemVerilog Introduction (13) Data Organization - Structures struct { addr_t SrcAdr; • Structs Preserve addr_t DstAdr; Logical Grouping data_t Data; } Pkt; • Reference to Struct facilitates more Pkt.SrcAdr = SrcAdr; meaningful code if (Pkt.DstAdr == Node.Adr) LLikikee i nin C C b buut tw witihthoouut t ththee o opptitoionnaal ls strtruucctuturree tags before the { typedef struct { bit [7:0] opcode; tags before the { bit [23:0] addr; } instruction; // named structure type instruction IR; // define variable IR.opcode = 1; // set field in IR SystemVerilog Introduction (14) Data Organization - Packed Structures Consists of bit fields, which are packed together in memory without gaps – They are easily converted to and from bit vectors. struct packed { `define Valid 24 bit Valid; `define Tag 23:16 byte Tag; 15:0 bit [15:0] Addr; `define Addr } Entry; iTag = Entry[`Tag]; iTag = Entry.Tag; iAddr = Entry[`Addr]; iAddr = Entry.Addr; iValid = Entry[`Valid] iValid = Entry.Valid 32 0 unpacked 2 Valid packed struct may struct 1 Tag packed struct may 0 Addr ccoonntatainin o oththeerr p paacckkeedd structs or packed arrays 24 23 1615 0 structs or packed arrays Valid Tag Address packed struct SystemVerilog Introduction (15) Data Organization - Type Casting int'(2.0 * 3.0) A data type can be changed shortint' {8’hFA, 8’hCE} by using a cast (‘) operation 17 ' (x – 2) Any aggregate bit-level object can be reshaped OObbjejecctsts m muusst th haavvee Packed ⇔ Unpacked, Array ⇔ Structure idideenntitcicaal lb biti ts sizizee typedef struct { bit [7:0] f1; f1 A bit [7:0] f2; bit [7:0] f3[0:5]; f2 } Unpacked_s; { typedef struct packed f30 f31 f32 f33 f34 f35 bit [15:0][0:2] f1; bit [15:0] f2; } Packed_s; B Unpacked_s A; Packed_s B; f10 f11 f12 f2 … A = Unpacked_s’(B); B = Packed_s’(A); SystemVerilog Introduction (16) Data Organization - Unions typedef union { union typedef union { int n; byte [5:0] bytes; real f; provide storage for real rlevel; } u_type; either int or real integer ilevel; } Data_u_t; u_type u; struct { structs and unions can be assigned as a Data_u_t Data; whole logic isBytes; can contain fixed size packed or unpacked logic isReal; arrays logic isInteger; } DPkt; Unpacked Unions Enable Single Variable DPkt.Data = 3.124; to Contain Data from Multiple Types DPkt.IsReal = 1; Data Read from Unpacked Union Must Be if (DPkt.IsReal) from Last Field Written realvar = DPkt.rlevel; Requires Type Awareness SystemVerilog Introduction (17) Data Organization – Packed Unions • Packed Unions Enable • Packed Unions Enable Multiple Namespaces for Many Convenient Name Same-Sized, Integer Data References typedef logic [7:0] byte_t; inst.fields.opcode = 16’hDEAD; typedef struct packed { inst.bytes[1] = 8’hBE; logic [15:0] opcode; inst[7:0] = 8’hEF; logic [1:0] Mod; … inst == 32’hDEADBEEF; logic [2:0] Base; } Instruction_t; typedef union packed { byte_t [3:0] bytes; Instruction_t fields; • No Need To Test Type } Instruction_u; • Data Maps To All Instruction_u inst; Members SystemVerilog Introduction (18) Data Organization – Tagged Unions • Provide type-safety and brevity • Improve correctness • Improve ability to reason about programs for FV typedef tagged union { struct { bit [4:0] reg1, reg2, regd; } Add; tagIgInensdsttrur n iiinonsnsttr{r;; ...b..i.t [9:0] JmpU; ccasastsereu(c(itinns{sttrr)) mmaattcchheess ttabagiggtgeed[d1A:Ad0dd]d {c{rcr1,1,,rr22,,rrdd}}:: rrff[[rrdd]] == rrff[[rr11]] ++ rrff[[rr22]];; ttabagiggtgeed[d9J:Jm0mp]p jaj:d: d r; ccaassee ((jj)) mmaattcchheess } JmpC; ttaaggggeedd JJmmppUU aa :: ppcc == ppcc ++ aa;; } Jmp; ttaaggggeedd JJmmppCC {{cc,,aa}}:: } Instr; iiff ((rrff[[cc]]))