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C 2011 MICHAEL KAHN KATELMAN a META-LANGUAGE for FUNCTIONAL VERIFICATION c 2011 MICHAEL KAHN KATELMAN A META-LANGUAGE FOR FUNCTIONAL VERIFICATION BY MICHAEL KAHN KATELMAN DISSERTATION Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate College of the University of Illinois at Urbana-Champaign, 2011 Urbana, Illinois Doctoral Committee: Professor Jos´eMeseguer, Chair and Director of Research Professor Arvind, Massachusetts Institute of Technology Associate Professor Grigore Ros, u Professor Josep Torrellas ABSTRACT This dissertation perceives a similarity between two activities: that of coordi- nating the search for simulation traces toward reaching verification closure, and that of coordinating the search for a proof within a theorem prover. The programmatic coordination of simulation is difficult with existing tools for dig- ital circuit verification because stimuli generation, simulation execution, and analysis of simulation results are all decoupled. A new programming language to address this problem, analogous to the mechanism for orchestrating proof search tactics within a theorem prover, is defined wherein device simulation is made a first-class notion. This meta-language for functional verification is first formalized in a parametric way over hardware description languages using rewriting logic, and subsequently a more richly featured software tool for Verilog designs, implemented as an embedded domain-specific language in Haskell, is described and used to demonstrate the novelty of the programming language and to conduct two case studies. Additionally, three hardware description languages are given formal semantics using rewriting logic and we demonstrate the use of executable rewriting logic tools to formally analyze devices implemented in those languages. ii This dissertation is dedicated to MIPS Technologies, Inc., in appreciation for having provided me with the opportunity to closely observe the functional verification effort of the 74K microprocessor. iii ACKNOWLEDGMENT I entered the doctoral program during August of 2004, and ultimately defended on July 18, 2011. Summarizing concisely the nearly seven years during which I have been part of the Department of Computer Science at UIUC is, of course, impossible. However, I am profoundly grateful to have been able to participate in some way in the long and important tradition of scholarly work, and to have been able to experience so many of the special things that come from being an academic. Not the least of those things are all of the friendly, smart, and eccentric people who I met and shared the experiences with, and whose creativity was always thought provoking and entertaining. I am also incredibly grateful for the freedom I was afforded to pursue my own research agenda, and feel that it enriched my experience it immeasurably. In addition, I enjoyed especially the many seminars and courses I attended, books and research articles I learned from, research visits at other institutions, and conferences in far-away places (Svalbard!). A few people deserve special thanks in making all the incredible experiences noted above possible. My friend and advisor, Jos´eMeseguer, of course being foremost among them for his technical, emotional, and financial support, and for being so committed to the ideals of scholarly pursuit. Arvind and his research group at MIT could not have been more hospitable and welcoming, or more generous with their time. So much so that I inflicted myself upon them during three separate extended stays. I am also extremely grateful to the other members of my dissertation committee, Josep Torrellas and Grigore Ros, u, who were always kind and helpful in pursuing this work. I wish that I knew how to properly thank all of the people, places, and things with which I associate the best aspects of the past seven years: (apologies for omissions) Jos´eMeseguer, Arvind, Josep Torrellas, Grigore Ros, u, Tanya Crenshaw, Joe Hendrix, Sean Keller, Ralf Sasse, Camilo Rocha, iv Musab AlTurki, Kyungmin Bae, Beatriz Alarc´on,Ra´ulGuti´errez,Felix Schernhammer, Santiago Escobar, Peter Olveczky,¨ Francisco Duran, Nar- ciso Mart´ı-Oliet,Fredrik Kjølstad, Azadeh Farzan, Nana Arizumi, Traian S, erb˘anut, ˘a,Patrick Meredith, Chucky Ellison, Andrei S, tef˘anescu,Dennis Griffith, Michael Ilseman, Edgar Pek, Pavithra Prabhakar, David Nelson, Alexandre Duch^ateau,Jonas Eckhardt, Tobias M¨uhlbauer, Steven Lauter- burg, Rajesh Kumar Karmani, Vijay Ganesh, Nirav Dave, Myron King, Kermin Elliot Fleming, Michael Pellauer, Murali Vijayaraghavan, Abhinav Agarwal, Rays Jiang, Andrew Colombi, Jeff Green, Mark-Oliver Stehr, Susie Heo, Samuel Kamin, Bari¸sAktemur, Howard Katelman, Susan Katelman, John Katelman, Joseph Katelman, Madeline Katelman, Dav Zimak, Brendan Kiburg, Nicholas Rizzolo, The Graybeards. v TABLE OF CONTENTS CHAPTER 1 INTRODUCTION . 1 CHAPTER 2 PRELIMINARIES . 9 2.1 Rewriting Logic . .9 2.2 Haskell . 16 CHAPTER 3 RELATED WORK . 20 3.1 Functional Verification . 20 3.2 Rewriting Logic Semantics . 25 CHAPTER 4 FORMALIZATION . 28 4.1 Overview . 28 4.2 Parameterization . 30 4.3 Analogy . 31 4.4 RHDL ................................ 33 4.5 Problem . 34 4.6 RMETA ............................... 35 4.7 RIR ................................ 36 4.8 RSTRAT .............................. 39 4.9 Example . 39 CHAPTER 5 IMPLEMENTATION ARCHITECTURE . 42 5.1 VlogMetaLang ........................... 43 5.2 Skeleton . 45 5.3 VlogMetaLang.Core ....................... 46 5.4 VlogMetaLang.Syntax ...................... 48 5.5 VlogMetaLang.Data ....................... 49 5.6 VlogMetaLang.Util ....................... 51 5.7 VlogMetaLang.Strategy ..................... 52 5.8 VlogMetaLang.SMT ........................ 54 5.9 Example . 54 vi CHAPTER 6 CAPABILITIES . 59 6.1 Some Utilities . 61 6.2 Coordination of Multiple Simulations . 63 6.3 Feedback . 68 6.4 Backtracking . 72 6.5 Breadth-First . 76 6.6 Symbolic Execution . 79 6.7 Combined Concrete and Symbolic Simulation . 81 CHAPTER 7 CASE STUDIES . 85 7.1 I2C Bus-Master Controller . 85 7.2 Microprocessor . 91 CHAPTER 8 SEMANTICS: VERILOG . 102 8.1 Disclaimer . 102 8.2 Contributions . 102 8.3 Concepts . 103 8.4 Semantics: Configuration . 109 8.5 Semantics: Equations and Rules . 112 8.6 Examples . 119 CHAPTER 9 SEMANTICS: PRODUCTION RULE SETS . 126 9.1 Introduction . 126 9.2 Mathematical Semantics: MPRS ................. 128 9.3 Rewriting Logic Semantics: RPRS ................ 138 9.4 Relative Correctness of MPRS and RPRS ............ 151 9.5 Automated Hazard and Deadlock Freedom Analysis . 162 9.6 Speed-Independent and Quasi-Delay-Insensitive Circuits . 168 9.7 Conclusion . 170 CHAPTER 10 SEMANTICS: BTRS . 174 10.1 Syntax . 175 10.2 Caveats . 179 10.3 Example: Single-Element Queue . 180 10.4 Semantics Overview . 181 10.5 Expression Evaluation . 184 10.6 Action Evaluation . 189 10.7 Semantics . 192 10.8 Discussion . 193 10.9 Example: A Deadlocking Completion Buffer . 194 CHAPTER 11 CONCLUSION . 199 vii APPENDIX A IMPLEMENTATION DETAILS . 201 A.1 start ............................... 201 A.2 concretize ............................ 203 A.3 simulate ............................. 205 REFERENCES . 214 viii CHAPTER 1 INTRODUCTION The International Technology Roadmap for Semiconductors (ITRS) [41] is a biennial report on technical challenges confronting the global semiconductor industry, representing a consensus view of major industry associations from Asia, Europe, and the United States. Topics ranging from device physics to embedded software are discussed and analyzed to identify research directions and potential solutions, speculating over a fifteen-year time span. The topic of this dissertation is the part of the digital circuit design process called functional verification, wherein a device is evidenced to coincide with its high-level design specification, and about which the 2009/2010 ITRS makes the following statements. \Implied needs are in: (1) verification, which is a bottleneck that has now reached crisis proportions . " \. due to the growing complexity of silicon designs, functional verification is still an unresolved challenge, defeating the enormous effort put forth by armies of verification engineers and academic research efforts.” \Multiple sources report that in current development projects verification engineers outnumber designers, with this ratio reaching two to one for the most complex designs." [41, Design] The above quotations demonstrate the practical importance, and indeed the urgency of, concerted research efforts aimed at improving functional verification: effecting verification closure faster, at a higher quality, and with fewer engineering resources. Many aspects of the functional verification process warrant attention from researchers, however in this dissertation, we 1 Figure 1.1: Coverage Closure Feedback Loop. address just one, coverage closure. This is the iterative process of generating stimuli, running simulations, and assessing various coverage metrics (e.g. see [6]), as depicted in Figure 1.1. Janick Bergeron, a highly regarded engineer who has written extensively on functional verification (e.g. [5, 6]), recently said about the coverage closure process: Something that is challenging and time-consuming is an ideal candidate for automation. In [contemporary verification practice], the Holy Grail is the automation of the feedback loop between the coverage metrics and the constraint solver. [7, July 5, 2010] Fully automating this feedback loop is an unreasonable goal, as doing so would imply an efficient automated algorithm for reaching coverage closure;
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