Integrating e Verification IP in a VMM Testbench JL Gray Verilab
[email protected] Adiel Khan Synopsys
[email protected] 30 March 2010 ABSTRACT Modern testbenches often consist of components drawn from multiple languages. In many of these cases, multi-language and multi-methodology interaction is not well defined. In this paper, we will demonstrate the use of e verification components (eVCs) in a SystemVerilog/VMM testbench. Several complex issues arise when using SystemVerilog as the “primary” language. Initial simulator engine synchronization, random generation ordering, timing problems caused by program blocks, and methodology synchronization between the VMM and eRM will all be discussed. Copyright © 2010 Verilab, Inc. All rights reserved. Integrating e Verification IP in a VMM Testbench Contents 1 Overview ................................................................................................................... 3 1.1 Background .......................................................................................................... 3 1.2 Terminology ......................................................................................................... 4 1.3 Other Useful Terminology ................................................................................... 4 2 Challenges ................................................................................................................. 4 2.1 Method Ports ....................................................................................................... 4 2.2