Arm Cortex M7 Technical Reference Manual
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Arm cortex m7 technical reference manual Continue ARM Cortex-M is a family of IP cores, mainly for 32-bit microcontrollers developed by ARM and licensed by various manufacturers. The kernel introduces a reduced computer instruction kit (RISC), is part of the architecture of ARMv6 or ARMv6 ARMv7 and is divided into ascendable complexity into units of Cortex-M0, Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M3, Cortex-M4, Cortex-M7 and cortex-M33. ARM Cortex-M0 and M3 microcontrollers from NXP and Silicon Laboratories General ARM Limited do not produce microprocessors or microcontrollers themselves, but licenses the core to chip manufacturers and manufacturers, so-called Integrated Device Manufacturers (IDM), which are the actual core of ARM for proprietary and productive peripherals such as Controller Area Network (CAN), Expand serial interfaces, Ethernet interfaces, pulse width modulation outputs, analog to digital converters , Universal asynchronous receiver transmitter (UART) and more. These devices are connected to the ARM core with the Advanced Microcontroller (AMBA) bus architecture. ARM Limited offers a variety of kernel licensing models that differ in cost and volume of data provided. In all cases, the right is to freely distribute your own equipment with ARM processors. ARM Cortex-M processors are available to licensees as IP cores in Verilog hardware description language and can be displayed as a digital hardware circuit using logic synthesis, and can then be used either in the arrays (FPGAs) field programmable gates or specific integrated circuit applications (ASICs). Depending on the license model, either the IP core (IP-Core license) is allowed, or a brand new, proprietary microarchitecture can be developed that implements the ISA ARM (architectural license). If both licenses belong, you can also expand and change the IP kernels. The advantages of a license architecture are that in addition to integrating your own peripherals, other extensions such as your own machine commands, integrating special debugging interfaces or because of their own architecture, optimization for a specific purpose (such as mobile devices) is possible. The Cortex-M0 and M1 command suite is based on the ARMv6-M architecture, the Cortex-M3 architecture on the ARMv7-M architecture, and the Cortex-M4 and Cortex-M7 architectures armv7E-M. The differences primarily relate to the set of commands and available machine commands. Teh configured so that the binary machine commands are compatible up, i.e. the Cortex-M0 or M1 machine program is also capable of running on the Cortex-M3, M4 or M7 unchanged. Conversely, not all Cortex-M3, M4 or M7 commands can run on Cortex-M0 or M1. All processors in the Cortex-M family support core teams from the thumb-2 set, the Thumb 2 team set, and the hardware multiplier. However, the M0 and M1 lack new extensions such as CB, CBNS and IT teams in the thumb command set, which are only available in the later developed ARMv7-M architecture. And the Thumb 2 team set is limited to multiple teams such as BL, DMB, DSB, ISB, MRS and MSR. The limitations of the M0 and M1 are the result of a requirement to keep the chip area as low as possible. The Cortex-M3, with a larger chip area, includes a full thumb and thumb 2 command kit, also provides some special instructions, its own separation unit in the equipment, and can handle mathematical commands such as adding instead of overflowing with saturation, which is especially important in signal processing. The Cortex-M4 expands these capabilities with some special commands common to digital signal processors (DSP) and additionally provides a floating point block to handle floating then such numbers according to IEEE 754 for easy accuracy. The Cortex-M7 extends the floating point block to handle floating point numbers for double precision. Cortex-M-Femilli, Befelsece ARMCortex-M Thumb Thumb-2 Equipment-Multiplizierer Equipment-Dividierer DSPErweiterung S'tttigungs-arithmetik Gleitkommaeinheit Trustson ARMArchitektur Cortex-M0 Gretante Tails Tailmenge 1 oder 32 Cyclone Nein nein nein nein ARMv6-M'9 Cortex-M1 Grutentheils Teilmenge 3 oder 33 Cyclone Nein nein nein nein nein NEin ARMv6-M.9. Cortex-M3 Follsundig Follstundig 1 Chiklus ja ne nein teilweise nein ARMv7-M'10' Cortex-M4 Vollst'ndig Vollst'n Ggdig 1 Chiklus jha ja ja optional nein ARMv7E-M'10 Cortex-M7 Fallstundig 1 Chiklus jha ja optional nein ARMv7E-M'1 0 Cortex-M23 Follsundig Follstundig 1 Cycle yes yes yes no yes ARMv8-M'12' Cortex-M33 Full 1 cycle yes yes yes optional ja ARMv8-M ARM Cortex- M Options Cortex-M4 yes Optional Optional Cortex-M7 yes Optional Optional Optional Most Cortex-M3 and M4 chips offer bit banding. This means that certain bits in memory can be displayed on their own Word address, making it easier to address them. This should not be confused with However, whether this function exists on a specific Cortex-M implementation should be considered on a case-by-case basis. The types of this article or section consist mainly of lists that need to be replaced by thread text. Please help Wikipedia improve this. More information can be found here. Cortex-M0 Features of Cortex-M0 are: the architecture of the ARMv6-M architecture of von Neumann (unlike the M3 and M4) 32-bit multiplier, selected for synthesis with a loop that requires a larger chip area, or with 32 cycles and a smaller chip area. 3-stage pipeline implementations Among others, the following semiconductor manufacturers offer Cortex-M0 based microcontrollers: Infineon: XMC1000 family nuvoTon: NuMicro family NXP: LPC11xx and LPC12xx families STMicroelectronics: STM32-F0 family Toshiba: TX00 family Cortex-M0 + Special features of the Cortex-M0+ are: ARMv6-M architecture[9] Von Neumann architecture (unlike M3 and M4)[15] Wake-up interrupt controller[15] Interrupt vector table shift to RAM[15] Command set Thumb – almost entirely except for CBZ, CBNZ, IT. Thumb-2 subset consisting of BL, DMB, DSB, ISB, MRS, MSR. A 32-bit multiplier selected for cycle synthesis that requires a higher chip area, or with 32 cycles and a smaller chip area. 2-stage pipeline implementations Among others, the following semiconductor manufacturers offer Cortex-M0+ based microcontrollers: Atmel: SAM-D20/21 and SAM-D10/11 family Freescale: Kinetis KL family NXP: LPC800 family Renesas: Synergy family (S1) Silicon Laboratories: Zero Gecko Family (EFM32ZG) Spansion/Cypress: FM0+ Family STMicroelectronics: STM32L0 Family Cortex-M1 Special features of the Cortex-M1 are: ARMv6-M architecture[9] Command set Thumb – almost completely except for CBZ, CBNZ, IT. Thumb-2 subset consisting of BL, DMB, DSB, ISB, MRS, MSR. A 32-bit multiplier selected for cycle synthesis that requires a higher chip area, or with 32 cycles and a smaller chip area. Realizations Among other things, the following semiconductor manufacturers of the field programmable gate Array (FPGA) offer so-called soft cores for their logical modules: Actel FPGa Altera FPGAs Xilinx FPGAs Cortex-M3 → the main article: Cortex-M3 Cortex M3 in the NXP microcontroller, Type LPC1768 Special features Of the Cortex-M3 are: ARMv7-M Architecture 10 command kit full thumb 2 command set full thumb-2 command set 32-bit unit multiplier with loop, 2 to 12 long division command cycles, mathematical functions units with overflow or saturation of property. Pipeline with a forecast jump from 1 to 240 physical hardware interruptions, a special form interrupts with 12 cycles of delay. Different Standby Modes (Sleep Modes) Memory Protection Unit (MPU) with 8 regions as an option 1.25 DMIPS on the frequency of MHz clocks can be produced with 90 nm semiconductor technology. 32 W on MHz hour-speed area on chip for core: 0.12 mm2 Implementations Among other things, the following semiconductor manufacturers offer Cortex-M3 based microcontrollers: Actel: SmartFusion Family Atmel: SAM3 Family Cypress Semiconductor: PSoC 5 NXP: LPC13xx, LPC15xx, LPC17xx, LPC18xx Family Silicon Laboratories: Tiny Hekco (EFM32TG), Gekko (EFM32G), Leopard Gekko (EFM32LG) and Giant Gekko Families (EFM32GG) Spansion/Cypress: FM3 Family STMicroelectronics: STM32 F2, F1 L1, L1, W Family Texas Instruments: Stellaris, TMS470 and some processors from the OMAP4 Toshiba family: the TX03 Cortex-M4 family → main article: Special Cortex-M4 Features In the Cortex-M4 design corresponds to the M3, which is extended by special DSP commands and an additional floating point. Cortex-M4 with a floating point block is called Cortex-M4F. Special features of the Cortex-M4 architecture are: the architecture of ARMv7E-M, which sets a complete set of commands of the thumb, a complete set of commands of the thumb-2 with a 32-bit multiplier with a loop, from 2 to 12 cycles of long division team, a mathematical block of functions with overflow or saturation properties. DSP extensions: 16/32-bit MAC one-cycle team, 8/16-bit SIMD arithmetic. an additional floating point block called FPv4-SP, IEEE-754. A 3-stage conveyor with a jump forecast of 1 to 240 physical hardware breaks, a special form interrupts with 12 cycles of delay. verschiedenartiger Bereitschaftsbetrieb (Sleep Modes) Speicherschutzeinheit (MPU) mit 8 Regionen als Option 1,25 DMIPS pro MHz Taktfrequenz (1,27 DMIPS / MHz mit FPU) Implementierungen Unter anderem bieten folgende Halbleiterhersteller Cortex-M4 basierende Mikrocontroller an: Atmel: SAM4-Familie (Cortex-M4) Freescale: Kinetis-Familie (Cortex-M4 und Cortex-M4F) Infineon: XMC4000-Familie (Cortex-M4F) NXP: LPC40xx- und LPC43xx-Familien (Cortex-M4) Silicon Laboratories: Pearl-Gecko-Familie (EFM32PG, Cortex-M4) und Wonder Gecko Familie (EFM32WG, Cortex-M4F) Spansion/Cypress: FM4-Familie (Cortex-M4F) STMicroelectronics: STM32-F4, L4-, F3-, G4-Familien (Cortex-M4F) Texas Instruments: Stellaris-LM4F- und Tiva-TM4C-Familie (Cortex-M4F) Toshiba: TX04-Familie (Cortex-M4F) Cortex-M7 Besonderheiten Im Vergleich zum Cortex-M4 wurde der M7 mit einer längeren Dual-Issue-Pipeline für höhere Taktfrequenzen, einem neu konzipierten Speichersystem u.