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Standby Power Management Architecture for Deep- Submicron Systems

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Standby Power Management Architecture for Deep- Submicron Systems Standby Power Management Architecture for Deep- Submicron Systems Michael Alan Sheets Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2006-70 http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-70.html May 19, 2006 Copyright © 2006, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Standby Power Management Architecture for Deep-Submicron Systems by Michael Alan Sheets B.S.C.E. (Georgia Institute of Technology) 1999 M.S. (University of California, Berkeley) 2003 A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences in the GRADUATE DIVISION of the UNIVERSITY OF CALIFORNIA, BERKELEY Committee in charge: Professor Jan Rabaey, Chair Professor Robert Brodersen Professor Paul Wright Spring 2006 The dissertation of Michael Alan Sheets is approved: Chair Date Date Date University of California, Berkeley Spring 2006 Standby Power Management Architecture for Deep-Submicron Systems Copyright 2006 by Michael Alan Sheets 1 Abstract Standby Power Management Architecture for Deep-Submicron Systems by Michael Alan Sheets Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences University of California, Berkeley Professor Jan Rabaey, Chair In deep-submicron processes a signi¯cant portion of the power budget is lost in standby power due to increasing leakage e®ects. For systems that have long idle times punctuated by bursts of activity, such as PDAs, cell-phones, and wireless sensor networks nodes, this standby power consumption reduces the e®ectiveness of duty-cycling. This work surveys a number of subthreshold leakage reduction techniques and identi¯es supply rail gating (MTCMOS) as the most promising. MTCMOS is a dynamic technique that has two distinct modes: an active processing mode and a lower power sleep mode. The smallest area implementations of MTCMOS have the side-e®ect of losing the state of the system when in sleep mode. This complicates the resumption of the active mode, because traditional designs are intolerent to the loss of state. This work presents a general framework to reduce the state maintainence requirements during sleep mode, without losing information required to resume the active mode. The framework is applied to ¯nite state machines and microprocessors, since these are commonly used in system design. Partitioning the system into subsystems with individually controlled supply rails (termed power domains) allows ¯ne-grain control of the power mode for portions of the chip. Each power domain must be dynamically put in the appropriate power mode to ensure correct system operation while minimizing power consumption. This control logic collectively forms the core of a power manager. Most power manager implementation approaches are largely ad-hoc and custom designed for each application. This work presents a structured methodology and architecture for the implementation 2 and control of power domains to form a power managed system. Approaches to the partitioning and implementation of individual power domains are explored. The functional requirements for the power manager are examined, including the physical and temporal composition of the power domains. This methodology and architecture are demonstrated on the protocol processor for the PicoRadio wireless sensor network node. The Charm test chip, implemented in 130nm CMOS, uses supply rail gating for eight power domains to reduce standby power 92%. Professor Jan Rabaey Dissertation Committee Chair i For my parents ii Contents List of Figures v List of Tables vii Acknowledgments viii 1 Introduction 1 1.1 Problem statement ................................ 1 1.1.1 Increasing dominance of standby power ................ 1 1.1.2 Impact on burst systems ......................... 2 1.2 Thesis ....................................... 3 1.2.1 Power domain modes ........................... 4 1.2.2 Power managed system ......................... 4 1.3 Overview of thesis ................................ 5 1.3.1 Contributions ............................... 5 1.3.2 Outline .................................. 6 2 Power Reduction Techniques 7 2.1 Standby Power Reduction ............................ 7 2.1.1 Clock Gating ............................... 7 2.1.2 Reducing Standby Activity ....................... 9 2.2 Sources of Static Power ............................. 9 2.2.1 Gate Leakage ............................... 9 2.2.2 Subthreshold Leakage .......................... 11 2.3 Devices and Circuits ............................... 11 2.3.1 Raising the Threshold Voltage ..................... 12 2.3.2 Power Rail Gating ............................ 17 2.3.3 Comparison of Techniques ........................ 21 3 System State 23 3.1 Types of State .................................. 23 3.2 Methodology ................................... 25 3.3 Case Studies ................................... 26 3.3.1 Finite State Machines .......................... 26 CONTENTS iii 3.3.2 Extended Finite State Machines .................... 34 3.3.3 Microprocessors .............................. 41 4 Power Managed System 44 4.1 Power Domains .................................. 44 4.2 Physical Composition .............................. 45 4.3 Temporal Composition .............................. 46 4.3.1 Correctness ................................ 46 4.3.2 E±ciency ................................. 47 4.3.3 Scheduling ................................ 48 4.4 Power Manager Components .......................... 53 4.4.1 Scheduler ................................. 53 4.4.2 System Timewheel ............................ 56 4.4.3 Power Control Network ......................... 57 4.4.4 Domain Controllers ........................... 59 4.5 Locality and Scalability ............................. 59 5 PicoRadio Design Driver 61 5.1 Quark PicoNode System ............................. 61 5.2 Power Domain Architecture ........................... 63 5.2.1 Partitioning ................................ 63 5.2.2 Power Modes ............................... 65 5.2.3 Power Interface .............................. 66 5.2.4 Sleep Mode Implementation ....................... 69 5.3 Power Domain Functionality .......................... 71 5.3.1 Domain `dw8051' ............................. 72 5.3.2 Domain `netq' .............................. 78 5.3.3 Domain `dll' ................................ 80 5.3.4 Domain `neighbor' ............................ 85 5.3.5 Domain `serial' .............................. 87 5.3.6 Domain `interface' ............................ 88 5.3.7 Domain `location' ............................ 89 5.3.8 Domain `baseband' ............................ 90 5.4 Power Manager Architecture .......................... 91 5.4.1 Power Network Interface (PNI) ..................... 91 5.4.2 Time subsystem ............................. 92 5.4.3 Power subsystem ............................. 94 5.4.4 Domain controller subsystem ...................... 97 5.4.5 Command and Event FSMs ....................... 99 5.5 Implementation .................................. 99 5.5.1 Design Flow Overview .......................... 99 5.5.2 Emulation Targets ............................ 101 5.5.3 ASIC implementation .......................... 104 5.5.4 Hierarchical Floorplanning ....................... 104 5.5.5 Power Domain Implementation ..................... 104 CONTENTS iv 5.5.6 JTAG Test Port ............................. 106 5.6 Results ....................................... 107 5.6.1 Functional Testing ............................ 107 5.6.2 Leakage Measurements .......................... 110 6 Conclusions and Future Work 113 Bibliography 115 A Charm C Library Header File 120 v List of Figures 1.1 Leakage and active power trends according to ITRS roadmap. ........ 2 1.2 Duty cycling savings curve with 5% activity factor and accounting for leak- age power consumption. ............................. 3 2.1 Gated and enabled clocks used to reduce switching activity. ......... 8 2.2 Load lines for stack e®ect ............................ 12 2.3 Stack e®ect performance degradation ...................... 13 2.4 Circuit for multiple threshold CMOS (MTCMOS) using sleep transistors. 18 2.5 Circuit variants of MTCMOS that retain the state. .............. 19 2.6 Graph of performance and leakage vs. MTCMOS power switch size for inverter chain. ................................... 20 2.7 Graph of lowest virtual supply voltage vs. MTCMOS power switch size for inverter chain with VDD = 1:2V. ........................ 20 2.8 Graph of performance vs. virtual supply node capacitance for same test circuit used for Figure 2.6 (W=L = 10). .................... 21 3.1 Baseline and pipelined datapath example circuit. ............... 25 3.2 Basic concept of FSM transformation. ..................... 31 3.3 State transition diagram of sleep FSM. ..................... 31 3.4 Block diagram of transformed FSM next state logic. ............. 33 3.5 State transition diagram for a basic EFSM. .................. 35 3.6 State transition diagram for EFSM in Figure 3.5 expanded to a FSM. ... 37 3.7
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