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Microprocessor Design Microprocessor Design en.wikibooks.org March 15, 2015 On the 28th of April 2012 the contents of the English as well as German Wikibooks and Wikipedia projects were licensed under Creative Commons Attribution-ShareAlike 3.0 Unported license. A URI to this license is given in the list of figures on page 211. If this document is a derived work from the contents of one of these projects and the content was still licensed by the project under this license at the time of derivation this document has to be licensed under the same, a similar or a compatible license, as stated in section 4b of the license. The list of contributors is included in chapter Contributors on page 209. The licenses GPL, LGPL and GFDL are included in chapter Licenses on page 217, since this book and/or parts of it may or may not be licensed under one or more of these licenses, and thus require inclusion of these licenses. The licenses of the figures are given in the list of figures on page 211. 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Contents 1 Introduction 3 1.1 About This Book ................................ 3 1.2 How Will This Book Be Organized? ...................... 3 1.3 Prerequisites ................................... 4 1.4 Who Is This Book For? ............................. 4 1.5 What This Book Will Not Cover ....................... 4 1.6 Terminology ................................... 5 2 Microprocessors 7 2.1 Microprocessors ................................. 7 2.2 Abstraction Layers ............................... 11 2.3 Operating System ................................ 12 2.4 ISA ........................................ 12 2.5 Moore’s Law ................................... 12 2.6 Clock Rates ................................... 14 2.7 Basic Elements of a Computer ......................... 15 3 Computer Architecture 17 3.1 Von Neumann Architecture .......................... 17 3.2 Harvard Architecture .............................. 18 3.3 Modern Computers ............................... 18 3.4 RISC and CISC and DSP ........................... 18 3.5 Microprocessor Components .......................... 19 3.6 Endian ...................................... 22 3.7 Stack ....................................... 23 3.8 further reading ................................. 24 4 Instruction Set Architectures 25 4.1 ISAs ....................................... 25 4.2 Memory Arrangement ............................. 26 4.3 Common Instructions .............................. 26 4.4 Instruction Length ............................... 28 4.5 Further reading ................................. 29 5 Memory 31 5.1 Memory Hierarchy ............................... 31 5.2 Hard Disk Drives ................................ 31 5.3 RAM ....................................... 31 5.4 Cache ...................................... 33 5.5 Registers ..................................... 33 III Contents 6 Control and Datapath 35 6.1 References .................................... 36 7 Performance 37 7.1 Clock Cycles ................................... 37 7.2 Cycles per Instruction ............................. 37 7.3 Instruction count ................................ 38 7.4 CPU Time .................................... 38 7.5 Performance ................................... 38 7.6 Amdahls Law .................................. 38 7.7 Benchmarking .................................. 39 8 Assembly Language 41 8.1 Assemblers .................................... 41 8.2 Assembly Language Constructs ........................ 41 8.3 Load and Store ................................. 42 8.4 Arithmetic .................................... 42 8.5 Jumping ..................................... 42 8.6 Branching .................................... 42 8.7 Further reading ................................. 43 9 Design Steps 45 9.1 Determine Machine Capabilities ........................ 45 9.2 Design the Datapath .............................. 46 9.3 Create ISA .................................... 46 9.4 Instruction Set Design ............................. 47 9.5 Build Control Logic ............................... 48 9.6 Design the Address Path ............................ 48 9.7 Verify the design ................................ 48 9.8 Further reading ................................. 49 9.9 References .................................... 49 10 Basic Components 51 10.1 Basic Components ............................... 51 10.2 Registers ..................................... 51 10.3 Multiplexers ................................... 52 10.4 Adder ...................................... 53 11 Program Counter 55 11.1 Updating the PC ................................ 55 11.2 Branching .................................... 57 12 Instruction Decoder 61 12.1 RISC Instruction Decoder ........................... 61 12.2 CISC Instruction Decoder ........................... 61 13 Register File 63 13.1 Register File ................................... 64 13.2 More registers than you can shake a stick at . 66 IV Contents 13.3 Register Bank .................................. 67 13.4 References .................................... 69 14 Memory Unit 71 14.1 Memory Unit .................................. 71 14.2 Actions of the Memory Unit .......................... 71 14.3 Timing Issues .................................. 71 15 ALU 73 15.1 Tasks of an ALU ................................ 74 15.2 ALU Slice .................................... 74 15.3 Example: 2-Bit ALU .............................. 74 15.4 Example: 4-Bit ALU .............................. 75 15.5 Additional Operations ............................. 76 15.6 ALU Configurations .............................. 76 15.7 References .................................... 83 16 FPU 85 16.1 Floating point numbers ............................. 85 16.2 Floating Point Unit Design ........................... 86 16.3 Further Reading ................................. 87 17 Control Unit 89 17.1 Simple Control Unit .............................. 89 17.2 Complex Control Unit ............................. 89 18 Add and Subtract Blocks 91 18.1 Addition and Subtraction ........................... 91 18.2 Bit Adders .................................... 91 18.3 Serial Adder ................................... 95 18.4 Parallel Adder .................................. 95 18.5 Sources ...................................... 101 19 Shift and Rotate Blocks 103 19.1 Shift and Rotate ................................ 103 19.2 Logical Shift ................................... 103 19.3 Arithmetic shift ................................. 103 19.4 Rotations .................................... 104 19.5 Fast Shift Implementations . 105 19.6 Further reading ................................. 105 20 Multiply and Divide Blocks 107 20.1 Multiply and Divide Problems . 107 20.2 Multiplication Algorithms . 107 20.3 Division Algorithm ............................... 108 20.4 Multiply and Accumulate . 108 21 ALU Flags 109 21.1 Comparisons ................................... 109 V Contents 21.2 Zero Flag .................................... 109 21.3 Overflow Flag .................................. 109 21.4 Carry/Borrow flag ............................... 109 21.5 Comparisons ................................... 110 21.6 Latch ALU flags or not? ............................ 110 22 Single Cycle Processors 111 22.1 Cycle Times ................................... 111 22.2 Redundant Hardware .............................. 111 22.3 Single Cycle Designs .............................. 112 23 Multi Cycle Processors 113 23.1 Multi-Cycle Stages ............................... 113 23.2 Hardware Reuse ................................. 114 24 Pipelined Processors 115 24.1 Pipelining Introduction ............................. 115 24.2 Pipelining Hardware .............................. 116 24.3 Superpipeline .................................. 118 24.4 Resources .................................... 119 25 Superscalar Processors 121 26 VLIW Processors 123 26.1 VLIW Vs Superscalar .............................. 123 26.2 Multi-Issue .................................... 123 27 Vector Processors 125 27.1 Parallel Execution ............................... 125 27.2 Non-Parallel Execution ............................. 126 28 Multicore Processors 127 28.1 Symmetric Multi-core .............................. 127 28.2 Asymmetric Multi-core ............................. 127 28.3 Symmetric Multicore .............................. 128 28.4 Asymmetric Multi-core ............................. 129 28.5 further reading ................................. 130 29 Exceptions 131 30 Interrupts 133 30.1 Further Reading ................................. 134 31 Hazards 135 31.1 Data Hazards .................................. 135 31.2 Control Hazards ................................. 136 31.3 Structural Hazards ............................... 136 31.4 Fixing Hazards ................................
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