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Institutionen För Systemteknik Department of Electrical Engineering Institutionen för systemteknik Department of Electrical Engineering Examensarbete/Master Thesis Improving an FPGA Optimized Processor Examensarbete utfört i elektroniksystem vid Tekniska högskolan vid Linköpings universitet av Mahdad Davari LiTH-ISY-EX--11/4520--SE Linköping 2011 TEKNISKA HÖGSKOLAN LINKÖPINGS UNIVERSITET Department of Electrical Engineering Linköpings tekniska högskola Linköping University Institutionen för systemteknik S-581 83 Linköping, Sweden 581 83 Linköping This page intentionally left blank. Improving an FPGA Optimized Processor Examensarbete utfört i Datorteknik vid Tekniska högskolan i Linköping av Mahdad Davari LiTH-ISY-EX--11/4520--SE Handledare: Andreas Ehliar ISY, Linköpings universitet Examinator: Olle Seger ISY, Linköpings universitet Linköping, October 2011 This page intentionally left blank. II Presentation Date Department and Division 2011-10-14 Department of Electrical Engineering Publishing Date (Electronic version) 2011-10-17 Language Type of Publication ISBN (Licentiate thesis) x English Licentiate thesis Other (specify below) x Degree thesis ISRN: LiTH-ISY-EX--11/4520--SE Thesis C-level Title of series (Licentiate thesis) Thesis D-level Report Number of Pages Other (specify below) Series number/ISSN (Licentiate thesis) 117 URL, Electronic Version http://www.ep.liu.se Publication Title Improving an FPGA Optimized Processor Author Mahdad Davari Abstract This work aims at improving an existing soft microprocessor core optimized for Xilinx Virtex®-4 FPGA. Instruction and data caches will be designed and implemented. Interrupt support will be added as well, preparing the microprocessor core to host operating systems. Thorough verification of the added modules is also emphasized in this work. Maintaining core clock frequency at its maximum has been the main concern through all the design and implementation steps. Keywords FPGA, Soft Microprocessor Core, IP, Cache, Exception Handling, MIPS III This page intentionally left blank. IV Abstract This work aims at improving an existing soft microprocessor core optimized for Xilinx Virtex®-4 FPGA. Instruction and data caches will be designed and implemented. Interrupt support will be added as well, preparing the microprocessor core to host operating systems. Thorough verification of the added modules is also emphasized in this work. Maintaining core clock frequency at its maximum has been the main concern through all the design and implementation steps. V This page intentionally left blank. VI Acknowledgements I hereby would like to thank my supervisor, Dr. Andreas Ehliar, who allowed me to work on this project under his supervision. I would like to express my gratitude to him for providing invaluable technical support during discussion sessions throughout the project, and also having to withstand my boring questions from time to time. This thesis was a rare opportunity for me to review the outstanding work of experts previously worked on this project. It provided me with the chance to review the whole processor design flow in practice and find insight into processor design issues. I would also like to express my gratitude to all the kind staff at Computer Engineering division, for all their support and providing a friendly work environment. I consider any contributions stemmed from this work as a result of “standing on the shoulder of giants”. VII This page intentionally left blank. VIII Contents 1.Introduction 1 1.1 Purpose ....................................................................................... 1 1.2 Intended Audience ...................................................................... 2 1.3 Limitations ................................................................................... 2 1.4 Outline ......................................................................................... 2 1.5 Abbreviations .............................................................................. 3 2.Background 7 2.1 FPGA ............................................................................................ 7 2.1.1 Configurable Logic Block .................................................. 8 2.1.2 Block RAM ...................................................................... 11 2.2 Soft Microprocessor Cores ......................................................... 13 2.3 MIPS .......................................................................................... 13 2.4 ξ Soft Microprocessor Family Overview ..................................... 14 2.5 Optimization Techniques ........................................................... 17 3.Instruction Cache 21 3.1 Locality of References ................................................................ 21 3.2 Memory Hierarchy ..................................................................... 22 3.3 Cache Memory Basics ................................................................ 24 3.3.1 Cache Organization ........................................................ 25 3.3.2 Block Size ....................................................................... 28 3.3.3 Block Replacement ......................................................... 29 3.3.4 Data Consistency ............................................................ 30 IX X Contents 3.4 Instruction Cache Implementation ............................................ 31 3.4.1 BRAM Dual Port Configuration ....................................... 35 3.4.2 Cache Controller FSM ..................................................... 38 3.4.3 Cache miss and Pipeline ................................................. 39 3.4.4 Cache miss and Restart Address ..................................... 40 3.4.5 Instruction Preprocessor ................................................ 41 3.4.6 Way Prediction ............................................................... 43 4.Data Cache 49 4.1 Data Cache Organization ........................................................... 49 4.2 Data Cache Controller ................................................................ 52 4.3 Write Policy ............................................................................... 52 4.4 Cache Miss and Pipeline ............................................................ 54 4.5 Cache Miss Hazards ................................................................... 54 4.6 Cache Miss and Restart Address ................................................ 55 4.7 Read After Write Hazard ............................................................ 55 4.8 Critical Path ............................................................................... 57 4.9 Simultaneous Instruction and Data Cache Misses ...................... 57 5.Verification 59 5.1 Test Considerations ................................................................... 59 5.2 Use of Python™ Script................................................................ 60 5.3 I-Cache Test Corner Cases .......................................................... 62 5.4 I-Cache Test Bench Structure ..................................................... 63 5.5 D-Cache Test Corner Cases ........................................................ 66 6.Interrupts and Exceptions 67 6.1 Introduction to Interrupts and Exceptions ................................. 67 6.2 MIPS Exception and Interrupt Basics ......................................... 68 Contents XI 6.2.1 Pre-Service Tasks ............................................................ 70 6.2.2 Service Routine Tasks ..................................................... 72 6.2.3 Post-Service Tasks .......................................................... 72 6.3 Exception Handler Implementation ........................................... 73 6.3.1 Special Purpose Register File .......................................... 75 6.3.2 Extending the Instruction Set ......................................... 76 6.3.3 Program Counter Extension ........................................... 77 6.3.4 Timer Interrupt .............................................................. 77 6.4 Return Address .......................................................................... 78 6.5 User/Kernel Mode ..................................................................... 79 6.6 Uncached I/O ............................................................................. 80 6.6.1 MIPS Memory Map ........................................................ 80 6.6.2 Implementation ............................................................. 81 7.Results 87 7.1 Overall Synthesis Report ............................................................ 87 7.2 ICache Synthesis Report ............................................................ 88 7.3 DCache Synthesis Report ........................................................... 88 7.4 Exception Handler Synthesis Report .......................................... 89 8.Conclusions 91 9.Future Work 95 Bibliography 97 A ξ2 Soft Microprocessor Core Timeline 101 B XIPS Core Synthesis Report 103 XII Contents C XICE Core Synthesis Report 105 D XIPS Core ICache Synthesis Report 107 E XICE Core ICache Synthesis Report 109 F XIPS Core DMem Synthesis Report 111 G XICE Core DMem Synthesis Report 113 H XIPS Core Decoder, Logic Unit, PC Synthesis Report 115 I XICE Core Exception Handler Synthesis Report 117 Chapter 1 Introduction "Research is what I'm doing when I don't know what I'm doing." Wernher von Braun 1.1 Purpose This thesis work will focus on improving an FPGA optimized processor by adding caches and interrupt support, enabling the processor to host operating
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