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NESS Esk a 2005.0034090 a 22005 Sato Et US007 185309B1 (12) United States Patent (10) Patent No.: US 7,185,309 B1 Kulkarni et al. (45) Date of Patent: Feb. 27, 2007 (54) METHOD AND APPARATUS FOR 2004/0006584 A1 1/2004 Vandeweerd APPLICATION-SPECIFIC PROGRAMMABLE 2004/O128120 A1 7/2004 Coburn et al. NESS Esk A 2005.00340902005/0114593 A1A 220055/2005 SatoCassell et al.et al. (75) Inventors: Chidamber R. Kulkarni, San Jose, CA 2005/0172085 A1 8/2005 Klingman (US); Gordon J. Brebner, Monte 2005/0172087 A1 8/2005 Klingman Sereno, CA (US); Eric R. Keller, 2005/0172088 A1 8/2005 Klingman Boulder, CO (US); Philip B. 2005/0172089 A1 8/2005 Klingman James-Roxby, Longmont, CO (US) 2005/0172090 A1 8/2005 Klingman O O 2005/0172289 A1 8/2005 Klingman (73) Assignee: Xilinx, Inc., San Jose, CA (US) 2005/0172290 A1 8/2005 Klingman (*) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 (21) Appl. No.: 10/769,591 OTHER PUBLICATIONS (22) Filed: Jan. 30, 2004 U.S. Appl. No. 10/769,330, filed Jan. 30, 2004, James-Roxby et al. (51) Int. Cl. (Continued) G06F 7/50 (2006.01) Primary Examiner Thuan Do (52) U.S. Cl. ............................................. 716/18: 718/2 Assistant Examiner Binh Tat (58) Field of Classification Search .................. 716/18, (74) Attorney, Agent, or Firm—Robert Brush 716/2, 3: 709/217: 71.9/313 See application file for complete search history. (57) ABSTRACT (56) References Cited U.S. PATENT DOCUMENTS Programmable architecture for implementing a message 5,867,180 A * 2/1999 Katayama et al. .......... processing system using an integrated circuit is described. In 6,078,736 A 6, 2000 Guccione an example, specification data is received that includes 6.82.183 B1 1/2001 Wingard et al. attributes of the memory system. A logical description of the 6,230307 B1 5/2001 Davis et al. memory system is generated in response to the specification 6,324,629 B1 1 1/2001 Kulkarni et al. data. The logical description defines a memory component 6.405,160 B1 6/2002 Djaja et al. and a memory-interconnection component. A physical 6,581,187 B2 6/2003 Gupta et al. description of the memory system is generated in response 6,647.431 B1* 11/2003 Utas - - - - - - - - - - - - - - - - - - - - - - - - - - - T19, 313 tO the logical description. The physical description includes 2% R ck '3.S. Ein et al. ............. 716/17 memory circuitry associated with the integrated circuit - I e defined by the memory component. The memory circuitry 6,891,397 B1 5, 2005 Brebner includes an interconnection topology defined by the memory 6,918, 103 B2 * 7/2005 Brawn et al. ................. T16/18 interconnection component 2003/00333.74 A1 2/2003 Horn et al. ................. 709/217 p 2003/O126195 A1 7/2003 Reynolds et al. 2003. O182083 A1 9, 2003 Schwenke et al. 11 Claims, 15 Drawing Sheets 700 SPECIFY MEMORYMIDL stJBSYSTEMUSING EMERATEGICAL VIEWFMENRY --- 706 SUBSYSTEM -- ANALYZEANOR OTMZ MMORY -- 707 SUBSYSTEM MAPLOGICAL WEW OF MEMORY SU3SYSTEMONTCFPGAACHITECTURE --- 78 TO PRODUCEFPGAES3NATA COMBINEFPGA SIGNATAWTH cTHRESIGNATA TodFINE SYSTEM --- 70 PCCESS collMEd FPGADESIGNATA to PRODUCE configuration stSTREAM-72 AA LOADBITSTREAMNTOFPA US 7,185,309 B1 Page 2 U.S. PATENT DOCUMENTS Gordon Brebner; "Single-chip Gigabit Mixed-version IP Router on Virtex-II Pro'; Proceedings of the 10th Annual IEEE Symposium on 2005/0177671 A1 8/2005 Klingman Field-Programmable Custom Computing Machines (FCCM'02 2005/0210178 A1 9/2005 Klingman 2005/0223384 A1 10/2005 Klingman );Apr. 2002; IEEE Computer Science Press; pp. 35-44. 2005, O262286 A1 11/2005 Klingman Xilinx, Inc.; U.S. Appl. No. 10/402,659 filed on Mar. 28, 2003 by James-Roxby. OTHER PUBLICATIONS Xilinx, Inc.; U.S. Appl. No. 10/420,652 filed on Apr. 21, 2003 by U.S. Appl. No. 10/769,331, filed Jan. 30, 2004, Keller et al. Brebner. U.S. Appl. No. 10/769,592, filed Jan. 30, 2004, Brebner et al. Gordon Brebner; “Multithreading for Logic-Centric Systems'; 12th Xilinx, Inc.; U.S. Appl. No. 10/421,013 filed on Apr. 21, 2003 by International Conference on Field Programmable Logic and Appli Brebner. cations; Montepellier, France; Sep. 2-4, 2002; Springer LNCS 2438; pp. 5-14. * cited by examiner U.S. Patent Feb. 27, 2007 Sheet 1 of 15 US 7,185,309 B1 Z2| WOCl HOSSEOOHc] X\HOWEWN T\/NHEILXE ÅHOWEWN U.S. Patent Feb. 27, 2007 Sheet 3 of 15 US 7,185,309 B1 300 (STARD 302 DEFINE MP SYSTEM SPECIFICATION DATAUSINGAPASSOCATED 304 WITHSOFT PLATFORM ARCHITECTURE GENERATE LOGICAL VIEW OF MP SYSTEM IN ACCORDANCE WITH MP 306 SYSTEM SPECIFICATION DATA MAP LOGICAL VIEW ONTO FPGA ARCHITECTURE TO PRODUCE 308 FPGADESIGN DATA PROCESS FPGADESIGN DATA TO PRODUCE CONFIGURATION BITSTREAM 310 DATA LOAD CONFIGURATION BITSTREAM 312 INTO FPGA CEND)-N-314 FIG. 3 U.S. Patent Feb. 27, 2007 Sheet 4 of 15 US 7,185,309 B1 ·LNE|NOCHWOOSSEOOHc] 007 HO_LINOW U.S. Patent US 7,185,309 B1 019 909 909 009 U.S. Patent Feb. 27, 2007 Sheet 6 of 15 US 7,185,309 B1 U.S. Patent Feb. 27, 2007 Sheet 7 of 15 US 7,185,309 B1 7OO (STARD-702 SPECIFY MEMORY SUBSYSTEMUSING 704 MDL GENERATE LOGICAL VIEW OF MEMORY 706 SUBSYSTEM ANALYZE AND/OR OPTIMIZE MEMORY 707 SUBSYSTEM MAP LOGICAL VIEW OF MEMORY SUBSYSTEMONTO FPGAARCHITECTURE 708 TO PRODUCE FPGADESIGN DATA COMBINE FPGADESGN DATA WITH 710 OTHER DESIGN DATA TO DEFINE SYSTEM PROCESS COMBINED FPGADESIGN DATA TO PRODUCE CONFIGURATION BITSTREAM 712 DATA LOAD BITSTREAM INTO FPGA 71.6 U.S. Patent Feb. 27, 2007 Sheet 8 of 15 US 7,185,309 B1 ABSTRACT MEMORY 806 ADDRESSES 808 ABSTRACT TIME 804 800 INTERCONNECT 810 an RESOURCES FIG. 8 U.S. Patent Feb. 27, 2007 Sheet 9 Of 15 US 7,185,309 B1 INCOMING MESSAGE O O O DATA 900 COMPUTATIONAL COMPUTATIONAL COMPUTATIONAL ELEMENT ELEMENT O O O ELEMENT 906 906 906 FIG. 9 1002 10022 1002N NCOMING MESSAGE MEMORY INTERFACE 1004 DATA COMPUTATIONAL COMPUTATIONAL ELEMENT ELEMENT OO6 1 OO6 OOO FIG. 1 O U.S. Patent Feb. 27, 2007 Sheet 10 of 15 US 7,185,309 B1 |'91-' U.S. Patent Feb. 27, 2007 Sheet 12 of 15 US 7,185,309 B1 START IS FINISHED STOP SUSPEND S SUSPENDED CLOCK 1316 1320 1318 FIG. 13 1502 15022 15023 15024 1508 1508 1508 1508 1506 THREAD THREAD THREAD THREAD P 1510 1510 1510 1500 1504 FIG. 15 U.S. Patent Feb. 27, 2007 Sheet 13 of 15 US 7,185,309 B1 1402 14022 1402N THREAD THREAD THREAD MODEL MODEL O O O MODEL 1406- 1408- 14O6- 1408 1406- 1408 INTERCONNECTION COMPONENT 1404 THREAD MODEL FIG. 14 U.S. Patent Feb. 27, 2007 Sheet 14 of 15 US 7,185,309 B1 COP PRIMITIVES SIGNAL GROUPNG PRIMITIVES INTERPROCESS MEREEENT COMMUNICATION PRIMITIVES IMPLEMEMTATION RUN-TIME METRIC PRIMTIVES PRIMITIVES DEBUGGING PRIMITIVES 1604 U.S. Patent Feb. 27, 2007 Sheet 15 of 15 US 7,185,309 B1 SUPPORT CIRCUITS COMPUTER 1704 1700 OUTPUT DEVICE(S) 1711 I/O MEMORY INTERFACE 1703 1702 INPUT DEVICE(S) 1712 FIG. 17 US 7,185,309 B1 1. 2 METHOD AND APPARATUS FOR Another aspect of the invention relates to a design tool for APPLICATION-SPECIFIC PROGRAMMABLE designing a memory system for implementation using an MEMORY ARCHITECTURE AND integrated circuit. An input section is adapted to specify INTERCONNECTION NETWORK ON A CHP attributes of the memory system. A first database stores a memory model defining a memory component and a FIELD OF THE INVENTION memory interconnection component. A second database stores a physical memory configuration associated with the One or more aspects of the present invention relate integrated circuit. A memory model section includes a first generally to integrated circuit design tools and, more par portion and a second portion. The first portion is adapted to ticularly, to a programmable architecture for implementing 10 generate an instance of the memory component and an a message processing System using an integrated circuit. instance of the memory-interconnection component. The second portion is adapted to implement the memory com BACKGROUND OF THE INVENTION ponent instance and the memory-interconnection component instance in terms of memory circuitry and interconnection Programmable logic devices (PLDs) exist as a well 15 circuitry, respectively, of the physical memory configuration known type of integrated circuit (IC) that may be pro to produce a physical view of the memory system. grammed by a user to perform specified logic functions. There are different types of programmable logic devices, BRIEF DESCRIPTION OF THE DRAWINGS Such as programmable logic arrays (PLAS) and complex programmable logic devices (CPLDs). One type of pro Accompanying drawing(s) show exemplary embodiment grammable logic device, known as a field programmable (s) in accordance with one or more aspects of the invention; gate array (FPGA), is very popular because of a Superior however, the accompanying drawing(s) should not be taken combination of capacity, flexibility, time-to-market, and to limit the invention to the embodiment(s) shown, but are COSt. for explanation and understanding only. An FPGA typically includes an array of configurable logic 25 FIG. 1 is a block diagram depicting an exemplary embodi blocks (CLBs) surrounded by a ring of programmable ment of an FPGA coupled to external memory and a input/output blocks (IOBs). The CLBs and IOBs are inter program memory; connected by a programmable interconnect structure. The FIG. 2 is a block diagram depicting an exemplary embodi CLBs, IOBs, and interconnect structure are typically pro ment of a design tool for designing a message processing grammed by loading a stream of configuration data (known 30 system for implementation using an FPGA: as a bitstream) into internal configuration memory cells that FIG.
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