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Compiler - 3 C Coce Mo Processor U.S USOO7310594B1 (12) United States Patent (10) Patent No.: US 7,310,594 B1 Ganesan et al. (45) Date of Patent: Dec. 18, 2007 (54) METHOD AND SYSTEM FOR DESIGNING A 2001/0025363 A1* 9/2001 Ussery et al. .................. T16.1 MULTIPROCESSOR 2003/0023950 A1* 1/2003 Ma et al. ....... ... 717,102 2003/OO37321 A1* 2/2003 Bowen .......... ... T17,149 (75) Inventors: Satish R. Ganesan, Mountain View, 2003.01.10481 A1* 6/2003 Wada et al. ...... ... 717,158 CA (US); Usha Prabhu, Los Gatos, CA 2005/0204348 A1* 9/2005 Horning et al. ............. T17,140 (US); Sundararajarao Mohan, OTHER PUBLICATIONS Sunnyvale, CA (US); Ralph D. Wittig, Menlo Park, CA (US); David W. Dr. Guido Arnout teaches a SystemC Standard, includes a design Bennett, Lafayette, CO (US) implementation in both hardware and software (see pp. 573-577), (2000 IEEE).* Matthew D'Souza teaches an "Embedded Bluetooth Stack imple (73) Assignee: Xilinx, Inc., San Jose, CA (US) mentation with Nios Softcore Processor'. (Oct. 2001).* (*) Notice: Subject to any disclaimer, the term of this David C. Zaretski teaches a “Design and Evaluation of MATLAB patent is extended or adjusted under 35 Functions on FPGAs'. (Master Thesis, Jun. 2001).* U.S.C. 154(b) by 645 days. * cited by examiner Primary Examiner Paul Rodriguez (21) Appl. No.: 10/295,687 Assistant Examiner—Andre Pierre-Louis (22) Filed: Nov. 15, 2002 (74) Attorney, Agent, or Firm—Pablo Meles; LeRoy D. Maunu (51) Int. Cl. G06F 7/50 (2006.01) (57) ABSTRACT (52) U.S. Cl. ................... 703/13; 716/1; 716/4; 716/18: A multiprocessor system (10) includes a plurality of pro 717/100; 717/104; 717/149 cessing engines (14, 16, 18, 20, 22., 32.33 and 35) including (58) Field of Classification Search ................ 717/104, a software processing engine and a hardware processing 717/105,159, 102, 106, 151,140, 149; 716/1, engine implemented on a single silicon device defined by a 716/4, 18; 713/190; 703/13 single programming language and the single programming See application file for complete search history. language tagged with at least one macro. The multiprocessor (56) References Cited system further includes connectivity (37 and 40) between the plurality of processing engines defined by the single U.S. PATENT DOCUMENTS programming language and by the single programming 6,075.935 A * 6/2000 Ussery et al.................. 716/17 language tagged with at least one macro. 6,944,848 B2 * 9/2005 Hartman et al. ............ 717/124 7,039.906 B1* 5/2006 Trelewicz et al. .......... 717/149 24 Claims, 7 Drawing Sheets - 2 Compiler - 3 C COce mo PrOCeSSOr U.S. Patent Dec. 18 , 2007 Sheet 1 of 7 US 7,310,594 B1 l–/ JOSS0001) <-?p00OJossa001)| e??du/00 —/9—/8 ?ZIS???uÁSTOIH ?JeMpJEH9p00 H O TOIH 9p0O I"OIH U.S. Patent Dec. 18, 2007 Sheet 2 of 7 US 7,310,594 B1 COreCOnnect BuS JOSS000Id ?? ??M)9p00 U.S. Patent US 7,310,594 B1 ZIZ()IZ U.S. Patent Dec. 18 9 2007 Sheet 4 of 7 US 7,310,594 B1 ---- (((LIS)LnOTS-ITTIX - (((CIS)LnOTS-ITTIX U.S. Patent Dec. 18 9 2007 Sheet 5 of 7 US 7 9 310,594 B1 ©zelg0101WU] U.S. Patent US 7,310,594 B1 OO s US 7,310,594 B1 1. 2 METHOD AND SYSTEM FOR DESIGNING A “FPGA-based embedded processor SoCs' are a specific MULTIPROCESSOR subset of FPGA-based SoCs with or without their own processors. FIELD OF THE INVENTION The processing modules can either be hardware or soft ware based. This invention relates generally to programmable logic Notwithstanding advantages provided by using FPGA devices, and more particularly to a method and system for based SoCs, the development of these SoCs can be very designing a multiprocessor System using a single program challenging, particularly where software and hardware pro ming language. cessing engines are combined in a single system. Existing 10 systems for designing multiprocessors such as Coware Sys BACKGROUND OF THE INVENTION temC cater to the needs of hardware designers with an emphasis on the detailed mechanics of a particular system. Programmable devices are general-purpose integrated cir Such a system fails to allow a designer to work more in the cuits that can be configured for a wide variety of applica software level of abstraction and fails to allow a user to use tions. Such programmable devices have two basic versions, 15 simple tags to implement different functions on different mask programmable devices, which are programmed only processing engines. In another system, the Celoxica Handel by a manufacturer, and field programmable devices, which C/Xilinx Forge compiler system allows C code to be trans are programmable by the end user. In addition, program lated directly into hardware using parallelizing compiler mable devices can be further categorized as programmable techniques. Rather than translating from C into hardware, memory devices or programmable logic devices. Program there is a need to translate from function to structure where mable memory devices include programmable read only the structure can be hardware or Software processors. memory (PROM), erasable programmable read only One of the other challenges includes communication memory (EPROM) and electronically erasable program among multiple hardware and Software processors embed mable read only memory (EEPROM). Programmable logic ded in a FPGA-based SoC. Typically, such communication devices include programmable logic array (PLA) devices, 25 occurs over a bus. Unfortunately, communication over a bus programmable array logic (PAL) devices, erasable program involves a large amount of overhead due to bus arbitration mable logic devices (EPLD) devices, complex program times. Therefore, several clock cycles are typically needed mable logic devices (CPLD), programmable gate arrays for simple communication among processing modules. Fur (PISA), application specific integrated circuits (ASIC). thermore, the actual links among the processing modules are As chip capacity continues to increase significantly, the 30 not flexible in terms of defining or customizing data sizes use of field programmable gate arrays (FPGAs) is quickly and FIFO sizes. Also, many links among processors are replacing the use of application specific integrated circuits processor type dependent. FPGA based embedded processor (ASICs). An ASIC is a specialized integrated circuit that is SoCs are being introduced into the market, but there are no designed and mask programmed for a particular application Solutions which allow users to customize the system, the Such as a specialized microprocessor. With the shrinkage in 35 hardware and Software processing modules, the links among integrated circuit design rules, FPGAS, which are user the processing modules, and the associated Software, nor is programmable, achieve almost the gate density of factory there a system enabling a user to trade off a function between programmed ASICS. This high gate density has contributed being implemented in hardware (FPGA fabric) or software immensely to the popularity of FPGAs. FPGAs typically (running on the embedded processor). It would be desirable include user configurable input/output blocks (IOBs), and 40 to have a method and system for designing multiprocessor programmable logic blocks, and configurable interconnect systems in FPGA-based SoCs that enables a translation lines, and Switching capability for interconnecting the lines (without resorting to a central processor or other co-proces and programming the blocks. sors) from function to structure including Software and The advancement of computer chip technology has also hardware processors independent of processing module resulted in the development of embedded processors and 45 type, and that further overcomes the shortcomings described controllers. An embedded processor or controller can be a above. microprocessor or microcontroller circuit that has been integrated into an electronic device as opposed to being built SUMMARY OF THE INVENTION as a standalone module or “plug in card.’ Advancement of FPGA technology has led to the development of FPGA 50 In a first aspect of the present invention, a method of based systems-on-chip (SoC) including FPGA-based designing a multiprocessor System using a single program embedded processor SoCs. A SoC is a fully functional ming language comprises the steps of defining at least one product having its electronic circuitry contained on a single of a structure of at least two processing engines and a chip. While a standalone microprocessor chip requires ancil connectivity between the at least two processing engines by lary electronic components to process instructions, a SoC 55 tagging the programming language with a directive and may include all required ancillary electronics on a single compiling the programming language with the directive. integrated circuit chip. For example, a SoC for a cellular In a second aspect of the present invention, a multipro telephone can include a microprocessor, encoder, decoder, cessor System having a plurality of processing engines on a digital signal processor (DSP), RAM and ROM. It should be field programmable gate array based System-on-Chip (SoC) understood when contemplating the present invention that 60 comprises a structure of at least two processing engines an FPGA-Based SoC does not necessarily include a micro defined by a programming language and the programming processor or microcontroller. For example, a SoC for a language tagged with at least one directive and connectivity cellular telephone could include an encoder, decoder, digital between the at least two processing engines defined by the signal processor (DSP), RAM and ROM that rely on an programming language and by the programming language external microprocessor. A SoC could also include multiple 65 tagged with at least one directive. processing modules coupled to each other via a bus or In a third aspect of the present invention, a multiprocessor several busses. It should also be understood herein that system comprises a plurality of processing engines including US 7,310,594 B1 3 4 a software processing engine and a hardware processing is adhered to as much as is possible, because any changes in engine implemented on a single silicon device defined by a this partition may necessitate extensive redesign.
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