MULTICORE SYSTEM ON CHIP ELECTROCARDIOGRAPHY
BY
ALIU SUNDAY JOHN COMPUTER SCIENCE DEPARTMENT AFRICAN UNIVERSITY OF SCIENCE AND TECHNOLOGY, ABUJA NIGERIA
IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE AWARD OF MASTERS OF SCIENCE DEGREE IN COMPUTER SCIENCE AND ENGINEERING
December 2010.
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ABSTRACT
Basically electrocardiography is a commonly used, non-invasive procedure for recording electrical changes in the heart. The record, which is called an electrocardiogram (ECG or EKG), shows the series of waves that relate to the electrical impulses which occur during each beat of the heart. The results are printed on paper or displayed on a monitor. The waves in a normal record are named P, Q, R, S, T, U and follow in alphabetical order. This research exploits the technology of parallel processing to process the electrocardiography computational kernels in parallel. The idea we are presenting is to implement the traditional multi lead bulky electrocardiogram on a programmable chip which is small and more efficient.
The technology is implemented on an FPGA (Target device is Altera Stratix III EP3SL50F484C2) based on Multicore System on Chip. The Logic Utilization for one-lead system which is scalable to multi lead after compilation was 43%, combinational ALUTs 9669/38000 (25%), Memory ALUTs 16/19000
(<1%), Total registers 11583/38000 (30%) and total thermal power dissipation of 463.86mW .
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ACKNOWLEDGEMENT
I want to most importantly acknowledge God for the grace to have sailed through this journey at the African University of Science and Technology in the last 18 months. To God be all the glory. I must also appreciate those behind the idea of African University of Science and Technology and the general administration of the University. They are the giants on whose shoulders I have been standing in AUST.
I must not fail to acknowledge my thesis supervisor Professor Ben Abdallah Abderazek, of the
University of Aizu Japan whose encouragement and support have been most helpful in the production of this thesis work. I deeply thank Professor Ben Abdallah Abderazek, for without him this thesis would not have exixted. I know there are better days ahead for us.
I want to also appreciate every student of the African University of Science and Technology especially the 2009/2010 session. Its been a journey of a lifetime. Years coming till the end of our sojourn
I will continue to remember the great times we had. There has never been such a brotherhood in my history before boarding the AUST flight.
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TABLE OF CONTENTS Page
Title Page …...... 1
Abstract...... 2
Acknowledgement...... 3
Table of Contents...... 7
List of Figures...... 8
List of Tables...... 9
Chapter One: Introduction...... 10
1.0 Introduction...... 10
1.1 Purpose of the research work...... 11
1.2 Background...... 11
1.3 Scope of work...... 12.
Chapter Two: Literature review...... 13
2.0 Electrocardiography and heart disease...... 13
2.1 Digital signal processing...... 17
2.1.1 Analog and digital signals...... 17
2.1.2 Signal processing...... 18
2.1.3 Analog to digital conversion...... 18
2.1.4 Sampling...... 19
2.1.5 Quantization error...... 20
2.1.6 Sampling rate...... 20
2.1.7 Oversampling...... 21
2.1.8 Aliasing...... 21
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2.1.9 ADC structures...... 22
2.1.10 Autocorrelation function...... 27
2.2 Digital filters...... 28
2.2.1 Analysis techniques...... 29
2.2.2 Impulse response...... 30
2.2.3 Difference equation...... 30
2.2.4 Filter design...... 31
2.2.5 Filter realization...... 33
2.2.5.1 Direct form I...... 34
2.2.5.2 Direct form II...... 34
2.3 Programmable Logic Devices...... 35
2.3.1 Programmable Array Logic (PAL)...... 37
2.3.2 Programmable Logic Array (PLA)...... 37
2.3.3 Generic Array Logic (GAL)...... 38
2.3.4 Complex Programmable Logic devices (CPLD)...... 39
2.4 Field Programmable Gate Array (FPGA)...... 40
2.4.1 History of FPGA...... 41
2.4.2 Modern development...... 42
2.4.3 Architecture...... 43
2.4.4 FPGA design and programming...... 45
2.5 Multicore system on chip...... 46
2.5.1 Structure...... 47
2.5.2 Design flow...... 47
2.6 Electronic design automation (EDA) tools...... 49
2.6.1 System on programmable chip (SOPC) builder...... 50
2.6.2 Nios II processor...... 50
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2.6.3 Hardware description Language (HDL)...... 51
Chapter three: Analysis and Design...... 53
3.0 Peak period detection algorithm...... 53
3.1 Period detection...... 53
3.1.1 Reading data...... 54
3.1.2 Derivation...... 55
3.1.3 Autocorrelation...... 60
3.1.4 Finding intervals...... 70
3.2 Digital finite impulse response filter design FIR...... 70
3.3 System architecture...... 71
3.3.1 Reading data section...... 72
3.3.2 Filtering and data analysis section...... 73
3.3.3 Display section...... 74
Chapter four : Implementation and results...... 75
4.0 SOPC builder system generation and quartus II compilation...... 75
4.1 Quartus II compilation of the entire design...... 76
4.2 Nios II IDE implementation of ppd algorithm...... 77
4.3 Results...... 79
4.3.1 Flow Summary...... 79
4.3.2 Analysis and synthesis resources usage summary...... 80
4.3.3 Power analysis summary...... 81
4.3.4 Register transfer logic RTL of design...... 82
Chapter five : Conclusion and Future work...... 84
5.0 Conclusion...... 84
5.1 Future work...... 84
References...... 86
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LIST OF FIGURES
Page
Figure 1. Heart working in normal condition...... 14
Figure 2.A typical ECG waveform...... 15
Figure 3.Picture of the heart showing myocardial infarction...... 15
Figure 4.Picture of the heart showing arterial fibrination...... 16
Figure 5.Picture of the heart showing aortic valve stenosis...... 16
Figure 6. Signal sampling representation...... 19
Figure 7. Direct form I...... 34
Figure 8. Direct form II...... 34
Figure 9. Programmable array logic...... 37
Figure 10. Programmable logic array...... 38
Figure 11. Lattice GAL 16V8 and 20V8...... 38
Figure 12. A Xilinx FPGA development board...... 40
Figure 13. An altera cyclone II FPGA...... 42
Figure 14. Simplified illustration of a logic cell...... 43
Figure 15. Logic block pin location...... 44
Figure 16. A microcontroller based system on chip...... 48
Figure 17. Filtered ECG signal...... 54
Figure 18. Derivative of ECG signal...... 55
Figure 19. A Matlab plot of AFx against L...... 59
Figure 20. Autocorrelation function of derivative...... 60
Figure 21. Finding R peak...... 66
Figure 22. Finding P peak...... 67
Figure 23. Finding T peak...... 67
Figure 24. Finding U peak...... 68
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Figure 25. Finding Q peak...... 69
Figure 26. Finding S peak...... 69
Figure 27. Multicore system on chip electrocardiography...... 70
Figure 28. Data reading section...... 71
Figure 29. Filtering and analysus modules...... 72
Figure 30. Display section...... 73
Figure 31. Complete system design with ADC not shown...... 74
Figure 32. SOPC builder interface...... 75
Figure 33. Quartus II compilation...... 76
Figure 34. NIOS II project creation...... 77
Figure 35. NIOS II building...... 78
Figure 36. Flow summary report...... 79
Figure 37. Analysis and synthesis report...... 80
Figure 38. Power analysis report...... 81
Figure 39. RTL of design...... 82
Figure 40. Prototype of system...... 82
Figure 41. Part of the Technical Map view...... 83
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LIST OF TABLES
Page
Table 1. Twelve Sample for calculation...... 56
Table 2. Result of sample calculations...... 59
Table 3. Flow summary report...... 79
Table 4. Analysis and synthesis usage summary...... 80
Table 5. Power analysis summary report...... 81
.
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CHAPTER 1
INTRODUCTION
1.0 INTRODUCTION
Technology over the years has been a tool that man has employed to make life a better place for habitation. The importance of health to life cannot be over emphasised as it is a common saying that health is wealth. In general our state of health is reflected in our heart beats, blood pressure, body temperature and a whole lot of other parameters. The state of the heart is obviously the most important since it is the power house of a man's life. This research intend to develop a system that will monitor the state of health of a person by analysing input signals from the body system of a person and sending the result to a doctor in a remote location who will examine the analysed body signals and know the state of health of the person in real time. It is a very interesting novelty. You don't have to move here and there to be examined by your doctor. It is a just in time and on the fly medical examination. In Africa and other parts of the world there are some sick or elderly people who have mobility impedance. Such a class of people need not border about mobility as the technology is all about best comfort. Again apart from sick and elderly people every living soul needs this technology. The state of our heart is very important and a lot of people just don't care about the state of their hearts. Its not that they don't want to but considering the stress of going to the hospital, waiting for a doctor and paying for medical examination people are not motivated to go for heart check up. With the technology being proposed heart medicine will experience a great revolution as the boundaries of engineering are pushed beyond the limit. The technology will be implemented on an FPGA. At a very high level of abstraction the system will accept input signals from the user (like the probes of an ECG) but in this case in-body and then pass the signal through an analog to digital converter (ADC). The result from the ADC is then filtered by passing it through a filter. Then to memory. The resulting output is fed to EGC analyser for analysis of the filtered signal to generate appropriate waveforms that reflect the state of health of the heart of the patient. The ECG analyses is 10 performed by the algorithms known as the peak period detection algorithm. The intention is that the result is then displayed on screen and routed to a doctor in some remote location who will do the necessary prescription, but in this report the hardware design and compilation is done using the quartus II CAD
(Computer aided design) tool with the included SOPC(System on programmable chip) builder and then the software programming is done using the NIOS II eclipse IDE for programming the NIOS II soft processors in the work. The completed design is not downloaded to a DSP FPGA instead the results of compilation from the CAD tools are shown.
1.1 PURPOSE OF THE RESEARCH WORK
The purpose of this reseach work is to design and implement an electrocardiogram on chip using multicore system on chip technology exploiting parallel processing technology in processing the ECG computational kernel. The entire ECG system is implemented on a DSP FPGA chip thus drastically reducing the size of the traditional bulky ECG and at the same time improving accuracy and efficiency.
This is a great novelty as the result of the research will greatly improve the ECG system and health of the people expecially elderly people and in developing countries with special focus on Africa.
1.2 BACKGROUND
As the importance of heart medicine cannot be overemphasised there have been lots of research in the field of electrocardiography. With the advancement in system on chip technologies there has been a concerted research move to change the paradym od the traditional bulky ECG implementation to a complete system on chip implementation. Research work have been on in MIT, havard code blue project, and very importantly in the Adaptive Systems Laboratory School of Computer Science and Engineering,
The University of Aizu under the umbrella of the BANSMOM project. What we are aiming at in this research is to bend the beam of such research towards an African terrain.
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1.3 SCOPE OF WORK
The work entails the design and implementation of an ECG system on chip including both the hardware and software architecture. The system hardware is designed with the Quartus II EDA design tool and the integrated SOPC builder tool. The peak period detection algorithm is implemented in software in
C programming language with the aid of the NIOS II Integrated development environment. The hardware design is for a one – lead ECG system which is scalable to a multi lead system.
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CHAPTER 2
LITERATURE REVIEW
2.0 ELECTROCARDIOGRAPHY AND HEART DISEASES
The term electrocardiography is better known as an ECG, but is also called EKG which is the abbreviation for electrocardiogram. This technique is used to record the electrical impulses which immediately precede the contractions of the heart muscle. This method causes no discomfort to a patient and is often used for diagnosing heart disorders such as coronary heart disease, pericarditis or inflammation of the membrane around the heart, cardiomyopathy or heart muscle disease, arrhythmia and coronary thrombosis. When using this technique doctors will connect electrodes to the chest, wrist and ankles that are connected to a recording machine. This machine will display the electrical activity in the heart as a trace on a rolling graph or screen. Using the electrocardiography any abnormalities are revealed to the doctor. This technique can be taken at a doctor's office, hospital or even at home and will provide your doctor with a 24 hour record of the patients heart activity from a tape recorder that is worn by the patient doctors can look at the printed graph to see if the heart chambers are contracting with complete regularity which indicates a normal rhythm. If the contractions of the lower heart chambers are extremely irregular this could indicate ventricular fibrillation. When the upper and lower heart chambers are beating independently this could indicate a complete heart blockage. If the upper heart chambers are beating fast and irregular, this can indicate arterial fibrillation. The electrocardiography is a painless and quick procedure. The electrical impulses in the heart are recorded and amplified on a moving strip of paper which allows a doctor or analyze what is known as the pace maker of the heart which is the part that triggers each heart beat, the rate, rhythm and nerve conduction pathways of the heart. Small metal contacts or what are called electrodes are placed on the skin of the patient to measure the flow and direction of the electrical currents in the heart during each heart beat. Each of the electrodes are connected by a wire to a machine that will produce what is called a tracing for each electrode. This tracing represents a particular
13 view or what is called lead of the heart's electrical patterns. In most cases any person who is suspected of having heart disease will have an ECG taken by their doctor. This will aid the doctor in identifying a number of heart problems such as abnormal heart rhythms, excessive thickening of the heart muscle or what is known as hypertrophy and results from high blood pressure inadequate blood supply to the heart, inadequate oxygen supply to the heart, and a thin or absent heart muscle which has resulted because it has been replaced by non-muscular tissue.
An electrocardiography produces waves that are known as the P, Q, R, S, T and U waves which gives each part of the ECG an alphabetical designation. As the heart beat begins with an impulse from the senatorial node which is also known as the main pace maker, the impulse will first activate the upper chambers of the heart or atria and produce the P wave. Then the electrical current will flow down to the lower chambers of the heart or ventricles producing the Q, R and S waves. As the electrical current spreads back over the ventricles in the opposite direction it will produce the T waves. Using this technique doctors can determine where in the heart abnormal rhythms start which allows them to begin to determine the cause. A picture of the heart in a normal working condition is shown
Figure 1. Heart working in normal condition.
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Also below is a typical ECG waveform
Figure 2. A typical ECG waveform
some heart diseases
• Myocardial infartion
Figure 3. Picture of the heart showing Myocardial infartion
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• Atrial fibrillation
Figure 4. Picture of the heart showing Atrial fibrillation condition.
• Aortic Valve Stenosis
Figure 5. Picture of the heart showing Aortic Valve Stenosis condition.
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2.1 DIGITAL SIGNAL PROCESSING
Digital signal processing has been with us for decades now with some astronomical development in the area over the years. The world of science and engineering is filled with signals: images from remote space probes, voltages generated by the heart and brain, radar and sonar echoes, seismic vibrations, and countless other applications. Digital Signal Processing is the science of using computers to understand these types of data. This includes a wide variety of goals: filtering, speech recognition, image enhancement, data compression, neural networks, and much more. DSP is one of the most powerful technologies that will shape science and engineering in the twenty-first century. DSP, or Digital Signal
Processing, as the term suggests, is the processing of signals by digital means. A signal in this context can mean a number of different things. Historically the origins of signal processing are in electrical engineering, and a signal here means an electrical signal carried by a wire or telephone line, or perhaps by a radio wave. More generally, however, a signal is a stream of information representing anything from stock prices to data from a remote-sensing satellite. A digital signal consists of a stream of numbers, usually (but not necessarily) in binary form. The processing of a digital signal is done by performing numerical calculations.
2.1.1 ANALOG AND DIGITAL SIGNALS In many cases, the signal of interest is initially in the form of an analog electrical voltage or current, produced for example by a microphone or some other type of transducer. In some situations, such as the output from the readout system of a CD (compact disc) player, the data is already in digital form.
An analog signal must be converted into digital form before DSP techniques can be applied. An analog electrical voltage signal, for example, can be digitised using an electronic circuit called an analog-to- digital converter or ADC. This generates a digital output as a stream of binary numbers whose values represent the electrical voltage input to the device at each sampling instant.
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2.1.2 SIGNAL PROCESSING Signals commonly need to be processed in a variety of ways. For example, the output signal from a transducer may well be contaminated with unwanted electrical "noise". The electrodes attached to a patient's chest when an ECG is taken measure tiny electrical voltage changes due to the activity of the heart and other muscles. The signal is often strongly affected by "mains pickup" due to electrical interference from the mains supply. Processing the signal using a filter circuit can remove or at least reduce the unwanted part of the signal. Increasingly nowadays, the filtering of signals to improve signal quality or to extract important information is done by DSP techniques rather than by analog electronics.
2.1.3 ANALOG TO DIGITAL CONVERSION Signals in the real world are analog: light, sound,heart signal. So, real-world signals must be converted into digital, using a circuit called analog to digital conversion, before they can be manipulated by digital equipment. Scanning a picture for example with a scanner is doing is an analog-to-digital conversion: The scanner is taking the analog information provided by the picture (light) and converting into digital. When voice is recorded or a VoIP solution is used on the computer, an analog-to-digital conversion takes place to convert voice, which is analog, into digital information. Digital information isn’t only restricted to computers. For talk on the phone, for example, voice is converted into digital since voice is analog and the communication between the phone switches is done digitally. When an audio CD is recorded at a studio, analog-to-digital conversion is taking place, converting sounds into digital numbers that will be stored on the disc. To get the analog signal back, the opposite conversion – digital-to-analog, which is done by a circuit called DAC, Digital-to-Analog Converter – is needed. Playing an audio CD, what the CD player is doing is reading digital information stored on the disc and converting it back to analog so that the music can be heard. Talking on the phone, a digital-to-analog conversion is also taking place at the receving end so that the recipient can get the call. There are some basic reasons to use digital signals instead of analog, noise being the number one. Since analog signals can assume any value, noise is interpreted as being part of the original signal. Digital systems, on the other hand, can only understand two numbers, zero and one. Anything different from this is discarded. Basically Analog-to-digital
18 conversion is an electronic process in which a continuously variable (analog) signal is changed, without altering its es sential content, into a multi -level (digital)signal.The input to an analog -to-digital converter
(ADC) consists of a voltage that varies among a theoretically infinite number of values. Examples are sine waves, the waveforms representing human speech, heart signals and the signals from a conventional television camera. The output of the ADC, in contrast, has defined levels or states. The number of states is almost always a power of two -- that is, 2, 4, 8, 16, etc. The simplest digital signals have only two states, and are called binary. All whole numbers can be represented in binary form as strings of ones and zeros.
Digital signals propagate more efficiently than analog signals, largely because digital impulses, which are well-defined and orderly, are easie r for electronic circuits to distinguish from noise, which is chaotic. This is the chief advantage of digital modes in communications. Computers "talk" and "think" in terms of binary digital data; while a microprocessor can analyze analog data, it must be converted into digital form for the computer to make sense of it.
2.1.4 SAMPLING In signal processing, sampling is the reduction of a continuous signal to a discrete signal. A common example is the conversion of a sound wave (a continuous -time signal) to a sequence of samples
(a discrete-time signal). A sample refers to a value or set of values at a point in time and/or space. A sampler is a subsystem or operation that extracts samples from a continuous signal. A theoretical ideal sampler produces samples e quivalent to the instantaneous value of the continuous signal at the desired points.
Figure 6. Signal sampling representation
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2.1.5 QUANTIZATION ERROR Quantization error is due to the finite resolution of the ADC, and is an unavoidable imperfection in all types of ADC. The magnitude of the quantization error at the sampling instant is between zero and half of one LSB (least significant bit). In the general case, the original signal is much larger than one LSB.
When this happens, the quantization error is not correlated with the signal, and has a uniform distribution.
Its RMS value is the standard deviation of this distribution, given by 0.289. At lower levels the quantizing error becomes dependent of the input signal, resulting in distortion. This distortion is created after the anti-aliasing filter, and if these distortions are above 1/2 the sample rate they will alias back into the audio band. In order to make the quantizing error independent of the input signal, noise with an amplitude of 2 least significant bits is added to the signal. This slightly reduces signal to noise ratio, but, ideally, completely eliminates the distortion. It is known as dither.
2.1.6 SAMPLING RATE The analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called the sampling rate or sampling frequency of the converter. A continuously varying bandlimited signal can be sampled (that is, the signal values at intervals of time T, the sampling time, are measured and stored) and then the original signal can be exactly reproduced from the discrete-time values by an interpolation formula. The accuracy is limited by quantization error.
However, this faithful reproduction is only possible if the sampling rate is higher than twice the highest frequency of the signal. This is essentially what is embodied in the Shannon-Nyquist sampling theorem.
Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constant during the time that the converter performs a conversion (called the conversion time). An input circuit called a sample and hold performs this task—in most cases by using a capacitor to store the analog voltage at the input, and using an electronic switch or gate to disconnect the capacitor from the input.
Many ADC integrated circuits include the sample and hold subsystem internally.
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2.1.7 OVERSAMPLING Usually, signals are sampled at the minimum rate required, for economy, with the result that the quantization noise introduced is white noise spread over the whole pass band of the converter. If a signal is sampled at a rate much higher than the Nyquist frequency and then digitally filtered to limit it to the signal bandwidth then there are three main advantages:
• digital filters can have better properties (sharper rolloff, phase) than analogue filters, so a sharper
anti-aliasing filter can be realised and then the signal can be downsampled giving a better result
• a 20-bit ADC can be made to act as a 24-bit ADC with 256× oversampling
• The signal-to-noise ratio due to quantization noise will be higher than if the whole available band
had been used. With this technique, it is possible to obtain an effective resolution larger than that
provided by the converter alone
• The improvement in SNR (signal to noise ratio) is 3dB (equivalent to 0.5 bits) per octave of
oversampling which is not sufficient for many applications. Therefore, oversampling is usually
coupled with noise shaping . With noise shaping, the improvement is 6L+3 dB per octave where L
is the order of loop filter used for noise shaping.
2.1.8 ALIASING All ADCs work by sampling their input at discrete intervals of time. Their output is therefore an incomplete picture of the behaviour of the input. There is no way of knowing, by looking at the output, what the input was doing between one sampling instant and the next. If the input is known to be changing slowly compared to the sampling rate, then it can be assumed that the value of the signal between two sample instants was somewhere between the two sampled values. If, however, the input signal is changing rapidly compared to the sample rate, then this assumption is not valid. If the digital values produced by
21 the ADC are, at some later stage in the system, converted back to analog values by a digital to analog converter or DAC, it is desirable that the output of the DAC be a faithful representation of the original signal. If the input signal is changing much faster than the sample rate, then this will not be the case, and spurious signals called aliases will be produced at the output of the DAC. The frequency of the aliased signal is the difference between the signal frequency and the sampling rate. For example, a 2 kHz sine wave being sampled at 1.5 kHz would be reconstructed as a 500 Hz sine wave. This problem is called aliasing. To avoid aliasing, the input to an ADC must be low-pass filtered to remove frequencies above half the sampling rate. This filter is called an anti-aliasing filter, and is essential for a practical ADC system that is applied to analog signals with higher frequency content. Although aliasing in most systems is unwanted, it should also be noted that it can be exploited to provide simultaneous down-mixing of a band-limited high frequency signal.
2.1.9 ADC STRUCTURES These are the most common ways of implementing an electronic ADC:
• A direct conversion ADC or flash ADC has a bank of comparators sampling the input signal in
parallel, each firing for their decoded voltage range. The comparator bank feeds a logic circuit that
generates a code for each voltage range. Direct conversion is very fast, capable of gigahertz
sampling rates, but usually has only 8 bits of resolution or fewer, since the number of comparators
needed, 2N - 1, doubles with each additional bit, requiring a large expensive circuit. ADCs of this
type have a large die size, a high input capacitance, high power dissipation, and are prone to
produce glitches on the output (by outputting an out-of-sequence code). Scaling to newer
submicrometre technologies does not help as the device mismatch is the dominant design
limitation. They are often used for video, wideband communications or other fast signals in optical
storage.
• A successive-approximation ADC uses a comparator to reject ranges of voltages, eventually
settling on a final voltage range. Successive approximation works by constantly comparing the 22
input voltage to the output of an internal digital to analog converter (DAC, fed by the current value
of the approximation) until the best approximation is achieved. At each step in this process, a
binary value of the approximation is stored in a successive approximation register (SAR). The
SAR uses a reference voltage (which is the largest signal the ADC is to convert) for comparisons.
For example if the input voltage is 60 V and the reference voltage is 100 V, in the 1st clock cycle,
60 V is compared to 50 V (the reference, divided by two. This is the voltage at the output of the
internal DAC when the input is a '1' followed by zeros), and the voltage from the comparator is
positive (or '1') (because 60 V is greater than 50 V). At this point the first binary digit MSB (most
significant bit) is set to a '1'. In the 2nd clock cycle the input voltage is compared to 75 V (being
halfway between 100 and 50 V: This is the output of the internal DAC when its input is '11'
followed by zeros) because 60 V is less than 75 V, the comparator output is now negative (or '0').
The second binary digit is therefore set to a '0'. In the 3rd clock cycle, the input voltage is
compared with 62.5 V (halfway between 50 V and 75 V: This is the output of the internal DAC
when its input is '101' followed by zeros). The output of the comparator is negative or '0' (because
60 V is less than 62.5 V) so the third binary digit is set to a 0. The fourth clock cycle similarly
results in the fourth digit being a '1' (60 V is greater than 56.25 V, the DAC output for '1001'
followed by zeros). The result of this would be in the binary form 1001. This is also called bit-
weighting conversion, and is similar to a binary search. The analogue value is rounded to the
nearest binary value below, meaning this converter type is mid-rise (see above). Because the
approximations are successive (not simultaneous), the conversion takes one clock-cycle for each
bit of resolution desired. The clock frequency must be equal to the sampling frequency multiplied
by the number of bits of resolution desired. For example, to sample audio at 44.1 kHz with 32 bit
resolution, a clock frequency of over 1.4 MHz would be required. ADCs of this type have good
resolutions and quite wide ranges. They are more complex than some other designs.
• A ramp-compare ADC produces a saw-tooth signal that ramps up or down then quickly returns to
zero. When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a 23
comparator fires, and the timer's value is recorded. Timed ramp converters require the least
number of transistors. The ramp time is sensitive to temperature because the circuit generating the
ramp is often just some simple oscillator. There are two solutions: use a clocked counter driving a
DAC and then use the comparator to preserve the counter's value, or calibrate the timed ramp. A
special advantage of the ramp-compare system is that comparing a second signal just requires
another comparator, and another register to store the voltage value. A very simple (non-linear)
ramp-converter can be implemented with a microcontroller and one resistor and capacitor . Vice
versa, a filled capacitor can be taken from an integrator, time-to-amplitude converter, phase
detector, sample and hold circuit, or peak and hold circuit and discharged. This has the advantage
that a slow comparator cannot be disturbed by fast input changes.
• The Wilkinson ADC was designed by D. H. Wilkinson in 1950. The Wilkinson ADC is based on
the comparison of an input voltage with that produced by a charging capacitor. The capacitor is
allowed to charge until its voltage is equal to the amplitude of the input pulse. (A comparator
determines when this condition has been reached.) Then, the capacitor is allowed to discharge
linearly, which produces a ramp voltage. At the point when the capacitor begins to discharge, a
gate pulse is initiated. The gate pulse remains on until the capacitor is completely discharged. Thus
the duration of the gate pulse is directly proportional to the amplitude of the input pulse. This gate
pulse operates a linear gate which receives pulses from a high-frequency oscillator clock. While
the gate is open, a discrete number of clock pulses pass through the linear gate and are counted by
the address register. The time the linear gate is open is proportional to the amplitude of the input
pulse, thus the number of clock pulses recorded in the address register is proportional also.
Alternatively, the charging of the capacitor could be monitored, rather than the discharge.
• An integrating ADC (also dual-slope or multi-slope ADC) applies the unknown input voltage to
the input of an integrator and allows the voltage to ramp for a fixed time period (the run-up
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period). Then a known reference voltage of opposite polarity is applied to the integrator and is
allowed to ramp until the integrator output returns to zero (the run-down period). The input voltage
is computed as a function of the reference voltage, the constant run-up time period, and the
measured run-down time period. The run-down time measurement is usually made in units of the
converter's clock, so longer integration times allow for higher resolutions. Likewise, the speed of
the converter can be improved by sacrificing resolution. Converters of this type (or variations on
the concept) are used in most digital voltmeters for their linearity and flexibility.
• A delta-encoded ADC or Counter-ramp has an up-down counter that feeds a digital to analog
converter (DAC). The input signal and the DAC both go to a comparator. The comparator controls
the counter. The circuit uses negative feedback from the comparator to adjust the counter until the
DAC's output is close enough to the input signal. The number is read from the counter. Delta
converters have very wide ranges, and high resolution, but the conversion time is dependent on the
input signal level, though it will always have a guaranteed worst-case. Delta converters are often
very good choices to read real-world signals. Most signals from physical systems do not change
abruptly. Some converters combine the delta and successive approximation approaches; this works
especially well when high frequencies are known to be small in magnitude.
• A pipeline ADC (also called subranging quantizer) uses two or more steps of subranging. First, a
coarse conversion is done. In a second step, the difference to the input signal is determined with a
digital to analog converter (DAC). This difference is then converted finer, and the results are
combined in a last step. This can be considered a refinement of the successive approximation ADC
wherein the feedback reference signal consists of the interim conversion of a whole range of bits
(for example, four bits) rather than just the next-most-significant bit. By combining the merits of
the successive approximation and flash ADCs this type is fast, has a high resolution, and only
requires a small die size.
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• A Sigma-Delta ADC (also known as a Delta-Sigma ADC) oversamples the desired signal by a
large factor and filters the desired signal band. Generally, a smaller number of bits than required
are converted using a Flash ADC after the filter. The resulting signal, along with the error
generated by the discrete levels of the Flash, is fed back and subtracted from the input to the filter.
This negative feedback has the effect of noise shaping the error due to the Flash so that it does not
appear in the desired signal frequencies. A digital filter (decimation filter) follows the ADC which
reduces the sampling rate, filters off unwanted noise signal and increases the resolution of the
output (sigma-delta modulation, also called delta-sigma modulation).
• A Time-interleaved ADC uses M parallel ADCs where each ADC sample data every M:th cycle of
the effective sample clock. The result is that the sample rate is increased M times compared to
what each individual ADC can manage. In practice, the individual differences between the M
ADCs degrade the overall performance reducing the SFDR. However, technologies exist to correct
for these time-interleaving mismatch errors.
• An ADC with intermediate FM stage first uses a voltage-to-frequency converter to converts the
desired signal into an oscillating signal with a frequency proportional to the voltage of the desired
signal, and then uses a frequency counter to convert that frequency into a digital count
proportional to the desired signal voltage. Longer integration times allow for higher resolutions.
Likewise, the speed of the converter can be improved by sacrificing resolution. The two parts of
the ADC may be widely separated, with the frequency signal passed through a opto-isolator or
transmitted wirelessly. Some such ADCs use sine wave or square wave frequency modulation;
others use pulse-frequency modulation. Such ADCs were once the most popular way to show a
digital display of the status of a remote analog sensor.
26
There can be other ADCs that use a combination of electronics and other technologies:
• A Time-stretch analog-to-digital converter (TS-ADC) digitizes a very wide bandwidth analog
signal, that cannot be digitized by a conventional electronic ADC, by time-stretching the signal
prior to digitization. It commonly uses a photonic preprocessor frontend to time-stretch the signal,
which effectively slows the signal down in time and compresses its bandwidth. As a result, an
electronic backend ADC, that would have been too slow to capture the original signal, can now
capture this slowed down signal. For continuous capture of the signal, the frontend also divides the
signal into multiple segments in addition to time-stretching. Each segment is individually digitized
by a separate electronic ADC. Finally, a digital signal processor rearranges the samples and
removes any distortions added by the frontend to yield the binary data that is the digital
representation of the original analog signal.
2.1.10 AUTOCORRELATION FUNCTION
Autocorrelation refers to the correlation of a time series with its own past and future values.
Autocorrelation is also sometimes called “lagged correlation” or “serial correlation”, which refers to the correlation between members of a series of numbers arranged in time. Positive autocorrelation might be considered a specific form of “persistence”, a tendency for a system to remain in the same state from one observation to the next. For example, the likelihood of tomorrow being rainy is greater if today is rainy than if today is dry. Geophysical time series are frequently autocorrelated because of inertia or carryover processes in the physical system. For example, the slowly evolving and moving low pressure systems in the atmosphere might impart persistence to daily rainfall. Or the slow drainage of groundwater reserves might impart correlation to successive annual flows of a river. Or stored photosynthates might impart correlation to successive annual values of tree-ring indices. Autocorrelation complicates the application of statistical tests by reducing the effective sample size. Autocorrelation can also complicate the identification of significant covariance or correlation between time series (e.g., precipitation with a tree- ring series). Autocorrelation implies that a time series is predictable, probabilistically, as future values are
27 correlated with current and past values. Three tools for assessing the autocorrelation of a time series are
• the time series plot • the lagged scatterplot • the autocorrelation function.
In digital dignal processing Autocorrelation is the correlation of a signal with itself. Informally, it is the similarity between observations as a function of the time separation between them. It is a mathematical tool for finding repeating patterns, such as the presence of a periodic signal which has been buried under noise, or identifying the missing fundamental frequency in a signal implied by its harmonic frequencies. It is often used in signal processing for analyzing functions or series of values, such as time domain signals.
In signal processing the autocorrelation function is normalized by mean and variance, and it is sometimes referred to as the autocorrelation coefficient.
The above definitions work for signals that are square integrable, or square summable, that is, of finite energy. Signals that "last forever" are treated instead as random processes, in which case different definitions are needed, based on expected values. For wide-sense-stationary random processes the autocorrelations are defined as
n= ∞
AF x[ k ]= ∑ x[ n]× x[ n− k ] n= − ∞ (1)
2.2 DIGITAL FILTERS In electronics, computer science and mathematics, a digital filter is a system that performs mathematical operations on a sampled, discrete-time signal to reduce or enhance certain aspects of that signal. This is in contrast to the other major type of electronic filter, the analog filter, which is an electronic circuit operating on continuous-time analog signals. An analog signal may be processed by a digital filter by first being digitized and represented as a sequence of numbers, then manipulated mathematically, and then reconstructed as a new analog signal (see digital signal processing). In an analog filter, the input signal is "directly" manipulated by the circuit.
A digital filter system usually consists of an analog-to-digital converter to sample the input signal, followed by a microprocessor and some peripheral components such as memory to store data and filter 28 coefficients etc. Finally a digital-to-analog converter to complete the output stage. Program Instructions
(software) running on the microprocessor implement the digital filter by performing the necessary mathematical operations on the numbers received from the ADC. In some high performance applications, an FPGA or ASIC is used instead of a general purpose microprocessor, or a specialized DSP with specific paralleled architecture for expediting operations such as filtering.
Digital filters may be more expensive than an equivalent analog filter due to their increased complexity, but they make practical many designs that are impractical or impossible as analog filters. Since digital filters use a sampling process and discrete-time processing, they experience latency (the difference in time between the input and the response), which is almost irrelevant in analog filters.
A digital filter is characterized by its transfer function, or equivalently, its difference equation.
Mathematical analysis of the transfer function can describe how it will respond to any input. As such, designing a filter consists of developing specifications appropriate to the problem (for example, a second- order low pass filter with a specific cut-off frequency), and then producing a transfer function which meets the specifications. The transfer function for a linear, time-invariant, digital filter can be expressed as a transfer function in the Z-domain; if it is causal, then it has the form shown in equation 2 below:
(2) where the order of the filter is the greater of N or M.
2.2.1 ANALYSIS TECHNIQUES
A variety of mathematical techniques may be employed to analyze the behaviour of a given digital filter. Many of these analysis techniques may also be employed in designs, and often form the basis of a filter specification. Typically, one analyzes filters by calculating how the filter will respond to a simple input such as an impulse response. One can then extend this information to visualize the filter's response to more complex signals. Riemann spheres have been used, together with digital video, for this purpose.
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2.2.2 IMPULSE RESPONSE The impulse response, often denoted h[k] or hk, is a measurement of how a filter will respond to the Kronecker delta function. For example, given a difference equation, one would set x0 = 1 and xk = 0 for and evaluate. The impulse response is a characterization of the filter's behaviour. Digital filters are typically considered in two categories: infinite impulse response (IIR) and finite impulse response
(FIR). In the case of linear time-invariant FIR fil ters, the impulse response is exactly equal to the sequence of filter coefficients:
(3) IIR filters on the other hand are recursive, with the output depending on both current and pre vious inputs as well as previous outputs. The general form of the an IIR filter is thus:
(4)
Plotting the impulse response will reveal how a filter will respond to a sudden, momentary disturbance.
2.2.3 DIFFERENCE EQUATION In discrete-time systems, the digital filter is often implemented by converting the transfer function
to a linear constant-coefficient difference equation (LCCD) via the Z -transform. The discrete
frequency-domain tr ansfer function is written as the ratio of two polynomials. For example:
(5)
This is expanded:
(6)
and divided by the highest order of z: 30
(7)
The coefficients of the denominator, a k, are the 'feed-backward' coefficients and the coefficients of
the numerator are the 'feed-forward' coefficients, b k. The resultant linear difference equation is:
(8)
or, for the example above:
(9)
rearranging terms:
(10)
then by taking the inverse z-transform:
(11)
and finally, by solving for y[n]:
(12)
This equation shows how to compute the next output sample, y[n], in terms of the past outputs,
y[n − p], the present input, x[n], and the past inputs, x[n − p]. Applying the filter to an input in this
form is equivalent to a Direct Form I or II realization, depending on the exact order of evaluation.
2.2.4 FILTER DESIGN The design of digital filters is a deceptively complex topic. Although filters are easily understood and calculated, the practical challenges of their design and implementation are significant and are the
31 subject of much advanced research.There are two categories of digital filter: the recursive filter and the nonrecursive filter. These are often referred to as infinite impulse response (IIR) filters and finite impulse response (FIR) filters, respectively. Filters are used to allow signals of certain frequencies to pass and block unwanted frequencies. Broadly there are analog filters and digital signals. Digital filters are used to filter digital signals. The digital signals are obtained from an analog to digital converter. Digital filters are designed digitally as it were by mathematical manipulations. Some advantages of digital filters over analog filters are
• A digital filter is programmable , i.e. its operation is determined by a program stored in the
processor's memory. This means the digital filter can easily be changed without affecting the
circuitry (hardware). An analog filter can only be changed by redesigning the filter circuit.
• Digital filters are easily designed, tested and implemented on a general-purpose computer or
workstation.
• The characteristics of analog filter circuits (particularly those containing active components) are
subject to drift and are dependent on temperature. Digital filters do not suffer from these problems,
and so are extremely stable with respect both to time and temperature.
• Unlike their analog counterparts, digital filters can handle low frequency signals accurately. As the
speed of DSP technology continues to increase, digital filters are being applied to high frequency
signals in the RF (radio frequency) domain, which in the past was the exclusive preserve of analog
technology.
• Digital filters are very much more versatile in their ability to process signals in a variety of ways;
this includes the ability of some types of digital filter to adapt to changes in the characteristics of
the signal.
There are various kinds of digital filters. These are :
• Low pass filters
• High Pass filters
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• Band Pass filters
• Notch filter
In this thesis the idea is to design a bandpass filter since signals from the heart have a range of
frequencies. The bandpass filter is designed by cascading a low pass filter and a high pass
filter. The lowpass filter allows the frequencies lower than the cut off frequency and rejects
higher frequencies, while the high pass filter on the other hand allows frequencies higher than
the cut off frequency to pass while attenuating lower frequencies. By a linear combination of
both filters a bandpass filter a bandpass filter is obtained that allows the required frequencies to
pass through the filter. By this ingenious design other frequencies arising from noise in the
environment and baseline wanders are eliminated.
In general a digital filter is characterised mathematically by what is known as the difference
equation. The difference equation is a formula for computing an output sample at time n based
on past and present input samples and past output samples in the time domain.
2.2.5 FILTER REALIZATION After a filter is designed, it must be realized by developing a signal flow diagram that describes the filter in terms of operations on sample sequences. A given transfer function may be realized in many ways.
Consider how a simple expression such as ax + bx + c could be evaluated – one could also compute the equivalent x(a + b) + c. In the same way, all realizations may be seen as "factorizations" of the same transfer function, but different realizations will have different numerical properties. Specifically, some realizations are more efficient in terms of the number of operations or storage elements required for their implementation, and others provide advantages such as improved numerical stability and reduced round- off error. Some structures are more optimal for fixed-point arithmetic and others may be more optimal for floating-point arithmetic.
2.2.5.1 DIRECT FORM I
A straightforward approach for IIR filter realization is Direct Form I, where the difference equation is 33 evaluated directly. This form is practical for small filters, but may be inefficient and impractical
(numerically unstable) for complex designs. In general, this form requires 2N delay elements (for both input and output signals) for a filter of order N.
Figure 7. Direct Form 1
2.2.5.2 DIRECT FORM II
The alternate Direct Form II only needs N delay units, where N is the order of the filter – potentially half as much as Direct Form I. This structure is obtained by reversing the order of the numerator and denominator sections of Direct Form I, since they are in fact two linear systems, and the commutativity property applies. Then, one will notice that there are two columns of delays (z − 1) that tap off the center net, and these can be combined since they are redundant, yielding the implementation as shown below. The disadvantage is that Direct Form II increases the possibility of arithmetic overflow for filters of high Q or resonance. It has been shown that as Q increases, the round-off noise of both direct form topologies increases without bounds.This is because, conceptually, the signal is first passed through an all-pole filter (which normally boosts gain at the resonant frequencies) before the result of that is saturated, then passed through an all-zero filter (which often attenuates much of what the all-pole half amplifies).
Figure 8. Direct form I
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2.3 PROGRAMMABLE LOGIC DEVICES
A programmable logic device or PLD is an electronic component used to build reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be used in a circuit it must be programmed, that is, reconfigured. Before PLDs were invented, read-only memory (ROM) chips were used to create arbitrary combinational logic functions of a number of inputs. Consider a ROM with m inputs (the address lines) and n outputs (the data lines). When used as a memory, the ROM contains 2m words of n bits each. Now imagine that the inputs are driven not by an m-bit address, but by m independent logic signals.
Theoretically, there are 2m possible Boolean functions of these m signals, but the structure of the ROM allows just 2n of these functions to be produced at the output pins. The ROM therefore becomes equivalent to n separate logic circuits, each of which generates a chosen function of the m inputs.
The advantage of using a ROM in this way is that any conceivable function of the m inputs can be made to appear at any of the n outputs, making this the most general-purpose combinational logic device available. Also, PROMs (programmable ROMs), EPROMs (ultraviolet-erasable PROMs) and EEPROMs
(electrically erasable PROMs) are available that can be programmed using a standard PROM programmer without requiring specialised hardware or software. However, there are several disadvantages:
• They are usually much slower than dedicated logic circuits,
• They cannot necessarily provide safe "covers" for asynchronous logic transitions so the PROM's outputs may glitch as the inputs switch,
• They consume more power,
• They are often more expensive than programmable logic, especially if high speed is required.
Since most ROMs do not have input or output registers, they cannot be used stand-alone for sequential logic. An external TTL register was often used for sequential designs such as state machines. Common
EPROMs, for example the 2716, are still sometimes used in this way by hobby circuit designers, who often have some lying around. This use is sometimes called a 'poor man's PAL.
In 1969, Motorola offered the XC157, a mask-programmed gate array with 12 gates and 30 35 uncommitted input/output pins. In 1970, Texas Instruments developed a mask-programmable IC based on the IBM read-only associative memory or ROAM. This device, the TMS2000, was programmed by altering the metal layer during the production of the IC. The TMS2000 had up to 17 inputs and 18 outputs with 8 JK flip flop for memory. TI coined the term Programmable Logic Array for this device.
In 1973 National Semiconductor introduced a mask-programmable PLA device (DM7575) with 14 inputs and 8 outputs with no memory registers. This was more popular than the TI part but cost of making the metal mask limited its use. The device is significant because it was the basis for the field programmable logic array produced by Signetics in 1975, the 82S100. (Intersil actually beat Signetics to market but poor yield doomed their part.) In 1971, General Electric Company (GE) was developing a programmable logic device based on the new PROM technology. This experimental device improved on
IBM's ROAM by allowing multilevel logic. Intel had just introduced the floating-gate UV erasable PROM so the researcher at GE incorporated that technology. The GE device was the first erasable PLD ever developed, predating the Altera EPLD by over a decade. GE obtained several early patents on programmable logic devices.
In 1974 GE entered into an agreement with Monolithic Memories to develop a mask- programmable logic device incorporating the GE innovations. The device was named the 'Programmable
Associative Logic Array' or PALA. The MMI 5760 was completed in 1976 and could implement multilevel or sequential circuits of over 100 gates. The device was supported by a GE design environment where Boolean equations would be converted to mask patterns for configuring the device.
2.3.1 PROGRAMMABLE ARRAY LOGIC (PAL)
MMI introduced a breakthrough device in 1978, the Programmable Array Logic or PAL. The architecture was simpler than that of Signetics FPLA because it omitted the programmable OR array. This made the parts faster, smaller and cheaper. They were available in 20 pin 300 mil DIP packages while the
FPLAs came in 28 pin 600 mil packages. Basically A programmable array logic circuit is a circuit having a programmable AND gate array and having means for connecting individual AND gate outputs to the input of one or the other of a pair of neighbouring OR gates. This allows the product terms to be shared 36 between two outputs.
Figure 9. Programmable Array Logic
2.3.2 Programmable Logic Array (PLA)
A programmable logic array (PLA) is a programmable device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. This layout allows for a large number of logic functions to be synthesized in the sum of products (and sometimes product of sums) canonical forms. One application of a PLA is to implement the control over a datapath. It defines various states in an instruction set, and produces the next state (by conditional branching). [eg. if the machine is in state 2, and will go to state 4 if the instruction contains an immediate field; then the PLA should define the actions of the control in state 2, will set the next state to be 4 if the instruction contains an immediate field, and will define the actions of the control in state 4]. Programmable Logic Arrays should correspond to a state diagram for the system. Other commonly used programmable logic devices are PAL, CPLD and
FPGA. Note that the use of the word "programmable" does not indicate that all PLAs are field- programmable; in fact many are mask-programmed during manufacture in the same manner as a mask
ROM. This is particularly true of PLAs that are embedded in more complex and numerous integrated circuits such as microprocessors. PLAs that can be programmed after manufacture are called FPLA (Field- programmable PLA). 37
Figure 10. Programmable Logic array
2.3.3 GENERIC ARRAY LOGIC (GAL)
An innovation of the PAL was the generic array logic device, or GAL, invented by Lattice
Semiconductor in 1985. This device has the same logical properties as the PAL but can be erased and reprogrammed. The GAL is very useful in the prototyping stage of a design, when any bugs in the logic can be corrected by reprogramming. GALs are programmed and reprogrammed using a PAL programmer, or by using the in-circuit programming technique on supporting chips. Lattice GALs combine CMOS and electrically erasable (E^2) floating gate technology for a high-speed, low-power logic device. A similar device called a PEEL (programmable electrically erasable logic) was introduced by the International
CMOS Technology (ICT) corporation
Figure 11. Lattice GAL 16V8 and 20V8
38
2.3.4 COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD)
PALs and GALs are available only in small sizes, equivalent to a few hundred logic gates. For bigger logic circuits, complex PLDs or CPLDs can be used. These contain the equivalent of several PALs linked by programmable interconnections, all in one integrated circuit. CPLDs can replace thousands, or even hundreds of thousands, of logic gates.
Some CPLDs are programmed using a PAL programmer, but this method becomes inconvenient for devices with hundreds of pins. A second method of programming is to solder the device to its printed circuit board, then feed it with a serial data stream from a personal computer. The CPLD contains a circuit that decodes the data stream and configures the CPLD to perform its specified logic function.
Each manufacturer has a proprietary name for this programming system.
2.4 FIELD PROGRAMMABLE GATE ARRAYS (FPGA)
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application- specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of the portion of the design and the low non-recurring engineering costs relative to an ASIC design (not withstanding the generally higher unit cost), offer advantages for many applications.
FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"—somewhat like a one-chip programmable breadboard. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.
In addition to digital functions, some FPGAs have analog features. The most common analog
39 feature is programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring unacceptably, and to set stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too slow. Another relatively common analog feature is differential comparators on input pins designed to be connected to differential signaling channels. A few "mixed signal FPGAs" have integrated peripheral Analog-to-Digital Converters
(ADCs) and Digital-to-Analog Converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip. Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.
Figure 12. A xilinx FPGA development board
2.4.1 HISTORY OF FPGA
The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field programmable), however programmable logic was hard-wired between logic gates. 40
In the late 1980s the Naval Surface Warfare Department funded an experiment proposed by Steve
Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.
Some of the industry’s foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in
1985.
Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt, invented the first commercially viable field programmable gate array in 1985 – the XC2064. The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market.[10] The
XC2064 boasted a mere 64 configurable logic blocks (CLBs), with two 3-input lookup tables (LUTs).
More than 20 years later, Freeman was entered into the National Inventor's Hall of Fame for his invention.
Xilinx continued unchallenged and quickly growing from 1985 to the mid-1990s, when competitors sprouted up, eroding significant market-share. By 1993, Actel was serving about 18 percent of the market.The 1990s were an explosive period of time for FPGAs, both in sophistication and the volume of production. In the early 1990s, FPGAs were primarily used in telecommunications and networking. By the end of the decade, FPGAs found their way into consumer, automotive, and industrial applications.FPGAs got a glimpse of fame in 1997, when Adrian Thompson, a researcher working at the University of Sussex, merged genetic algorithm technology and FPGAs to create a sound recognition device. Thomson’s algorithm configured an array of 10 x 10 cells in a Xilinx FPGA chip to discriminate between two tones, utilising analogue features of the digital chip. The application of genetic algorithms to the configuration of devices like FPGA's is now referred to as Evolvable hardware.
2.4.2 MODERN DEVELOPMENT
As previously mentioned, many modern FPGAs have the ability to be reprogrammed at "run time," and this is leading to the idea of reconfigurable computing or reconfigurable systems — CPUs that reconfigure themselves to suit the task at hand. Software-configurable microprocessors such as the Stretch
41
S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip.
Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts.
Xilinx claims that several market and technology dynamics are changing the ASIC/FPGA paradigm
• Integrated circuit costs are rising aggressively
• ASIC complexity has lengthened development time
• R&D resources and headcount are decreasing
• Revenue losses for slow time-to-market are increasing
• Financial constraints in a poor economy are driving low-cost technologies
These trends make FPGAs a better alternative than ASICs for a larger number of higher-volume applications than they have been historically used for, to which the company attributes the growing number of FPGA design starts. Some FPGAs have the capability of partial re-configuration that lets one portion of the device be re-programmed while other portions continue running.
Figure 13. An Altera Cyclone II FPGA
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2.4.3 ARCHITECTURE
The most common FPGA architecture consists of an array of logic blocks (called Configurable
Logic Block, CLB, or Logic Array Block, LAB, depending on vendor), I/O pads, and routing channels.
Generally, all the routing channels have the same width (number of wires). Multiple I/O pads may fit into the height of one row or the width of one column in the array.
An application circuit must be mapped into an FPGA with adequate resources. While the number of CLBs/LABs and I/Os required is easily determined from the design, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. For example, a crossbar switch requires much more routing than a systolic array with the same gate count. Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit,
FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of LUTs and IOs can be routed. This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs.
In general, a logic block (CLB or LAB) consists of a few logical cells (called ALM, LE, Slice etc).
A typical cell consists of a 4-input Lookup table (LUT), a Full adder (FA) and a D-type flip-flop, as shown below. The LUT are in this figure split into two 3-input LUTs. In normal mode those are combined into a
4-input LUT through the left mux (multiplexer). In arithmetic mode, their outputs are fed to the FA. The selection of mode are programmed into the middle mux. The output can be either synchronous or asynchronous, depending on the programming of the mux to the right, in the figure example. In practice, entire or parts of the FA are put as functions into the LUTs in order to save space
Figure 14. Simplified illustration of a logic cell 43
ALMs and Slices usually contains 2 or 4 structures similar to the example figure, with some shared signals. CLBs/LABs typically contains a few ALMs/LEs/Slices. In recent years, manufacturers have started moving to 6-input LUTs in their high performance parts, claiming increased performan ce. Since clock signals (and often other high-fanout signals) are normally routed via special -purpose dedicated routing networks in commercial FPGAs, they and other signals are separately managed.
For this example architecture, the locations of the FPGA l ogic block pins are shown below.
Figure 15. Logic Block Pin Locations
2.4.4 FPGA DESIGN AND PROGRAMMING
To define the behavior of the FPGA, the user provides a hardware description language (HDL) or a schematic design. The HDL form is more suited to work with large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. Ho wever, schematic entry can allow for easier visualisation of a design.
Then, using an electronic design automation tool, a technology -mapped netlist is generated. The netlist can then be fitted to the actual FPGA architecture using a process called place -and-route, usually performed by the FPGA company's proprietary place -and-route software. The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated (also using the FPGA company's proprietary software) is used to reconfigure the FPGA. Going from schematic/HDL source files to actual
44 configuration: The source files are fed to a software suite from the FPGA/CPLD vendor that through different steps will produce a file. This file is then transferred to the FPGA/CPLD via a serial interface
(JTAG) or to an external memory device like an EEPROM.
The most common HDLs are VHDL and Verilog, although in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level through the introduction of alternative languages. National
Instrument's LabVIEW graphical programming language ( sometimes referred to as "G" ) has an FPGA add-in module available to target and program FPGA hardware. The LabVIEW approach drastically simplifies the FPGA programming process.
To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called IP cores, and are available from FPGA vendors and third-party IP suppliers (rarely free, and typically released under proprietary licenses). Other predefined circuits are available from developer communities such as OpenCores (typically released under free and open source licenses such as the GPL, BSD or similar license), and other sources.
In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist.
2.5 MULTICORE SYSTEM ON CHIP
System-on-chip (SOC) is an integrated circuit that includes a processor, a bus, and other elements on a single chip substrate. System-on-Chip (SOC) design is a system in which various components, such 45 as volatile memory systems, non-volatile memory systems, data signal processing systems, mixed signal circuits and logic circuits are each formed into units and integrated on a single chip. The primary advantages of SOC devices are lower costs, greatly decreased size, and reduced power consumption of the system. Digital systems using SOC design, such as those used in handheld digital products, has replaced bulkier and higher power consuming digital systems built on a board in a package having several chips.
2.5.1 STRUCTURE
A typical SoC consists of:
• One microcontroller, microprocessor or DSP core(s). Some SoCs – called multiprocessor
System-on-Chip (MPSoC) – include more than one processor core.
• Memory blocks including a selection of ROM, RAM, EEPROM and flash.
• Timing sources including oscillators and phase-locked loops.
• Peripherals including counter-timers, real-time timers and power-on reset generators.
• External interfaces including industry standards such as USB, FireWire, Ethernet, USART, SPI.
• Analog interfaces including ADCs and DACs.
• Voltage regulators and power management circuits.
These blocks are connected by either a proprietary or industry-standard bus such as the AMBA bus from ARM. DMA controllers route data directly between external interfaces and memory, by-passing the processor core and thereby increasing the data throughput of the SoC. These blocks are connected by either a proprietary or industry-standard bus such as the AMBA bus from ARM. DMA controllers route data directly between external interfaces and memory, by-passing the processor core and thereby increasing the data throughput of the SoC.
2.5.2 DESIGN FLOW
An SoC consists of both the hardware described above, and the software that controls the microcontroller, microprocessor or DSP cores, peripherals and interfaces. The design flow for an SoC
46 aims to develop this hardware and software in parallel. Most SoCs are developed from pre-qualified hardware blocks for the hardware elements described above, together with the software drivers that control their operation. Of particular importance are the protocol stacks that drive industry-standard interfaces like USB. The hardware blocks are put together using CAD tools such as the Quartus II EDA design tool; the software modules are integrated using a software development environment like the NIOS
II eclipse IDE. A key step in the design flow is emulation: the hardware is mapped onto an emulation platform based on a field programmable gate array (FPGA) that mimics the behavior of the SoC, and the software modules are loaded into the memory of the emulation platform. Once programmed, the emulation platform enables the hardware and software of the SoC to be tested and debugged at close to its full operational speed. (Emulation is generally preceded by extensive software simulation. In fact, sometimes the FPGAs are used primarily to speed up some parts of the simulation work.)
After emulation the hardware of the SoC follows the place and route phase of the design of an integrated circuit before it is fabricated. Chips are verified for logical correctness before being sent to foundry. This process is called functional verification, and it accounts for a significant portion of the time and energy expended in the chip design life cycle (although the often quoted figure of 70% is probably an exaggeration). Verilog and VHDL are typical hardware description languages used for verification. With the growing complexity of chips, hardware verification languages like SystemVerilog, SystemC, e, and
OpenVera are also being used. Bugs found in the verification stage are reported to the designer.
SoCs can be fabricated by several technologies, including:
• Full custom • Standard cell • FPGA
SoC designs usually consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. And with fewer packages in the system, assembly costs are reduced as well.
However, like most VLSI designs, the total cost is higher for one large chip than for the same functionality distributed over several smaller chips, because of lower yields.
47
Figure 16. A microco ntroller based system on chip
2.6 ELECTRONIC DESIGN AUTOMATION (EDA) TOOLS
There are various electronic design and automation CAD tools for automating the design of the vast growing field of digital electronics. These technologies have made it possible to do design and synthesis on the computer where errors are easily corrected a nd then testing is done before the actual
48 physical implementation of the design. This has greatly resulted in an astronomical growth in the development of the electronic industry.
2.6.1 SYSTEM ON PROGRAMMABLE CHIP (SOPC) BUILDER QUARTUS II
SOPC Builder (System on a Programmable Chip Builder) is software made by Altera that automates connecting soft-hardware components to create a complete computer system that runs on any of its various FPGA chips. SOPC Builder incorporates a library of pre-made components (including the flagship Nios II soft processor, memory controllers, interfaces, and peripherals) and an interface for incorporating custom ones. Interconnections are made though the Avalon bus. Bus arbitration, bus width matching, and even clock domain crossing are all handled automatically when SOPC Builder generates the system. A GUI is the only thing used to configure the soft-hardware components (which often have many options) and to specify the bus topology. The resulting "virtual" system can then be connected to the outside world via the FPGA's programmable pins or connected internally to other soft components. The
FPGA's pins are routed to connectors, such as for PCI or DDR, or -- as is often the case in embedded systems -- to other chips mounted on the same PCB. Resource utilization on an FPGA hosting an SOPC
Builder system is very modest by modern standards.
2.6.2 NIOS II PROCESSOR
NIOS II is a 32 bit embedded processor architecture designed specifically for the Althera FPGA
family The Nios II processor is a general-purpose RISC processor core, providing:
• Full 32-bit instruction set, data path, and address space
• 32 general-purpose registers
• Optional shadow register sets
• 32 interrupt sources
• External interrupt controller interface for more interrupt sources
49
• Single-instruction 32 × 32 multiply and divide producing a 32-bit result
• Dedicated instructions for computing 64-bit and 128-bit products of multiplication
• Floating-point instructions for single-precision floating-point operations
• Single-instruction barrel shifter
• Access to a variety of on-chip peripherals, and interfaces to off-chip memories and
peripherals.
• Hardware-assisted debug module enabling processor start, stop, step, and trace under
control of the Nios II software development tools
• Optional memory management unit (MMU) to support operating systems that require MMUs.
• Optional memory protection unit (MPU)
• Software development environment based on the GNU C/C++ tool chain and the Nios II
Software Build Tools (SBT) for Eclipse
• Integration with Altera's SignalTap® II Embedded Logic Analyzer, enabling real-time
analysis of instructions and data along with other signals in the FPGA design
• Instruction set architecture (ISA) compatible across all Nios II processor systems
• Performance up to 250 DMIPS
A Nios II processor system is equivalent to a microcontroller or “computer on a chip” that includes a processor and a combination of peripherals and memory on a single chip. A Nios II processor system consists of a Nios II processor core, a set of on-chip peripherals, on-chip memory, and interfaces to off-chip memory, all implemented on a single Altera device. Like a microcontroller family, all Nios II processor systems use a consistent instruction set and programming model.
50
2.6.3 HARDWARE DESCRIPTION LANGUAGE (HDL)
In electronics, a hardware description language or HDL is any language from a class of computer languages and/or programming languages for formal description of electronic circuits, and more specifically, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation. HDLs are standard text- based expressions of the spatial and temporal structure and behaviour of electronic systems. Like concurrent programming languages, HDL syntax and semantics includes explicit notations for expressing concurrency. However, in contrast to most software programming languages, HDLs also include an explicit notion of time, which is a primary attribute of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as netlist languages used on electric computer-aided design (CAD). HDLs are used to write executable specifications of some piece of hardware. A simulation program, designed to implement the underlying semantics of the language statements, coupled with simulating the progress of time, provides the hardware designer with the ability to model a piece of hardware before it is created physically. It is this executability that gives HDLs the illusion of being programming languages. Simulators capable of supporting discrete-event (digital) and continuous- time (analog) modeling exist, and HDLs targeted for each are available. It is certainly possible to represent hardware semantics using traditional programming languages such as C++, although to function such programs must be augmented with extensive and unwieldy class libraries. Primarily, however, software programming languages do not include any capability for explicitly expressing time, and this is why they do not function as a hardware description language. Before the recent introduction of SystemVerilog, C++ integration with a logic simulator was one of the few ways to use OOP in hardware verification. SystemVerilog is the first major HDL to offer object orientation and garbage collection. Broadly there are two types of hardware description languages, namely :
• Verolog HDL
51
• VHDL
52
CHAPTER THREE
SYSTEM ANALYSIS AND DESIGN
3.0 PEAK PERIOD DETECTION ALGORITHM
The algorithm for determining the peaks of the signals is the peak period detection algorithm. This algorithm detects the first peak and the looks for other peaks. The algorithm essentially calculates the parameters listed below
▪ heart period ▪ peaks including P,Q,R,S,T and U ▪ Inter – peak spans
Basically peak heights, periods and inter-peak times that fall outside of safe values are paradigms for measuring the state of health of a person's heart and hence detecting abnormalities in the process.
Essentially the algorithm executes in broadly two part. The first is that the algorithm calculates the period using the autocorrelation function while the other part finds the number of peaks, amplitude of the peaks and the time interval of the peaks.
3.1 PERIOD DETECTION
This stage of the peak-period detection algorithm calculates the period essentially. There are four stages involved in the process namely
▪ reading data ▪ derivation ▪ autocorrelation and ▪ Finding interval.
3.1.1 READING DATA
This stage involves reading the data to be processed. These data have undergone appropriate filteration from the finite impulse response filter and stores in some buffer. The data is read and made available from the buffer for the processing unit to process. The algorithm running on the processing unit then processes the data accordingly. 53
Fig 17 . Filtered ECG signal
3.1.2 DERIVATION
The derivation stage performs a derivative of the signal. From calculus this translates to a mathematical calculation of the rate of change of the signal with respect to time. This parameter is more accurate in calculating the period of the signal than the original signal as a result of the high level of randomness and stochastic processes associated with the original signal without derivation. Some fluctuations around the peak will be reduced to near zero values after the derivation is performed on the signal. Let the signal read from memory be given by x(t). The derivative of the function is given by the approximation below,
∂ x x[n + 1 ] − x[n] (t) ≈ ∂ t (n + 1 ) − n − = x[n + 1 ] x[n] (13)
,
x[n] : current sampling data ( filtered orignal ECG/EKG signal )
nt, : current ti me ( step )
54
Fig 18. Derivative of ECG signal
3.1.3 AUTOCORRELATION
The autocorrelation phase of the peak period detection algorithm helps to find the periodicity of the ECG signal using the mathematics of the statistical autocorrelation function. The autocorrelation function is a mathematical tool for finding repeating patterns using statistics.
n= ∞
AF x[ k ]= ∑ x[ n]× x[ n− k ] n= − ∞ (14) where
AF x : the autocorrelation function x[ n]: the ECG/EKG filtered signal k : the number of lags of the autocorrelation
Assuming a finite number of time steps the autocorrelation function is given by
55
n=N
AF x[ k ]= ∑ x[ n]× x[ n− k ] n= 0 (15)
AF x : the autocorrelation function x[ n]: the ECG/EKG filtered signal N : the number of time steps needed for the calculations to get the period
CALCULATIONS OF AUTOCORRELATION FUNCTION FOR SIGNAL SAMPLES
In other to illustrate the idea of autocorrelation function and how it is used to detect periodicity sample calculation processes are shown below for hypothetical twelve sample signal.
I have assumed that the ECG/EKG signals are 12 samples shown below
Table 1. Twelve samples for calculations 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 0 1 2 0 1 2 0 1 2
11
AF x[ L ]= ∑ x[n]× x[ n− L ] n= 0 (16)
When n− L< 0, x is 0
Basically n will run from 0 to 11 for the twelve samples analysed here as shown below.
1st calculation.
11 11
AF x[ 0]= ∑ x[n]× y[ n− 0]= ∑ x[ n]× x[ n] n= 0 n= 0
012012012012 × × × × × × × × ×
012012012012
56
From which
AF [0]= 20 y
By Similar calculation process the others are shown below
2nd calculation.
11
AF x[1]= ∑ x[ n]× x[ n− 1] n= 0 (17)
y[ n] 012012012012
× × × × × × × ×
y[ n] 012012012012
AF [1]= 8 y
3rd calculation. 11
AF x[ 2]= ∑ x[ n]× x[ n− 2] n= 0 (18)
y[ n ] 012012012012
× × × × × × ×
y[ n ] 012012012012
AF [ 2]= 6 x
4th calculation.
11
AF x[ 3]= ∑ x[ n]× x[ n− 3] n= 0 (19)
57
x[ n] 012012012012
× × × × × ×
012012012012 x[ n ]
AF [ 3]= 15 x 5th calculation.
11
AF x[ 4]= ∑ x[ n]× x[n− 4] n= 0 (20)
x[ n] 012012012012
× × × × × ×
012012012012 x[ n]
AF [ 4]= 6 x
6th calculation.
11
AF x[ 5]= ∑ x[ n]× x[ n− 5] n= 0 (21)
012012012012 x[ n]
× × × × × ×
012012012012 x[ n]
AF [ 5]= 4 x
58
Tabulation of results obtained from continuing the calculation process
0 1 2 0 1 2 0 1 2 0 1 2 x[ n ]
L 0 1 2 3 4 5 6 7 8 9 10 11
20 8 6 15 6 4 10 4 2 5 2 0 AF x
Table 2. Result of sample calculations
Figure 19. Matlab plot of AFx against L
From the plot it is observed that every three samples are periodic.
59
Fig 20. Autocorrelation function of the Derivative
3.1.4 Finding intervals
Finding intervals part of the peak period detection algorithm is broadly divided into the following steps and sun algorithms. Flow charts are used to illustrate the various algorithms
• Finding maximum value
• Reduce negative value
• Peak detection from ACF result
• Find base points
• Sort base points
• Calculate interval
• Renew next start index
Finding maximum
The maximum value is set to be equal to the value at input index zero. The maximum
value index is set to zero and then the iterator value set to 1 for initialization. If the iterator 60 value is greater than ACF step the algorithm ends, otherwise it continues to check if the input value at the iterator index is greater than the maximum. If this is true the maximum value is equal to the input value at the iterator index and the maximum value index is set to the iterator value and then the iterator increments and the program goes back to the first checking stage. If the last decision point is not true the iterator just increments and the program goes back to the first decision stage.
Start
maxValue = inputValue[0]
maxValueIndex = 0
i=1
No end
I Yes Yes inputValue[i]>maxValue maxValue = inputValue[i] maxValueIndex = i No i++ 61 Reduce negative At the start of this algorithm, iterator is set to 1. The next is the decision point that checks if the iterator is less than the ACF step. If this is false the algorithm ends. Otherwise the algorithm checks if the input value at the iterator index is less than zero. If this is true the reduce negative value at the iterator index is set to zero and then the iterator is incremented. Otherwise the reduce negative value and the input value are set to equal at the iterator value. After this the iterator is incremented. The flowchart is shown below. Start i=1 No end I Yes No inputValue[i]<0 reducedNegativeValue[i] inputValue[i] Yes reduceNegativeValue[i]=0 i++ 62 Flow charts for the other algorithms are respectively shown Find base point 63 Peak detection from ACF results 64 Sort base point 65 Finding the peaks The processes involved in finding the peaks are analysed. Basically the waveform is made up of different peaks both positive and negative ones known as the P,Q,R,S,T and U peaks. It makes more sense to divide the peaks into positive and negative peaks. In a typical ECG waveform the P, R, T, U are positive peaks as their crests are above the horizontal reference axis while Q and S are negative peaks as they are below the horizontal reference axis Finding R peaks The R peak is the peak with the highest amplitude. In finding the R peaks, the maximum value is found among positive peaks in an interval. This peak is the R peak. The value and point of the R peaks are respectively stored. Figure 21. Finding R peak Finding P Peak The P peak is to the left of the R peak in a given ECG waveform. The P peak is actually formed at an index where the maximum value index, the R peak index is shifted a step back. 66 Essentially the P peak is found from among peaks from the start to the maximum value index. From the reference or start of the waveform, the P peak is the peak seen first before the R peak. This peak is identified as the P peak. The peak value and the point of the peak are stored. Fig 22. Finding P peak Finding T Peak The T peak occurs after the R peaks. It is the peak or maximum value found from among positive peaks from the maximum value index + 1. By shifting the maximum value index, the R peak index in this case, the T peak is found from the maximum of the positive peaks thereafter. Fig 23. Finding T peak 67 Finding U Peak The T peak typically is the maximum of the positive peaks that occur after the T peak. The U peak is found by finding the maximum value from among the positive peaks after the T wave index which is the T wave value index + 1. The value and the point of the U peak are respectively stored. Fig 24. Finding U peak 68 Finding Q peaks The Q peak is a negative peak. It is closest minimum negative peak to the R peak from the start point of the ECG waveform. Fig 25.Finding Q peak Finding S peaks The S peak is the minimum of the negative peak after the R peak value index. It is the negative peak from the R peak closest to it till end of waveform Fig 26. Finding S peak 69 3.2 DIGITAL FINITE IMPULSE RESPONSE FILTER DESIGN `The relationship between the output and input of a digital signal is defined by the difference equation below N − 1 y[ n]= ∑ ai xn− i i= 0 (22) where y[ n]: current filter output ai : filter's coefficients x n : current or previous filter inputs N : Number of filter taps For the ECG design the digital filter is a 5-11 kHz bandpass filter. In this work a finite impulse response bandpass filter is used. The delayed inputs are multiplied with their respective filter coefficients and added together to produce the output. FIR filter IP core is used in this work. 3.3 SYSTEM ARCHITECTURE DESIGN. Basically the entire system at a very abstracted level is shown by the diagram below with the process starting from the signals from the patient's body Figure 27. Multicore system on chip electrocardiography 70 The system architecture adopted is broadly divided into three parts. These are: • Reading data section • Filtering and data analysis section • Display section 3.3.1 READING DATA SECTION The data reading section comprises the analog to digital converter module,on chip memory and the central processing unit as shown by the broken blue lines in the diagram below. The analog to digital conversion ADC unit converts the analog heart signals to digital form for processing. Converted signals are stored in the on chip memory for the central processing unit to process. SDRAM VGA ADC SDRAM VGA Controller Controller Shared Bus On-chip CPU FIR Filter Memory Figure 28. data reading section 71 3.3.2 FILTERING AND DATA ANALYSIS SECTION The filtering and data analysis section essentially consist of the finite impulse response bandpass filter, the on chip memory, the SDRAM and the central processing unit. The FIR filter performs digital filteration on the signal to remove unwanted signals such as environmental noise and baseline wanders. The filtered data are stored in memory for the processing unit to process. The broken red lines shows the modules that make up the filtering and analysis modules SDRAM VGA ADC SDRAM VGA Controller Controller Shared Bus On-chip CPU FIR Filter Memory Figure 29. Filtering and analysis modules 72 3.3.3 DISPLAY SECTION. The display section consist of on chip memory, central processing unit, SDRAM and VGA modules and controllers. The VGA is for the display of the processed output. SDRAM VGA ADC SDRAM VGA Controller Controller Shared Bus On-chip CPU FIR Filter Memory Figure 30. Display section 73 3.3.4 COMPLETE SYSTEM ARCHITECTURE (ADC NOT SHOWN). below is the architectural diagram of the processing and display. The peak period detection algorithm module and the master module are shown Figure 31. Complete system diagram with ADC not shown 74 CHAPTER FOUR IMPLEMENTATION AND RESULTS 4.0 SOPC BUILDER SYSTEM GENERATION AND QUARTUS II COMPILATION The system hardware is designed with the quartus II integrated system on programmable chip SOPC builder. The system consists of NIOS II soft processor both master and peak period detection central processing units,FIR filter IP core ,GLCD and LED controllers,on chip and virtual external memories,JTAG UART,timers,other peripherals with the interconnecting fabrics. The SOPC builder interface is shown in the figure below. Figure 32. SOPC builder interface 75 4.1 QUARTUS II COMPILATION OF THE ENTIRE DESIGN. The quartus II EDA tool is used to compile the entire system. The result of the compilation is the generation of the .sof which is the file to be downloaded into the target FPGA. The quartus II compilation was successfully done as shown in the figure below. Fig 33. Quartus II compilation 76 4.2 NIOS II IDE IMPLEMENTATION OF PPD ALGORITHM The NIOS II IDE running on eclipse platform is used to run the peak period detection algorithm progam on the NIOS II soft processors generated in the systems design. The project is created by upoading the .sopcinfo (SOPC information) file and then running the C code on the processor. The NIOS II IDE is shown below. Fig 34. NIOS II project creation 77 Fig 35. NIOS II building 78 4.3 RESULTS 4.3.1 Flow summary The flow summary is shown in the table below : Logic Utilization 43.00% Combinational ALUTs 9669/38000 (25%) Memory ALUTs 16/19000 (<1%) Dedicated Logic Registers 11583/38000 (30%) Total Registers 11583 Total Pins 26/296 (9%) Total Virtual Pins 0 Total block memory bits 1,231,888/1,880,064 (66%) Device EP3SL50F484C2 Table 3. Flow Summary report The desktop is also shown below: Fig 36. Flow summary report 79 4.3.2 SOME REPORT ON ANALYSIS AND SYNTHESIS RESOURCE USAGE SUMMARY Estimated ALUTs Used 9658 Dedicated logic registers 11556 Total combinational functions 9658 Total fan-out 100304 Table 4. Analysis and synthesis resources usage summary report Full report is shown below : Fig 37. Analysis and synthesis report 80 4.3.3 SOME POWER ANALYSIS SUMMARY Family Stratix Device EP3SL50F484C2 Power Models Final Total thermal power dissipation 463.86mW Core dynamic power dissipation 0mW Core static power dissipation 435.89mW I/O Thermal power dissipation 27.96mW Power estimation confidence Low Table 5. Power analysis summary report Fig 38. Power analysis report 81 4.3.4 REGISTER TRANSFER LOGIC RTL OF DESIGN. Fig 39. RTL of design Fig 40. Prototype system 82 Part of the Technical Map view Figure 41. Part of the Technical Map view 83 CHAPTER FIVE CONCLUSION AND FUTURE WORK 5.0 CONCLUSION This thesis has bordered on implementing electrocardiography on multicore system on chip. We were able to design our hardware using the system on programmable chip (SOPC) builder integrated into quartus II and then also programmed our NIOS II processor for the ECG signal processing using the novel peak period detection algorithm. The algorithm first detects the period and then looks for all peaks. Our system opens up novel ways to do heart medicine in a more efficient way as the entire system is less bulky and more accurate than the traditional ECG. The technology was implemented on an FPGA (Target device is Altera Stratix III EP3SL50F484C2) based on Multicore System on Chip. The Logic Utilization for one- lead system which is scalable to multi lead after compilation was 43%, combinational ALUTs 9669/38000 (25%), Memory ALUTs 16/19000 (<1%), Total registers 11583/38000 (30%) and total thermal power dissipation of 463.86mW and an efficiency of 70%. 5.1 RECOMMENDATION Future work will look into networking issues as regards transmitting the processed ECG signals to a doctor in some remote location using various wireless internet technologies. Patients are put on given networks and signal integrity maintained to get the right signal to the right doctor for the right diagnoses and the right prescription. We intend to fine tune this technology to positively affect heart medicine in general and especially among elderly people in developing countries with Africa being a prime focus. We see a future not too far from now when this technology will become implemented in an African terrain and the world at large. Everybody’s heart signals using our solution will be connected on the network with real time record of their heart status to a doctor. We are pushing the boundaries of engineering beyond the 84 limit. 85 REFERENCES . [1] Mohamed Najim : Digital Filters Design for Signal and Image Processing. [2] Jinyuan Wu, “How to Design Compact FPGA Functions—Resource awareness design practices (2006) [3] Steven Brown and Zvonko Vranesic : Fundamentals of digital logic with VHDL design. pp 92- 114. [4] Steven W. Smith : The Scientist and Engineer's Guide to Digital Signal Processing 2nd Edition [5] Iyad Al Khatib Phd Thesis Department of Electronic, Computer, and Software Systems (ECS) School of Information and Communication Technology (ICT) Royal Institute of Technology (KTH) Stockholm, Sweden June 2008: Performance Analysis of Application- Specific Multicore Systems on Chip. [6] Mostafa Abd-El-Barr and Hesham El-Rewini Fundamentals of computer organization and Architecture. [7] Analog to digital conversion : http://en.wikipedia.org/wiki/Analog-to-digital_converter . [8] Digital filters : http://en.wikipedia.org/wiki/Digital_filter [9] Introduction to digital signal processing. http://www.dsptutor.freeuk.com/intro.htm [10] Altera Corporation, Quartus II,SOPC builder,NIOS II : www.altera.com [11] A. Alexandridi and G. Manis, Hardware Design for the Computation of Heart rate Variability, Journal of Medical Engineering & Technology, Vol. 26, No. 2, pp. 49- 62, March-April 2002. [12] Fuster, V. Epidemic of Cardiovascular Disease and Stroke: The Three Main Challenges, Circulation, Vol. 99, Issue 9, March 1999, 1132-1137. [13] Yasuyoshi Haga, Abderazek Ben Abdallah, Kenichi Kuroda : Embedded MCSoC Architecture and Period-Peak Detection (PPD) Algorithm for ECG/EKG Processing (2009). 86 [14] Code Blue Medical wireless sensor Networks: http://www.eecs.harvard.edu/~mdw/proj/codeblue [15] Iyad Al Khatib, et al: A Multiprocessor System-on-Chip for Real-Time Biomedical Monitoring and Analysis, Architectural Design Space Exploration. [16] Kristian M. Hafkemeyer et al: System-on-Chip Approach for Biomedical Signal Acquisition [17] R. Dorn , M. V ʗ lker , H. Neubauer1 , J. Hauer , J. Johansson: A channel ECG measuring system for wireless applications, International Workshop on Medical Measurement and Applications Benevento, Italy, 20-21 April, 2006. [18] Z. Piotrowskia and K. Ró żanowskib : Robust Algorithm for Heart Rate (HR) Detection and Heart Rate Variability (HRV) Estimation (2010) [19]Programmable Logic devices http://en.wikipedia.org/wiki/Programmable_logic_device 87