Program & Exhibits Guide

Total Page:16

File Type:pdf, Size:1020Kb

Program & Exhibits Guide FROM CHIPS TO SYSTEMS – LEARN TODAY, CREATE TOMORROW CONFERENCE PROGRAM & EXHIBITS GUIDE JUNE 24-28, 2018 | SAN FRANCISCO, CA | MOSCONE CENTER WEST Mark You Calendar! DAC IS IN LAS VEGAS IN 2019! MACHINE IP LEARNING ESS & AUTO DESIGN SECURITY EDA IoT FROM CHIPS TO SYSTEMS – LEARN TODAY, CREATE TOMORROW JUNE 2-6, 2019 LAS VEGAS CONVENTION CENTER LAS VEGAS, NV DAC.COM DAC.COM #55DAC GET THE DAC APP! Fusion Technology Transforms DOWNLOAD FOR FREE! the RTL-to-GDSII Flow GET THE LATEST INFORMATION • Fusion of Best-in-Class Optimization and Industry-golden Signoff Tools RIGHT WHEN YOU NEED IT. • Unique Fusion Data Model for Both Logical and Physical Representation DAC.COM • Best Full-flow Quality-of-Results and Fastest Time-to-Results MONDAY SPECIAL EVENT: RTL-to-GDSII Fusion Technology • Search the Lunch at the Marriott Technical Program • Find Exhibitors www.synopsys.com/fusion • Create Your Personalized Schedule Visit DAC.com for more details and to download the FREE app! GENERAL CHAIR’S WELCOME Dear Colleagues, be able to visit over 175 exhibitors and our popular DAC Welcome to the 55th Design Automation Pavilion. #55DAC’s exhibition halls bring attendees several Conference! new areas/activities: It is great to have you join us in San • Design Infrastructure Alley is for professionals Francisco, one of the most beautiful who manage the HW and SW products and services cities in the world and now an information required by design teams. It houses a dedicated technology capital (it’s also the city that Design-on-Cloud Pavilion featuring presentations my son is named after). A lot is waiting from the Design Infrastructure Alley exhibitors and for you on the three floors of the splendid Moscone West invited companies. Conference Center. • Smart Systems Square is a centralized exhibit pavilion After 54 years, DAC continues to be the premier conference where engineers can interact with developers, network for design and design automation for IC chips all the and platform providers, and verification experts for AI way to systems, and this year it’s filled with new energy. and machine learning applications. It also showcases With the help of countless volunteers, the DAC executive live demos of the winning entries from the System committee has assembled a top-tier research program, Design Contest. highly-regarded practitioners’ forums, and widely- Like to have some hands-on fun with building a mini represented exhibition. I briefly highlight some programs robot? Take the Sunday Sumo Robot Class to learn below. Many more are for you to explore. all that is needed to get your robot ready for the Sumo AI/machine learning is the new featured topic area at Robot Competition at 6:00 p.m. during the Tuesday night #55DAC. You will hear keynotes, invited talks, tutorials reception. Do not have time to manage your own? Come and research paper presentations (close to 20 sessions and see Sumo robot teams performing pre-competition altogether) on innovative hardware, software and system practices in the Smart Systems Square in preparation for designs of neural network accelerators as well as the their competition. application of AI/machine learning techniques to advancing The DAC Silicon/Technology Art Show is back in full force. EDA. You will also hear from the winners of DAC’s first One cannot find a better place than San Francisco to have System Design Contest, in which more than 100 teams this! The Art Show will highlight the beauty of electronic competed in developing low-energy and high-performance design and algorithms and showcase the works of implementations of neural network-based object detection companies and individuals that contribute to our industry. for drones and will get to see demos of the winning entries I encourage you to attend the Art Show/evening reception on the exhibit floor in theSmart Systems Square. on Monday starting at 6:00 p.m. Besides 50 sessions related to core EDA and IP topic Do you worry about missing any events that you want to areas, #55DAC features: attend? Download DAC’s mobile app! It not only makes • 23 sessions in Design (from heterogeneous SoCs, it easier for you to manage your schedule and activities architectures, circuits, to emerging technologies) at the show but also navigate the three floors of Moscone West. • 12 (six system, six auto) sessions in Embedded Software and Systems and Auto (from IoT, CPS, I hope I will get to talk to many of you in person during embedded memory, to autonomous driving) the week of #55DAC. Together, we LEARN TODAY and CREATE TOMORROW. • 16 sessions in Security/Privacy (from secure processor design, IC reverse engineering, hands-on IoT hacking, to blockchain for security), including presentations by Enjoy the #55DAC! winners of the Hack@DAC contest and hands-on IoT X. Sharon Hu hacking demos in DAC Pavlion; • 5 sessions in IoT (from embedded machine learning, IoT security, runtime support, to industrial IoT architectures) As always, you will find much action and excitement on the exhibition floor. To be more precise, the “exhibition floor” this year actually occupies two floors physically. With our twice daily coffee breaks on the exhibition floor, you will 1 TABLE OF CONTENTS General Chair’s Welcome ................................. 1 Tuesday Sky Talk ............................................ 39 Conference Sponsors ....................................... 3 Tuesday Designer/IP Track Poster Session .... 49 Important Information ....................................... 4 Tuesday Work-in-Progess Poster Session ..... 51 Networking Receptions .................................... 5 Wednesday Visionary Talk .............................. 54 Keynotes .......................................................... 6 Wednesday Keynote ...................................... 54 Visionary & SKY Talks ....................................... 8 Wednesday Sessions ..................................... 55 In Memory ........................................................ 9 Wednesday Designer/IP Track Poster Session ... 69 2018 Awards ................................................... 10 Wednesday Work-in-Progess Poster Session ...71 DAC Pavilion – Booth 2161 ............................ 11 Thursday Keynote .......................................... 75 Workshops ..................................................... 16 Thursday Sessions ......................................... 76 Monday Opening Session .............................. 20 Thursday is Training Day ................................ 85 Monday Keynote ............................................ 20 Colocated Conferences .................................. 87 Monday Sessions ........................................... 21 Additional Meetings ........................................ 89 Monday Sky Talk ............................................ 22 Committees & Organizers .............................. 97 Monday Designer/IP Track Poster Session .... 26 Platinum, Gold & Silver Sponsors ................ 100 Monday Tutorials ............................................ 28 Exclusive Sponsorships ............................... 101 Tuesday Opening Session .............................. 33 Exhibitor List ................................................. 102 Tuesday Keynote ............................................ 33 Design Infrastructure Alley – Booth 1258 ..... 103 Tuesday Sessions ........................................... 34 2 CONFERENCE SPONSORS ACM/SIGDA IEEE/COUNCIL ON ELECTRONIC DESIGN AUTOMATION ELECTRONIC SYSTEM DESIGN ALLIANCE 3 CONFERENCE INFORMATION EXHIBIT HOURS “BIRDS-OF-A-FEATHER” MEETINGS LOCATION: EXHIBIT HALLS LEVEL 1 & 2 DAC will provide conference rooms for informal groups to discuss items of common technical interest. These very Monday, June 25 10:00am - 6:00pm informal, non-commercial meetings, held after hours, are Tuesday, June 26 10:00am - 6:00pm referred to as “Birds-of-a-Feather” (BOF). Wednesday, June 27 10:00am - 6:00pm All BOF meetings are held at the Moscone Center West, Tuesday June 26 from 7:00 - 8:30pm. To arrange a BOF Meeting, please email Trevor Kearns at REGISTRATION HOURS [email protected] LOCATION: MOSCONE CENTER WEST – LEVEL ONE LOBBY Friday, June 22 12:00pm – 6:00pm FIRST AID ROOM Saturday, June 23 - Sunday, June 24 8:00am – 6:00pm First Aid Room is located on Level 1 of Moscone Monday, June 25 - Wednesday, June 27 7:00am – 7:00pm Center West. Thursday, June 28 7:00am – 5:00pm First Aid Room Hours: Friday, June 22 & Saturday, June 23: 8:00am - 5:00pm. Thank You to Our Sponsor Sunday, June 24: 8:00am - 10:30pm, Monday, June 25 & Tuesday, June 26: 8:00am - 7:00pm, Wednesday, June 27: 8:00am - 10:00pm, Thursday, June 28: 8:00am - 5:00pm. In-house security: x511 on a white house phone or on a cell phone, dial (415) 974-4021 ONLINE PROCEEDINGS DAC Proceedings and tutorials will be delivered electronically online via a username and password. DAC MOBLE APP To access: http://proceedings.dac.com Username = Email address Download the DAC App! Password = Registration ID (on your badge) Review the conference program, find Please refer to your registration receipt to be exhibitors, and create a personalized reminded of what package and associated files you schedule all from your phone or mobile are eligible to view. device. The DAC App is FREE for registered attendees! Check your email for your STAY CONNECTED personalized invite or visit DAC.com for more information WIRELESS INTERNET Moscone Center West has complimentary wireless internet service throughout the facility. 4 DAC NETWORKING OPPORTUNITIES WELCOME
Recommended publications
  • A 1024-Core 70GFLOPS/W Floating Point Manycore Microprocessor
    A 1024-core 70GFLOPS/W Floating Point Manycore Microprocessor Andreas Olofsson, Roman Trogan, Oleg Raikhman Adapteva, Lexington, MA The Past, Present, & Future of Computing SIMD MIMD PE PE PE PE MINI MINI MINI CPU CPU CPU PE PE PE PE MINI MINI MINI CPU CPU CPU PE PE PE PE MINI MINI MINI CPU CPU CPU MINI MINI MINI BIG BIG CPU CPU CPU CPU CPU BIG BIG BIG BIG CPU CPU CPU CPU PAST PRESENT FUTURE 2 Adapteva’s Manycore Architecture C/C++ Programmable Incredibly Scalable 70 GFLOPS/W 3 Routing Architecture 4 E64G400 Specifications (Jan-2012) • 64-Core Microprocessor • 100 GFLOPS performance • 800 MHz Operation • 8GB/sec IO bandwidth • 1.6 TB/sec on chip memory BW • 0.8 TB/sec network on chip BW • 64 Billion Messages/sec IO Pads Core • 2 Watt total chip power • 2MB on chip memory Link Logic • 10 mm2 total silicon area • 324 ball 15x15mm plastic BGA 5 Lab Measurements 80 Energy Efficiency 70 60 50 GFLOPS/W 40 30 20 10 0 0 200 400 600 800 1000 1200 MHz ENERGY EFFICIENCY ENERGY EFFICIENCY (28nm) 6 Epiphany Performance Scaling 16,384 G 4,096 F 1,024 L 256 O 64 4096 P 1024 S 16 256 64 4 16 1 # Cores On‐demand scaling from 0.25W to 64 Watt 7 Hold on...the title said 1024 cores! • We can build it any time! • Waiting for customer • LEGO approach to design • No global timinga paths • Guaranteed by design • Generate any array in 1 day • ~130 mm2 silicon area 1024 Cores 1Core 8 What about 64-bit Floating Point? Single Precision Double Precision 2 FLOPS/CYCLE 2 FLOPS/CYCLE 64KB SRAM 64KB SRAM 0.215mm^2 0.237mm^2 700MHz 600MHz 9 Epiphany Latency Specifications
    [Show full text]
  • Comparison of 116 Open Spec, Hacker Friendly Single Board Computers -- June 2018
    Comparison of 116 Open Spec, Hacker Friendly Single Board Computers -- June 2018 Click on the product names to get more product information. In most cases these links go to LinuxGizmos.com articles with detailed product descriptions plus market analysis. HDMI or DP- USB Product Price ($) Vendor Processor Cores 3D GPU MCU RAM Storage LAN Wireless out ports Expansion OSes 86Duino Zero / Zero Plus 39, 54 DMP Vortex86EX 1x x86 @ 300MHz no no2 128MB no3 Fast no4 no5 1 headers Linux Opt. 4GB eMMC; A20-OLinuXino-Lime2 53 or 65 Olimex Allwinner A20 2x A7 @ 1GHz Mali-400 no 1GB Fast no yes 3 other Linux, Android SATA A20-OLinuXino-Micro 65 or 77 Olimex Allwinner A20 2x A7 @ 1GHz Mali-400 no 1GB opt. 4GB NAND Fast no yes 3 other Linux, Android Debian Linux A33-OLinuXino 42 or 52 Olimex Allwinner A33 4x A7 @ 1.2GHz Mali-400 no 1GB opt. 4GB NAND no no no 1 dual 40-pin 3.4.39, Android 4.4 4GB (opt. 16GB A64-OLinuXino 47 to 88 Olimex Allwinner A64 4x A53 @ 1.2GHz Mali-400 MP2 no 1GB GbE WiFi, BT yes 1 40-pin custom Linux eMMC) Banana Pi BPI-M2 Berry 36 SinoVoip Allwinner V40 4x A7 Mali-400 MP2 no 1GB SATA GbE WiFi, BT yes 4 Pi 40 Linux, Android 8GB eMMC (opt. up Banana Pi BPI-M2 Magic 21 SinoVoip Allwinner A33 4x A7 Mali-400 MP2 no 512MB no Wifi, BT no 2 Pi 40 Linux, Android to 64GB) 8GB to 64GB eMMC; Banana Pi BPI-M2 Ultra 56 SinoVoip Allwinner R40 4x A7 Mali-400 MP2 no 2GB GbE WiFi, BT yes 4 Pi 40 Linux, Android SATA Banana Pi BPI-M2 Zero 21 SinoVoip Allwinner H2+ 4x A7 @ 1.2GHz Mali-400 MP2 no 512MB no no WiFi, BT yes 1 Pi 40 Linux, Android Banana
    [Show full text]
  • Oral History of Walden C. (Wally) Rhines
    Oral History of Walden (Wally) C. Rhines Interviewed by: Douglas Fairbairn Recorded: August 10, 2012 Mountain View, California CHM Reference number: X6589.2013 © 2012 Computer History Museum Oral History of Walden C. Rhines Fairbairn: Alright we’re here at the Computer History Museum, it’s August 10th, 2012. My name is Doug Fairbairn, and we’re here to interview Wally Rhines, who is the CEO and Chairman of Mentor Graphics, Corporation. Wally has a rich background in both semiconductors and electronic design automation and we want to try to cover both elements of that career in this oral history. So welcome, Wally, glad to have you with us. Rhines: Glad to be here, Doug. Fairbairn: So Wally, we want to start at the beginning, we want to talk about where you grew up, what it was like growing up, a little bit about your family life and especially how that might have influenced your career in technology. So just start off, where were you born? How did it all start? Rhines: I was born in Pittsburgh, Pennsylvania in 1946. My father was a professor at what was then Carnegie Tech and he was an engineer by training, a chemical engineer and later a metallurgical engineer and his father was an architect and so had a long history of engineering architecture and things like that, and when I was 10 or 11 years old, we moved to Gainesville, Florida where my father started the Material Science and Engineering Department at the University of Florida, which today is the largest in the US and so my recollections of childhood are heavily weighted toward Florida; going to junior high school and high school there, and most of my exposure to technology was associated with all the things you do at that age, science fairs and projects tied into the University of Florida so there was a lot of engineering influence all along.
    [Show full text]
  • Download a PDF Version of the 2017 Annual Review
    Front Back Cover for Avisan.qxp_Layout 1 11/15/17 1:27 PM Page 1 Secure Technology Alliance 191 Clarksville Road Princeton Junction, New Jersey 08550 Annual Review 2017 Alliance A Secure Publication Technology 7 Volume www.securetechalliance.org Annual Review 2017 SCA-ad 2017 resized.indd 1 10/30/2017 10:40:22 AM EXECUTIVE DIRECTOR’S LETTER: A MESSAGE FROM RANDY VANDERHOOF Delivering Value to a Diverse Market Thank you for taking the time to read the 2017 Annual Review. This publication captures the best aspects of the membership experience for 2017 that hundreds of individual members and their organizations helped to provide. This year was especially sig- nificant, as the organization expanded its mission beyond smart cards and was re-branded as the Secure Technology Alliance. The new name and scope allows the Alliance to include embedded chip technology, hardware and software, and the future of digital security in all forms. The vast number of deliverables and member-driven activities recorded in the publication illustrates the diversity of the markets we serve and the commitment of all the industry professionals who contribute their knowledge and leadership toward expanding the market for smart card and related secure chip technologies. CHANGE COMES WITH NEW OPPORTUNITIES The decision to expand the mission and rebrand the organization was driven THE DECISION TO EXPAND by the changes in the secure chip industry, mostly from mobile technol- ogy and the growth of Internet-connected devices. This does not mean the THE MISSION AND REBRAND market for smart cards has disappeared. In fact, over the last few years, the THE ORGANIZATION WAS U.S.
    [Show full text]
  • Software-Defined Hardware Provides the Key to High-Performance Data
    Software-Defined Hardware Provides the Key to High-Performance Data Acceleration (WP019) Software-Defined Hardware Provides the Key to High- Performance Data Acceleration (WP019) November 13, 2019 White Paper Executive Summary Across a wide range of industries, data acceleration is the key to building efficient, smart systems. Traditional general-purpose processors are falling short in their ability to support the performance and latency constraints that users have. A number of accelerator technologies have appeared to fill the gap that are based on custom silicon, graphics processors or dynamically reconfigurable hardware, but the key to their success is their ability to integrate into an environment where high throughput, low latency and ease of development are paramount requirements. A board-level platform developed jointly by Achronix and BittWare has been optimized for these applications, providing developers with a rapid path to deployment for high-throughput data acceleration. A Growing Demand for Distributed Acceleration There is a massive thirst for performance to power a diverse range of applications in both cloud and edge computing. To satisfy this demand, operators of data centers, network hubs and edge-computing sites are turning to the technology of customized accelerators. Accelerators are a practical response to the challenges faced by users with a need for high-performance computing platforms who can no longer count on traditional general-purpose CPUs, such as those in the Intel Xeon family, to support the growth in demand for data throughput. The core of the problem with the general- purpose CPU is that Moore's Law continues to double the number of available transistors per square millimeter approximately every two years but no longer allows for growth in clock speeds.
    [Show full text]
  • Safe and Secure Model-Driven Design for Embedded Systems Letitia Li
    Safe and secure model-driven design for embedded systems Letitia Li To cite this version: Letitia Li. Safe and secure model-driven design for embedded systems. Embedded Systems. Université Paris-Saclay, 2018. English. NNT : 2018SACLT002. tel-01894734 HAL Id: tel-01894734 https://pastel.archives-ouvertes.fr/tel-01894734 Submitted on 12 Oct 2018 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Approche Orientee´ Modeles` pour la Suretˆ e´ et la Securit´ e´ des Systemes` Embarques´ These` de doctorat de l’Universite´ Paris-Saclay prepar´ ee´ a` Telecom ParisTech Ecole doctorale n◦580 Denomination´ (STIC) NNT : 2018SACLT002 Specialit´ e´ de doctorat: Informatique These` present´ ee´ et soutenue a` Biot, le 3 septembre` 2018, par LETITIA W. LI Composition du Jury : Prof. Philippe Collet Professeur, Universite´ Coteˆ d’Azur President´ Prof. Guy Gogniat Professeur, Universite´ de Bretagne Sud Rapporteur Prof. Maritta Heisel Professeur, University Duisburg-Essen Rapporteur Prof. Jean-Luc Danger Professeur, Telecom ParisTech Examinateur Dr. Patricia Guitton
    [Show full text]
  • Survey and Benchmarking of Machine Learning Accelerators
    1 Survey and Benchmarking of Machine Learning Accelerators Albert Reuther, Peter Michaleas, Michael Jones, Vijay Gadepally, Siddharth Samsi, and Jeremy Kepner MIT Lincoln Laboratory Supercomputing Center Lexington, MA, USA freuther,pmichaleas,michael.jones,vijayg,sid,[email protected] Abstract—Advances in multicore processors and accelerators components play a major role in the success or failure of an have opened the flood gates to greater exploration and application AI system. of machine learning techniques to a variety of applications. These advances, along with breakdowns of several trends including Moore’s Law, have prompted an explosion of processors and accelerators that promise even greater computational and ma- chine learning capabilities. These processors and accelerators are coming in many forms, from CPUs and GPUs to ASICs, FPGAs, and dataflow accelerators. This paper surveys the current state of these processors and accelerators that have been publicly announced with performance and power consumption numbers. The performance and power values are plotted on a scatter graph and a number of dimensions and observations from the trends on this plot are discussed and analyzed. For instance, there are interesting trends in the plot regarding power consumption, numerical precision, and inference versus training. We then select and benchmark two commercially- available low size, weight, and power (SWaP) accelerators as these processors are the most interesting for embedded and Fig. 1. Canonical AI architecture consists of sensors, data conditioning, mobile machine learning inference applications that are most algorithms, modern computing, robust AI, human-machine teaming, and users (missions). Each step is critical in developing end-to-end AI applications and applicable to the DoD and other SWaP constrained users.
    [Show full text]
  • SPORK: a Summarization Pipeline for Online Repositories of Knowledge
    SPORK: A SUMMARIZATION PIPELINE FOR ONLINE REPOSITORIES OF KNOWLEDGE A Thesis presented to the Faculty of California Polytechnic State University San Luis Obispo In Partial Fulfillment of the Requirements for the Degree Master of Science in Computer Science by Steffen Lyngbaek June 2013 c 2013 Steffen Lyngbaek ALL RIGHTS RESERVED ii COMMITTEE MEMBERSHIP TITLE: SPORK: A Summarization Pipeline for Online Repositories of Knowledge AUTHOR: Steffen Lyngbaek DATE SUBMITTED: June 2013 COMMITTEE CHAIR: Professor Alexander Dekhtyar, Ph.D., De- parment of Computer Science COMMITTEE MEMBER: Professor Franz Kurfess, Ph.D., Depar- ment of Computer Science COMMITTEE MEMBER: Professor Foaad Khosmood, Ph.D., Depar- ment of Computer Science iii Abstract SPORK: A Summarization Pipeline for Online Repositories of Knowledge Steffen Lyngbaek The web 2.0 era has ushered an unprecedented amount of interactivity on the Internet resulting in a flood of user-generated content. This content is of- ten unstructured and comes in the form of blog posts and comment discussions. Users can no longer keep up with the amount of content available, which causes developers to start relying on natural language techniques to help mitigate the problem. Although many natural language processing techniques have been em- ployed for years, automatic text summarization, in particular, has recently gained traction. This research proposes a graph-based, extractive text summarization system called SPORK (Summarization Pipeline for Online Repositories of Knowl- edge). The goal of SPORK is to be able to identify important key topics presented in multi-document texts, such as online comment threads. While most other automatic summarization systems simply focus on finding the top sentences rep- resented in the text, SPORK separates the text into clusters, and identifies dif- ferent topics and opinions presented in the text.
    [Show full text]
  • Zerohack Zer0pwn Youranonnews Yevgeniy Anikin Yes Men
    Zerohack Zer0Pwn YourAnonNews Yevgeniy Anikin Yes Men YamaTough Xtreme x-Leader xenu xen0nymous www.oem.com.mx www.nytimes.com/pages/world/asia/index.html www.informador.com.mx www.futuregov.asia www.cronica.com.mx www.asiapacificsecuritymagazine.com Worm Wolfy Withdrawal* WillyFoReal Wikileaks IRC 88.80.16.13/9999 IRC Channel WikiLeaks WiiSpellWhy whitekidney Wells Fargo weed WallRoad w0rmware Vulnerability Vladislav Khorokhorin Visa Inc. Virus Virgin Islands "Viewpointe Archive Services, LLC" Versability Verizon Venezuela Vegas Vatican City USB US Trust US Bankcorp Uruguay Uran0n unusedcrayon United Kingdom UnicormCr3w unfittoprint unelected.org UndisclosedAnon Ukraine UGNazi ua_musti_1905 U.S. Bankcorp TYLER Turkey trosec113 Trojan Horse Trojan Trivette TriCk Tribalzer0 Transnistria transaction Traitor traffic court Tradecraft Trade Secrets "Total System Services, Inc." Topiary Top Secret Tom Stracener TibitXimer Thumb Drive Thomson Reuters TheWikiBoat thepeoplescause the_infecti0n The Unknowns The UnderTaker The Syrian electronic army The Jokerhack Thailand ThaCosmo th3j35t3r testeux1 TEST Telecomix TehWongZ Teddy Bigglesworth TeaMp0isoN TeamHav0k Team Ghost Shell Team Digi7al tdl4 taxes TARP tango down Tampa Tammy Shapiro Taiwan Tabu T0x1c t0wN T.A.R.P. Syrian Electronic Army syndiv Symantec Corporation Switzerland Swingers Club SWIFT Sweden Swan SwaggSec Swagg Security "SunGard Data Systems, Inc." Stuxnet Stringer Streamroller Stole* Sterlok SteelAnne st0rm SQLi Spyware Spying Spydevilz Spy Camera Sposed Spook Spoofing Splendide
    [Show full text]
  • Opencapi, Gen-Z, CCIX: Technology Overview, Trends, and Alignments
    OpenCAPI, Gen-Z, CCIX: Technology Overview, Trends, and Alignments BRAD BENTON| AUGUST 8, 2017 Agenda 2 | OpenSHMEM Workshop | August 8, 2017 AGENDA Overview and motivation for new system interconnects Technical overview of the new, proposed technologies Emerging trends Paths to convergence? 3 | OpenSHMEM Workshop | August 8, 2017 Overview and Motivation 4 | OpenSHMEM Workshop | August 8, 2017 NEWLY EMERGING BUS/INTERCONNECT STANDARDS Three new bus/interconnect standards announced in 2016 CCIX: Cache Coherent Interconnect for Accelerators ‒ Formed May, 2016 ‒ Founding members include: AMD, ARM, Huawei, IBM, Mellanox, Xilinx ‒ ccixconsortium.com Gen-Z ‒ Formed August, 2016 ‒ Founding members include: AMD, ARM, Cray, Dell EMC, HPE, IBM, Mellanox, Micron, Xilinx ‒ genzconsortium.org OpenCAPI: Open Coherent Accelerator Processor Interface ‒ Formed September, 2016 ‒ Founding members include: AMD, Google, IBM, Mellanox, Micron ‒ opencapi.org 5 5 | OpenSHMEM Workshop | August 8, 2017 NEWLY EMERGING BUS/INTERCONNECT STANDARDS Motivations for these new standards Tighter coupling between processors and accelerators (GPUs, FPGAs, etc.) ‒ unified, virtual memory address space ‒ reduce data movement and avoid data copies to/from accelerators ‒ enables sharing of pointer-based data structures w/o the need for deep copies Open, non-proprietary standards-based solutions Higher bandwidth solutions ‒ 25Gbs and above vs. 16Gbs forPCIe-Gen4 Better exploitation of new and emerging memory/storage technologies ‒ NVMe ‒ Storage class memory (SCM),
    [Show full text]
  • A Review of Detection of USB Malware Dr
    ISSN XXXX XXXX © 2017 IJESC Research Article Volume 7 Issue No.7 A Review of Detection of USB Malware Dr. Sunil Sikka1, Utpal Srivastva2, Rashika Sharma3 Associate Professor1, Assistant Professor2, M.Tech Student3 Department of Computer Science & Engineering Amity University Haryana, India Abstract: USB device is a very common device now days and because of its user friendly nature and ease. It is used by massive group of people. The hackers are taking advantage of this technology and planning a malware inside the usb device. It is also one of generally focus technologies by hackers. The usb with a malware is known as BAD USB; generally the malware is present in the firmware of the usb so it remains undetectable. As the firmware of the device is not scanned by the system and other applications. This flaw is the serious risk to our operation system as the malware can be undetected and it can come easy into our operating system (OS), without even the knowledge of the users. Keywords: Bad USB, Malware, HID (Human Interface Device), Firmware, Operating system (OS), USB, CMD I. INTRODUCTION device that communicates over USB is susceptible to this attack. We observe that the root cause of the Bad USB attack is a lack Hackers can easily plant a malware in the usb device and that of access control within the enumeration phase of the USB usb with a malware is known as “Bad USB”. Recently security protocol. researchers have disclosed this vulnerability and hackers are taking full advantage of this by planting a malware in the USB 1.1 BUILDING A BAD USB DEVICE device.[L] The malware remains undetected as it is present in the 1.
    [Show full text]
  • Quikchill : Thermoelectric Water Cooler Franz Louie Chua Santa Clara University
    Santa Clara University Scholar Commons Mechanical Engineering Senior Theses Engineering Senior Theses 6-15-2013 Quikchill : thermoelectric water cooler Franz Louie Chua Santa Clara University Brandon Ohara Santa Clara University Rachel Reid Santa Clara University Bernadette Tong Santa Clara University Follow this and additional works at: http://scholarcommons.scu.edu/mech_senior Part of the Mechanical Engineering Commons Recommended Citation Chua, Franz Louie; Ohara, Brandon; Reid, Rachel; and Tong, Bernadette, "Quikchill : thermoelectric water cooler" (2013). Mechanical Engineering Senior Theses. Paper 12. This Thesis is brought to you for free and open access by the Engineering Senior Theses at Scholar Commons. It has been accepted for inclusion in Mechanical Engineering Senior Theses by an authorized administrator of Scholar Commons. For more information, please contact [email protected]. QUIKCHILL: THERMOELECTRIC WATER COOLER by Franz Louie Chua, Brandon Ohara, Rachel Reid, and Bernadette Tong THESIS Submitted in Partial Fulfillment of the Requirements for the Bachelor of Science Degree in Mechanical Engineering in the School of Engineering Santa Clara University, 2013 Title page Santa Clara, California QUIKCHILL: THERMOELECTRIC WATER COOLER Franz Louie Chua, Brandon Ohara, Rachel Reid, and Bernadette Tong Department of Mechanical Engineering Santa Clara University Santa Clara, California 2013 Abstract Motivated by the increasing residential energy utilization projections and the fact that water and ice dispensers consume 20% of total refrigerator energy, a thermoelectric water chiller was designed to provide a more energy efficient alternative. Implementing the chiller under the sink provides a convenient means to source cold, filtered water, thereby eliminating the need for water and nice dispensers as well as filtering pitchers.
    [Show full text]