Survey and Benchmarking of Machine Learning Accelerators

1 Survey and Benchmarking of Machine Learning Accelerators Albert Reuther, Peter Michaleas, Michael Jones, Vijay Gadepally, Siddharth Samsi, and Jeremy Kepner MIT Lincoln Laboratory Supercomputing Center Lexington, MA, USA freuther,pmichaleas,michael.jones,vijayg,sid,[email protected] Abstract—Advances in multicore processors and accelerators components play a major role in the success or failure of an have opened the flood gates to greater exploration and application AI system. of machine learning techniques to a variety of applications. These advances, along with breakdowns of several trends including Moore’s Law, have prompted an explosion of processors and accelerators that promise even greater computational and machine learning capabilities. These processors and accelerators are coming in many forms, from CPUs and GPUs to ASICs, FPGAs, and dataflow accelerators. This paper surveys the current state of these processors and accelerators that have been publicly announced with performance and power consumption numbers. The performance and power values are plotted on a scatter graph and a number of dimensions and observations from the trends on this plot are discussed and analyzed. For instance, there are interesting trends in the plot regarding power consumption, numerical precision, and inference versus training. We then select and benchmark two commercially- available low size, weight, and power (SWaP) accelerators as these processors are the most interesting for embedded and Fig. 1. Canonical AI architecture consists of sensors, data conditioning, mobile machine learning inference applications that are most algorithms, modern computing, robust AI, human-machine teaming, and users (missions). Each step is critical in developing end-to-end AI applications and applicable to the DoD and other SWaP constrained users. We systems. determine how they actually perform with real-world images and neural network models, compare those results to the reported performance and power consumption values and evaluate them On the left side of Figure 1, structured and unstructured against an Intel CPU that is used in some embedded applications. data sources provide different views of entities and/or phe- nomenology. These raw data products are fed into a data con- Index Terms—Machine learning, GPU, TPU, dataflow, accelerator, embedded inference ditioning step in which they are fused, aggregated, structured, accumulated, and converted to information. The information generated by the data conditioning step feeds into a host I. INTRODUCTION of supervised and unsupervised algorithms such as neural networks, which extract patterns, predict new events, fill in Artificial Intelligence (AI) and machine learning (ML) have missing data, or look for similarities across datasets, thereby the opportunity to revolutionize the way many industries, converting the input information to actionable knowledge. arXiv:1908.11348v1 [cs.PF] 29 Aug 2019 militaries, and other organizations address the challenges of This actionable knowledge is then passed to human beings evolving events, data deluge, and rapid courses of action. for decision-making processes in the human-machine teaming Innovations in computations, data sets, and algorithms have phase. The phase of human-machine teaming provides the driven many advances for machine learning and its application users with useful and relevant insight turning knowledge into to many different areas. AI solutions involve a number of actionable intelligence or insight. different pieces that must work together in order to provide Underlying all of these phases is a bedrock of modern capabilities that can be used by decision makers, warfighters, computing systems that is comprised of one or more heteroge- and analysts; Figure 1 depicts these important pieces that are nous computing elements. For example, sensor processing may needed when developing an end-to-end AI solution. While occur on low power embedded computers, while algorithms certain components may not be as visible to end-users as may be computed in very large data centers. With regard to others, our experience has shown that each of these interrelated performance advances in these computing elements, Moore’s This material is based upon work supported by the Assistant Secretary of law trends have ended [1], as have a number of related Defense for Research and Engineering under Air Force Contract No. FA8721- laws and trends including Denard’s scaling (power density), 05-C-0002 and/or FA8702-15-D-0001. Any opinions, findings, conclusions or clock frequency, core counts, instructions per clock cycle, and recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the Assistant Secretary of Defense for instructions per Joule (Koomey’s law) [2]. Many of the tech- Research and Engineering. nologies, tricks and techniques of processor chip designers that 2 extended these trends have been exhausted. However, all is not including integer representations, have been shown to lost, yet; advancements and innovations are still progressing. be reasonably effective for inference [7], [8]. However, In fact, there has been a Cambrian explosion of computing it has also generally been established that very limited technologies and architectures in recent years. Specializa- numerical precisions like int4, int2, and int1 do not tion of circuits for certain functionalities is being exploited adequately represent model weight parameters and sig- whereby certain often-used operational kernels, methods, or nificantly affect model output predictions. functions are being accelerated with specialized circuit blocks The survey in the next section of this paper focuses on the and chips. These accelerators are designed with a different computational throughput of the processors and accelerators balance between performance and functional flexibility. One along with the power that is consumed to achieve that perfor- area in which we are seeing an explosion of accelerators is mance. Other factors include the memory bandwidth to load ML processors and accelerators [3]. Understanding the relative and update model parameters and data; memory capacity for benefits of these technologies is of particular importance to model weight parameters and input data, both close to the applying AI to domains under significant constraints such as arithmetic units and the global memory of the processors and size, weight, and power, both in embedded applications and accelerator; and arithmetic intensity [9] of the neural network in data centers. models being processed by the processor or accelerator. These But before we get to the survey of ML processors and factors are involved in managing model parameters and input accelerators, we must cover several topic that are important for data flows within the model; hence, they also influence the understanding several dimensions of evaluation in the survey. trade-offs between chip bandwidth capabilities, data flow We must discuss the types of neural networks for which these flexibility, and configuration and amount of computational ML accelerators are being designed; the distinction between capability. These factors, however, are beyond the scope of neural network training and inference; and the numerical this paper, and they will be addressed in future phases of this precision with which the neural networks are being used for research. training and inference: II. SURVEY OF PROCESSORS • Types of Neural Networks – AI and machine learning encompass a wide set of statistics-based technologies as Many recent advances in AI can be at least partly credited one can see in the taxonomy detailed in the algorithm to advances in computing hardware [10], [11]. In particular, section (Section 3) of this MIT Lincloln Laboratory modern computing advances have been able to realize many technical report [4]. Even among neural networks, there computationally heavy machine-learning algorithms such as are a growing number of neural network patterns [5]. neural networks. While machine-learning algorithms such as This paper will focus on processors that are geared neural networks have had a rich theoretic history [12], recent toward deep neural networks (DNNs) and convolutional advances in computing have made the application of such neural networks (CNNs). Overall, the most emphasis of algorithms a reality by providing the computational power computational capability for machine learning is on DNN needed to train and process massive quantities of data. Al- and CNNs because they are quite computationally inten- though the computing landscape of the past decade has been sive [6], with the fully connected and convolutional lay- rich with numerous innovations, more embedded and mobile ers being the most computationally intense. Conversely, applications that require low size, weight, and power (SWaP) pooling, dropout, softmax, and recurrent/skip connection systems will need capabilities that are beyond those delivered layers are not computationally intensive since these types by the traditional architectures of central processing units of layers stipulate datapaths for weight and data operands. (CPUs) and graphics processing units (GPUs). For example, • Neural Network Training versus Inference – Neural net- in commercial applications, it is common to off-load data work training uses libraries of input data to converge conditioning and algorithms to non-SWaP constrained plat- model weight parameters by applying the labeled input forms such high-performance

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