Porting Choices to ARM Architecture Based Platforms Francis M
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Porting Choices to ARM Architecture Based Platforms Francis M. David, Ellick M. Chan, Jeffrey C. Carlyle, Roy H. Campbell Department of Computer Science University of Illinois at Urbana-Champaign ffdavid,emchan,jcarlyle,[email protected] http://choices.cs.uiuc.edu/ Draft of 2007/01/12 15:12 Abstract initial code base for the ARM port. We chose to start with the SPARC port of Choices because it was the most Choices, an object-oriented operating system, has been used and tested port of Choices. All of the SPARC ported to the ARM architecture. The porting effort was code was copied to an ARM directory and names were based on the exising code-base for the SPARC pro- changed from SPARC to ARM. Machine dependent cessor based SPARCStation 1. Choices supports two code was copied and renamed from SS1 (SPARCStation ARM-based machine configurations: the Texas Instru- 1) to OMAP. All code that did not compile correctly was ments OMAP 1610 and the ARM Integrator as emulated excluded from the build using preprocessor #ifdef state- by QEMU. Choices on ARM supports virtual memory, ments and placing an Assert(NOTREACHED) state- write-back data caching and interrupt management with ment which, when executed, causes Choices to stop and support for serial I/O and timers. An environment con- display an error message with the filename and line num- sisting of X10-based remote power control devices, net- ber where the Assert was encountered. The porting worked serial ports and comprehensive build scripts en- effort proceeded by repeatedly booting Choices and fix- able short development cycles with the OMAP hard- ing excluded code whenever we encountered the corre- ware. The QEMU based virtual hardware presented sponding Assert statement. powerful debug capabilities useful for developing an op- Apart from porting SPARC code to ARM, we also erating system for the ARM. re-wrote parts of Choices for enhancements and clarity. Kernel debugging support was revamped and extended 1 Introduction to support core functionality from the current version of Choices is an object-oriented operating system devel- the remote GDB protocol [6]. The original GDB func- oped at the University of Illinois at Urbana-Champaign. tionality in Choices was confined to processor dependent The components of the system are encapsulated in code for SPARC. This was split into processor depen- classes and present a flexible design for management dent and processor independent parts. Processor depen- and extensibility. Choices originally supported National dent GDB stub code was added for the ARM. Semiconductor NS32332 based Encore Multimax ma- We also re-wrote the framework for handling proces- chines, Sun SPARC machines [1] and Intel Pentium pro- sor interrupts. A machine and processor independent cessor based machines [2]. InterruptManager is used to handle and dispatch inter- The ARM architecture has become tremendously rupts. A machine dependent class subclasses the Inter- popular in the embedded devices market space, includ- ruptManager and provides methods to interact with the ing the booming mobile device market. The modularity hardware. and extensibility inherent in Choices is a perfect match Pre-emptive context switching was also re-written for for the needs of a mobile device in a dynamic envi- ARM. In the original design, when handling a time-slice ronment. This paper describes our efforts in porting interrupt, the interrupt thread would directly switch con- Choices to two ARM-based platforms: the Texas In- text to the new process. This interfered with proper func- struments OMAP1610 based H2 development boards [3] tioning of the InterruptManager. So, the implementa- and the ARM Integrator CP platform [4] emulated by tion was re-written so that the context switch only oc- QEMU [5]. We first ported Choices to the OMAP hard- curs when the interrupt thread returns back through the ware; experience from the OMAP port and the conve- normal interrupt return mechanism. nience of the QEMU emulator allowed the later Integra- During the porting process, we added support for the tor port to be completed in a short time period. compressed ROM file system (cramfs) to Choices be- We decided to use the SPARC port of Choices as the cause all of the existing Choices file system drivers were 1 unusable. This is a read-only file system that was de- and interrupts. signed for simplicity and space efficiency. The cramfs The ARM architecture has 37 registers as shown in ta- file system is currently used as the root file system for ble 2. 31 of these registers are general purpose registers both the Choices ARM ports. We discuss file system including a program counter and 6 are status registers. support in more detail in section 8. Some of these registers are banked and are hidden ex- One of the challenges encountered with porting cept when executing in specific processor modes. These Choices to the ARM platform was the lack of a suit- registers such as the stack pointer are automatically able secondary storage device that we could use. The switched when entering a different processor mode. This Choices source base includes hard disk drivers; however, design allows fast processing of interrupts as the handler our target ARM platforms do not include a hard disk code does not need to manually switch to a new stack. drive. The OMAP and Integrator platforms include flash An application normally has access to 16 general pur- devices that could be used for secondary storage; how- pose registers (R0-R15) and one current program sta- ever, Choices does not have a flash device driver. For the tus register (CPSR). The following registers have spe- purposes of an initial port, we created a pseudo RAM cial meaning: R15 is the program counter (PC), R14 is disk device which stores all its data in volatile SDRAM. the link register (LR). By convention, the other general Choices expects a root file system to exist on this device purpose registers are assigned meanings as well: R13 is and mounts this file system during the boot process. The the stack pointer (SP), R12 is the scratch register (IP), file system image is pre-loaded into RAM by the boot- R11 is the frame pointer (FP) and R10 is the stack limit loader. (which is currently unused). Registers R4-R9 are callee- The remainder of this paper is organized as follows. preserved. Registers R0-R3 are used to pass arguments A brief overview of the ARM architecture is presented and return values when performing function calls. These in section 2. Some standards that are used for ARM soft- register usage conventions are defined by an Application ware development are discussed in section 3. Section 4 Binary Interface (ABI); the ABI is discussed in more de- is a high-level introduction to the Choices kernel archi- tail in section 3. tecture and organization. The computing environment A special set of banked registers, namely, saved pro- used to develop the Choices ARM ports is described in gram status registers (SPSR) are used to save a copy section 5. Section 6 describes ARM processor depen- of CPSR when switching modes and are not accessible dent changes that were required. OMAP and Integra- from the ARM SYS or ARM USR modes. tor machine dependent changes are documented in sec- The ARM processor enters special interrupt han- tion 7.1. We discuss the file system implementations in dling modes when certain events occur. These events Choices in section 8. Section 9 documents the develop- and modes are shown in table 3. When an in- ment time-line for the porting effort. Section 10 has a terrupt is received, the PC register is set to either short performance evaluation of the Choices ARM port. 0x00000000+offset or 0xFFFF0000+offset depending Section 11 summarizes our work and draws conclusions. on whether the processor is configured to use low or high In this paper, words in italics, such as InterruptMan- interrupt vectors. ager refer to Choices classes. The ARM processor supports address translation via an MMU (Memory Management Unit). The MMU uses 2 ARM Architecture Overview a two-level page table to map virtual to physical ad- ARM is a 32 bit RISC architecture. It supports a na- dresses. Each first level page table entry can directly tive full-fledged 32-bit instruction set. ARM also spec- specify a mapping for a 1MB memory region. A first ifies two other instruction sets: a 16-bit compressed level entry may also indirect to a second level page ta- RISC set called Thumb, and an 8-bit instruction set for ble, which maps memory in increments of either 16 KB, Java byte-codes called Jazelle. These are only available 4 KB, or 1 KB. Both first level and second level entries on selected versions of the ARM processor core. The include bits that determine access permissions based on ARM926EJ-S processor in the TI OMAP1610 H2 board processor mode. The entries also include bits that de- and the ARM1026EJ-S processor in the Integrator con- termine the caching policy used for the covered virtual form to the ARMv5 architecture generation and support memory region. both these extended instruction sets. Newer processors The ARMv5 architecture uses a split (Harvard) cache use ARMv6 and ARMv7. Choices only has support for architecture with separate instruction and data caches. ARMv5 but does not use Thumb or Jazelle. The cache can be disabled, configured for write-through The ARM processors in both the OMAP and the In- or write-back for individual pages. An on-chip write tegrator support seven modes of operation. There are buffer can be used to queue writes to memory. It also shown in table 1.