Common Drain Stage (Source Follower)

Claudio Talarico, Gonzaga University

Common Drain Stage

vgs = vi - vo

vbs = - vo VDD

RS VvIiN C C+C gd gdg b B&D vi G vs V vOoU T + VS C r gmvgs -gmbvo vgs gs o IB RL CL - vo S V B RL Csb+CL

EE 303 – Common Drain Stage 2

CD Bias Point

VDD § Assume VB=VOUT, so ID=IB

RS VIN VOUT = VIN −VGS I VOUT D VGS = VT + VS 0.5COXW / L I R B L V V PHI V PHI T = T 0 +γ ( + OUT − )

VB VDS = VDD −VOUT = VDD −VIN +VGS

§ For M1 to be in saturation

VDS > VOV = VGS +VT !

VDD −VIN +VGS > VGS +VT

! This is almost always the case

VIN < VDD +VT in practical realizations

EE 303 – Common Drain Stage 3

I/O DC characteristic (1)

Example: DC Transfer Function − 1 um Technology 5 VIN = 2.5V; I1=400µA; 4.5 VDD=5V; W/L=100µm/1µm Vout 4 Vth M1 triode 3.5 VDD-Vth ≈ 3.43 V 3

Source: Razavi [V] 2.5 out

V 2 M operation 1 1.5 6

1

5 0.5 Vds=Vdd−Vout 0 4 Vov=Vin−Vout−Vth 0 1 2 3 4 5 6 7 8 V [V] in ≅ 3 AV (@ VIN = 2.5V) 0.821 M1 sat. Math “artifact” due to ideal current source

2 (a current source can take any voltage value across it !!)

1 M1 triode § Vout(min) ≈ 0 0 0 1 2 3 4 5 6 7 8 § Vout(max) ≈ VDD-Vth V [V] in EE 303 – Common Drain Stage 4

I/O DC characteristic (2)

Example: DC Transfer Function − 1 um Technology 5 VIN = 2.5V; I =400 A; 1 µ 4.5 VDD= 5V; V = 0.9V; 4 I1 B W/L=100µm/1µm; 3.5

3 Vout=Vds2 element 0:m1 0:m2

[V] Vov2 model 0:simple_n 0:simple_n 2.5 region Saturati Saturati out Vds1 id 452.1261u 452.1261u V 2 Vov1 ibs -13.0315f 0. ibd -50.0000f -13.0315f 1.5 vgs 1.1968 900.0000m vds 3.6968 1.3032 vbs -1.3032 0. 1 vth 833.4784m 500.0000m vdsat 363.3703m 400.0000m 0.5 vod 363.3703m 400.0000m beta 6.8484m 5.6516m 0 gam eff 600.0000m 600.0000m 0 1 2 3 4 5 6 7 8 V [V] gm 2.4885m 2.2606m in gds 33.0095u 40.0000u gmb 514.7852u 758.2384u M off 2 M2 triode M2 sat M2 sat cdtot 72.3963f 93.2122f M sat M sat cgtot 256.5245f 256.4846f 1 1 M1 sat M1 triode cstot 246.1466f 286.3341f cbtot 66.1318f 128.5634f § Reduced output (and input) swing cgs 203.3341f 203.3341f - V (max) = V – V cgd 51.1337f 50.3996f out DD OV1 - Vout(min) = VOV2 * measurement EE 303 – Common Drain Stage 5 av0= 808.9285m CD Voltage Transfer

' 1 $ v % sC sC " v sC g v v 0 o % Ltot + gs + " − i gs − m ( i − o )= & RLtot #

vi v g + sC o = m gs + 1 g v vi v Cgs m gs g + sC + sC + gs m gs Ltot R - Ltot LHP C +C v gd gb o zero C R Ltot Ltot sC 1+ gs v g g o = m ⋅ m = 1 vi s(Cgs +CLtot ) gm + 1+ RLtot 1 gm + 1 RLtot CLtot = CL + Csb RLtot = RL || || ro g s mb 1− = a ⋅ z v0 s ≅ 1 1− often RLtot /gmb p EE 303 – Common Drain Stage 6

Low Frequency Gain

g 1 a = m R = R || || r v0 1 Ltot L o gmb gm + RLtot § Interesting cases V DD – Ideal current source; PMOS with source tied to body; no load resistor;

RL=∞, ro=∞, gmb= 0 Vo

Vi C L a =1 Yin v0

V DD – Ideal current source; NMOS; no load resistor;

V i RL=∞, ro=∞, gmb≠0

V o gm av0 = (typically ≅ 0.8) I R C B L L gm + gmb

– Ideal current source, PMOS with source tied to body; load resistor r =∞, g =0, R finite g o mb L a = m v0 1 gm + EE 303 – Common Drain Stage 7 RL

Low frequency input and output resistances

Rin Rout RS vin vout vs

gmvin ro 1/gm 1/gmb RL

a = g / (g’ +1/r +1/R ) v0 m m o L

§ Rin = ∞

§ Rout = ro || (1/g’m)

EE 303 – Common Drain Stage 8

High Frequency Gain

gm av0 = g'm +1/ ro +1/ RL s 1 1− g g + vo z m m av (s)= = av0 ⋅ z = − RLtot v s C p = − i 1− gs C + C p gs Ltot

§ Three scenarios: The presence of a LHP zero leads to the possibility that the pole and zero |z|<|p| |z|>|p| |z|=|p| will provide some degree of cancellation, |a (s)| |a (s)| |a (s)| v v v leading to a broadband response

av0 av0 av0

f f f (infinite bandwidth ?!?)

EE 303 – Common Drain Stage 9

CD Input Impedance

Consistent with insight from § By inspection: Miller Theorem Hint: Yin = sCgd + sCgs (1− av (s)) i=Cgs(vi-vo) vi

Yin + § Gain term av(s) is real and close to unity C gmvgs vgs gs up to fairly high frequencies - C +C v gd gb o § Hence, up to moderate frequencies, we

CLtot RLtot see a capacitor looking into the input

– A fairly small one, Cgd, plus a fraction of Cgs

EE 303 – Common Drain Stage 10

CD input impedance for PMOS stage (with Body-source tie)

VDD § gmb generator inactive – Low frequency gain very close g r >> 1 IB to unity m o g vOVUT m out av0 = ≅1 Cgs 1 g + CL m r Cbsub o vVIinN § Very small input capacitance Cgd CCin @ ≈ C Cgd in gd Yin = sCgd + sCgs (1− av (s))

Yin ≅ sCgd for av=1 (Vout=Vin) no current flows

through Cgs(perfect bootstrap)

§ The well-body capacitance Cbsub can be large and may significantly affect the 3-db bandwidth

EE 303 – Common Drain Stage 11

CD Output Impedance (1)

§ Let's first look at an analytically simple case – Input driven by ideal voltage source

1 1 Zout = + gm + gmb s(Cgs + Csb ) C gmvgs vgs gs - vo Cgd+Cgb

Zout Csb 1/gmb ZL AC shorted Low output impedance • Resistive up to very high frequencies YL=sCL+1/RL

EE 303 – Common Drain Stage 12

CD Output Impedance (2)

§ Now include finite source resistance

vg

Ri g (v -v ) Cgs m g o

Zx Zout Cgd+Cgb vo i x Csb 1/gmb ZL Neglect Cgd

Neglecting Cgd " v % v R i = v − v g + sC = v 1− g g + sC g ≅ i x ( o g )( m gs ) o $ '( m gs ) 1 # vo & vo + Ri " % sCgs $ ' 1+ sR C 1+ sR C vo i gs 1 $ i gs ' Zx = ≅ = i g + sC g $ sCgs ' x m gs m $ 1+ ' # gm &

EE 303 – Common Drain Stage 13

CD Output Impedance (3)

1 1+ sRiCgs Z ≅ ( ) x g " sC % m $1+ gs ' # gm & NOTE: Typically 1/gm is small, § Two interesting cases so this can happen !!

R < 1/g i m Ri > 1/gm

|Zx(s)| |Zx(s)|

1/gm 1/gm

f f

Inductive behavior!

EE 303 – Common Drain Stage 14

Equivalent Circuit for Ri > 1/gm

for s 0 Z 1/ g 1 (1+ sRiCgs ) = ⇒ x = m Zx ≅ g " sC % for s → ∞ ⇒ Zx = Ri m $1+ gs ' # gm & Z Z x out 1 R1 || R2 = R1 gm for s = 0 ⇒ Zx = R1 || R2 R2 Csb 1/gmb R = R for s → ∞ ⇒ Z = R 2 i x 2 L R2C L = i gs gm Ri −1 L 1+ (R + sL)R R R R Z = 1 2 = 1 2 1 x R + R + sL R + R L 1 2 1 2 1+

R1 + R2 § This circuit is prone to ringing! – L forms an LC tank with any capacitance at the output – If the circuit drives a large capacitance the response to step-like signals will result in ringing

EE 303 – Common Drain Stage 15

Inclusion of Parasitic Input Capacitance*

What happens to the output impedance if we don’t neglect Ci=Cgd ? * Hint: replace Ri with 1+ sR C +C Ri 1 ( i ( gs i )) Zi = Zx = Ri + sCiRi gm ! sCgs $ #1+ &(1+ sRiCi ) " gm %

€ 1 g 1 1 1 g < m < < < m R C +C R C C Ri (Cgs +Ci ) Cgs RiCi i ( gs i ) i i gs

|Z (s)| |Zx(s)| x

1/gm 1/gm

f f

EE114 EE 303 – Common Drain Stage 16

Applications of the Common Drain Stage

§ Level Shifter § Voltage Buffer § Load Device

EE 303 – Common Drain Stage 17

Application 1: Level Shifter

Vi=VGS +Vo

VDD Vo=Vi – VGS= Vi – (Vt+VOV)

Vi

VGS=Vt+Vov ≅ const. Vo

IB

§ Output quiescent point is roughly Vt+Vov lower than input quiescent point § Adjusting the W/L ratio allows to “tune” Vov (= the desired shifting level)

EE 303 – Common Drain Stage 18

Why is lowering the DC level useful ?

§ When building cascades of CS and CG amplifiers, as we move along the DC level moves up

§ A CD stage is a way to buffer the signal, and moving down the DC level

EE 303 – Common Drain Stage 19

Application 2: Buffer

VDD

VVBB1

IB1 RD (large) M1

vx Rout vVooutut Vvinin MX I RL M2 B2 (small)

VB2

§ Low frequency voltage gain of the above circuit is ~gmRbig

– Would be ~gm(Rsmall||Rbig) ~ gmRsmall without CD buffer stage

§ Disadvantage Vout (max) = VDD −VOV1 – Reduced swing Vout (min) = VOV 2

EE 303 – Common Drain Stage 20

Buffer Design Considerations

VDD V § Without the buffer the minimum VBB1 allowable value of Vx for Mx to IB1 RD (large) M1 remain in saturation is: VX > VGSX – Vthx vx Rout Vx vVououtt § With the buffer for M2 to remain in sat. Vviinn MX it must be: V M RL B IB22 (small) VX > VGS1+VGS2-Vth2

VB2

§ Assuming the overdrive of Mx and M2 are comparable this means that the allowable swing at X is reduced by VGS1 which is a significant amount (VGS1=VOV1 +Vth1)

EE 303 – Common Drain Stage 21

Application 3: Load Device

Looks familiar ? “CS stage with diode connected load”

V DD § Advantages compared to resistor load – "Ratiometric" M2 • Gain depends on ratio of similar parameters 1/(g +g ) m2 mb2 • Reduced process and temperature variations Vo – First order cancellation of nonlinearities Vi M1 § Disadvantage – Reduced swing

Vout (max) = VDD −V th2

gm1 Vout (min) = VIN −V th1= VOV1 av0 = gm2 + gmb2

EE 303 – Common Drain Stage 22

CD stage Issues

§ Several sources of nonlinearity

– Vt is a function of Vo (NMOS, without S to B connection) V = V +γ PHI +V − PHI t t 0 ( o ) 1 W 2 – I and thus V changes with V ID = µCOX (VGS −Vt ) D ov o 2 L • Gets worse with small RL

If we worry about distortion we need to keep ΔVin/2VOV small (à we need large VOV, and this affect adversely signal swing). If RL is small, things are even worse because to obtain the desired ΔVout we need more ΔVin (and so even more VOV)

ΔVout gm ≈ Small RL means less gain ΔVin g'm +1/ RL

§ Reduced input and output voltage swing

– Consider e.g. VDD=1V, Vt=0.3V, VOV=0.2V (VGS=Vt+Vov=0.5V) • CD buffer stage consumes 50% of supply headroom!

– In low VDD applications that require large output swing, using a CD buffer is often not possible – CD buffers are more frequently used when the required swing is small • E.g. pre-amplifiers or LNAs that turn µV into mV at the output EE 303 – Common Drain Stage 23

Summary – Elementary Transistor Stages

§ Common source – VCCS, makes a good voltage amplifier when terminated with a high impedance § Common gate – Typically low input impedance, high output impedance – Can be used to improve the intrinsic voltage gain of a common source stage • "Cascode" stage § Common drain – Typically high input impedance, low output impedance – Great for shifting the DC operating point of signals – Useful as a voltage buffer when swing and nonlinearity are not an issue

EE 303 – Common Drain Stage 24

CD Voltage Transfer Revisited (1)

§ The driving circuit has a finite resistance R example: if RS is the output s resistance of a CS stage it can be relatively large CD Core Zin Zout RS vin vout

Cgs vs Cgd 1/g’m Csb RL CL gmvin ro||1/g’m

R || C tot tot § This model resembles the model of the CS stage - The main difference is in the polarity of the controlled source - This difference has profound impact on the Miller amplification of the capacitance coupling input and output

EE 303 – Common Drain Stage 25

CD Voltage Transfer Revisited (2)

C 1+ s gs vout gm = av0 ⋅ 2 vs 1+ b1s + b2s

av0 = gm Rtot

b1 = RsCgs (1− av0 )+ RSCgd + RtotCgs + RtotCtot

b2 = RS Rtot (CgsCgd +CgsCtot +CgdCtot )

§ The zero in the transfer function is on the LHP and it occurs at

approximately ωT

§ Unfortunately the high frequency analysis can become quite involved. A dominant real pole does not always exist, in fact poles can be complex. In the case the poles are complex a designer should be careful that the

circuit does not exhibit too much overshoot and ringing.

EE 303 – Common Drain Stage 26

CD Voltage Transfer Revisited (3)

C C 1+ s gs 1+ s gs vout gm gm = av0 ⋅ 2 = av0 ⋅ 2 vs 1+ b1s + b2s s s 1+ + 2 ω0Q ω0

§ Interesting cases: 1 - A dominant pole condition exist ω ≅ b = τ 3dB b ( 1 ∑ j ) - Poles are complex 1

A dominant pole condition exist for: Q2 << 1/4

b2 2 <<1/ 4 b1

EE 303 – Common Drain Stage 27

Poles Location

2 s s § Roots of the denominator of the transfer function: 1+ + 2 = 0 ω0Q ω0

§ Complex Conjugate poles Poles location with Q> 0.5 (overshooting in step response) jω

ω 2 for Q > 0.5 ⇒ s = − 0 1± j 4Q −1 1,2 2Q ( ) φ = - For Q = 0.707 (φ=45°), the -3dB frequency is ω0 σ (Maximally Flat Magnitude or Butterworth Response)

- For Q > 0.707 the frequency response has peaking

§ Real poles (no overshoot in the step response)

ω0 2 for Q ≤ 0.5 ⇒ s1,2 = − 1± 1− 4Q Source: 2Q ( ) Carusone

EE 303 – Common Drain Stage 28

Frequency Response

|H(s)| 10

5

0 1 H(s) = 2 s s −5 1+ + 2 ω0Q ω0 Q=0.5 Magnitude [dB] −10 Q=1/sqrt(2) Q=1 −15 Q=2

−20 −2 −1 0 1 10 10 10 10 / 0

EE 303 – Common Drain Stage 29

Step Response

Source: “Underdamped” Q > 0.5 Carusone

Q=0.5

“Overdamped” Q > 0.5

time

§ Ringing for Q > 0.5 § The case Q=0.5 is called maximally damped response (fastest settling without any overshoot)

EE 303 – Common Drain Stage 30