Common Drain Amplifier Or Source Follower

Common Drain Amplifier or Source Follower

Figure 1(a) shows the source follower with ideal current source load. Figure 1(b) shows the ideal current source implemented by NMOS with constant gate to source voltage.

VDD VDD

M1 Vi M1 Vi

Vo Vo VTN+∆V

+ M2 VG ∆V

- VT0+∆V

(a) (b)

Figure 1. Common drain or source follower implementation.

1. Low Frequency Small Signal Equivalent Circuit

V1 = Vi , V2 = Vo ,Vbs1 = - Vo , Vgs1 = Vi - Vo = V1 - V2

YL = g ds2 (or ZL = rds2 ), YS = ∞(or ZS = 0)

From Figure 2(e),

I1 = 0

I 2 = −g m1vgs1 + (g mb1 + g ds1 )Vo = −g m1 (V1 - V2 ) + (g mb1 + g ds1 )V2

= -g m1V1 + (g m1 + g mb1 + g ds1 )V2

1 G1 D1 G1 D1 + +

vgs1 gm1vgs1 g vgs1 gm1vgs1 g gmb1vbs1 ds1 gmb1vo ds1 S D S D Vi 1 2 + Vi 1 2 +

g g ds2 Vo ds2 Vo S2 S2 - (a) - - (b) -

S G1 D1 G1 D1 2 + +

vgs1 gm1vgs1 g g vgs1 gm1vgs1 g g mb1 ds1 gmb1 ds1 ds2

S D S D Vi 1 2 + Vi 1 2 +

g V ds2 o Vo S2 (c) (d) - - - -

vgs1 I1 I2 S1 D2 G1 + + + + Y V V1 2 Y V Vo L i gm1vgs1 g g gmb1 ds1 ds2 - -

D1 S2 Zi Zo

(e) (f)

Figure 2. Source follower low frequency small signal equivalent circuit.

2 The corresponding Y-parameter matrix is,

 0 0  Y =   − g m1 g m1 + g mb1 + g ds1  detY = 0

The Source Follower Properties:

y 22 + YL (g m1 + g mb1 + g ds1 ) + g ds2 Zi = = = ∞ detY + y11YL 0 + (0)g ds2

y11 + YS 1 1 Zo = = = detY + y 22 YS y 22 g m1 + g mb1 + g ds1

− y 21 − (−g m1 ) g m1 A V0 = = = ≈ 1 y 22 + YL (g m1 + g mb1 + g ds1 ) + g ds2 g m1 + g mb1 + g ds1 + g ds2

A V = g m1 (Zo // ZL )

− y 21YL − g m1g ds2 A I = = = ∞ detY + y11YL 0 + (0)g ds2

3 2. High Frequency Small Signal Equivalent Circuit

VDD

C gd1 Cdb1 Vi M1

Cgs1 Csb1 Vo

Cgd2 Cdb2 CL VG M2

Figure 3. Source follower parasitic capacitances.

Figure 3 shows all the parasitic capacitances of source follower circuit. Figure 4 shows the high frequency small signal equivalent circuit. From Figure 4, one obtains,

a a b b b b a b V1 = VS , V2 = Vi = V1 , V2 = Vo , v gs1 = V1 - V2 , I 2 = -I1

G O = g mb1 + g ds1 + g ds2 , CO = Csb1 + Cdb2 + Cgd2 + C L

The network a current equation is:

a a a I1 = (G S + sCS )(V1 - V2 ) a a a I 2 = (G S + sCS )(V2 - V1 )

4 C G1 gd1 D1

v o V gs1 gs1 1 v C mb gs1 m1 gds1 g g

D2 C G S1 + IS S S (a) Vo C Csb1 db2 Cgd2 C gds2 L S2 -

(a)

+-vgs1 G1 S1 D2 + + Cgs1 1 gs

C v Vi gd1 g C Vo I CS GS m1 gmb1 ds1 gds2 o S - g - D1 S2 Co=Csb1+Cdb2+Cgd2+CL

(b) +-vgs1 G S G1 S1 D2 + + Cgs1 + CS gs1 Vi Cgd1 v g C Vo VS m1 gmb1 ds1 gds2 o - g - D1 S2 Co=Csb1+Cdb2+Cgd2+CL

Z b i (d)

Figure 4. Source follower high frequency small signal equivalent circuit.

5 The corresponding Y-parameter matrix is :

a  (G S + sCS ) − (G S + sCS ) Y =   − (G S + sCS ) (G S + sCS ) 

The network b current equation is:

b b b b b b I1 = sCgd1V1 + sCgs1 (V1 - V2 ) = s(Cgd1 + Cgs1 )V1 − sCgs1V2 b b b b b b b b b I 2 = −g m1Vgs1 + sCgs1 (V2 - V1 ) + (G o + sCo )V2 = −g m1 (V1 - V2 ) + sCgs1 (V2 - V1 ) + (G o + sCo )V2 b b = -(gm1 + sCgs1 )V1 + [g m1 + G o + s(Cgs1 + Co )]V2

The corresponding Y-parameter matrix is:

b  s(Cgd1 + Cgs1 ) - sCgs1  Y =   - (g m1 + sCgs1 ) g m1 + G o + s(Cgs1 + Co ) b detY = s(Cgd1 + Cgs1 )[g m1 + G o + s(Cgs1 + Co )] - sCgs1 (g m1 + sCgs1 )

= sCgd1[g m1 + G o + s(Cgs1 + Co )] + sCgs1 (G o + sCo )

The gain of network b , the unloaded last stage, is:

b b b b V2 − y 21 − y 21 g m1 + sCgs1 b A V = b = b b = b = ;YL = 0 V1 y 22 + YL y 22 g m1 + G o + s(Cgs1 + Co )

The input impedance of network b (or the load of network a) is given by:

b b b b y 22 + YL y 22 g m1 + G o + s(Cgs1 + Co ) Zi = b b b = b = detY + y11YL detY sCgd1[g m1 + G o + s(Cgs1 + Co )] + sCgs1 (G o + sCo )

The voltage gain of network a is given by:

a a a V2 − y 21 a 1 A V = a = a a ; YL = b V1 y 22 + YL Zi G + sC = S S sCgd1[g m1 + G o + s(Cgs1 + Co )] + sCgs1 (G o + sCo ) G S + sCS + g m1 + G o + s(Cgs1 + Co ) (G + sC )[g + G + s(C + C )] = S S m1 o gs1 o (G S + sCS )[g m1 + G o + s(Cgs1 + Co )] + sCgd1[g m1 + G o + s(Cgs1 + Co )] + sCgs1 (G o + sCo )

6 The overall gain is given by:

V V b  V b  V a  A = o = 2 =  2  2  = A b A a ; since V b = V a V a  b  a  V V 1 2 VS V1  V1  V1 

 g m1 + sCgs1  =   g m1 + G o + s(Cgs1 + Co )

 (G S + sCS )[g m1 + G o + s(Cgs1 + Co )]    (G S + sCS )[g m1 + G o + s(Cgs1 + Co )] + sCgd1[g m1 + G o + s(Cgs1 + Co )] + sCgs1 (G o + sCo ) (g + sC )(G + sC ) = m1 gs1 S S [G S + s(CS + Cgd1 )][g m1 + G o + s(Cgs1 + Co )] + sCgs1 (G o + sCo )

(g m1 + sCgs1 )(GS + sCS ) = 2 G S (g m1 + G o ) + s[(CS + Cgd1 )(g m1 + G o ) + G S (Cgs1 + Co ) + Cgs1G o ] + s [(CS + Cgd1 )(Cgs1 + Co ) + Cgs1Co ]

The trans-impedance of the overall network is:

Vo Vo A V A Z = = = IS VS (G S + sCS ) (G S + sCS )

g m1 + sCgs1 = 2 G S (g m1 + G o ) + s[(CS + Cgd1 )(g m1 + G o ) + G S (Cgs1 + Co ) + Cgs1G o ] + s [(CS + Cgd1 )(Cgs1 + Co ) + Cgs1Co ]

The DC gain is obtained by setting s=0.

g m1 A Z0 = G S (g m1 + G o )

The transimpedance can be re-written as follows:

C A (1+ s gs1 ) Z0 g A = m1 Z 1+ bs + as 2 (C + C )(g + G ) + G (C + C ) + C G b = S gd1 m1 o S gs1 o gs1 o G S (g m1 + G O ) (C + C )(C + C ) + C C a = S gd1 gs1 o gs1 o G S (g m1 + G O )

If the poles are far apart, their values can be estimated as follows :

1 G S (g m1 + G O ) p1 = − = − b (CS + Cgd1 )(g m1 + G O ) + G S (Cgs1 + CO ) + Cgs1G O

b (CS + Cgd1 )(g m1 + G O ) + G S (Cgs1 + CO ) + Cgs1G O p 2 = − = − a (CS + Cgd1 )(Cgs1 + CO ) + Cgs1CO g z = − m1 Cgs1

The bandwidth and gain bandwidth product are defined by the dominant pole p1. That is,

w BW = p1 w f = BW BW 2π

w GBW = A Z0 w BW w f = GBW GBW 2π

The phase margin PM for non-inverting amplifier is the distance between the phase angle at the unity gain bandwidth frequency with respect to –180. For the source follower transfer function this is calculated as follows:

s A Z0 (1+ ) A (s) = z Z s s (1+ )(1+ ) p1 p 2

jw GBW jw GBW A Z0 (1+ ) A Z0 (1+ ) A (jw ) = z ≈ z ; since w >> p Z GBW jw jw jw jw GBW 1 (1+ GBW )(1+ GBW ) ( GBW )(1+ GBW ) p1 p 2 p1 p 2

jw GBW jw GBW jw GBW ∠A Z (jw GBW ) = ∠A Z0 + ∠(1+ ) − ∠( ) − ∠(1+ ) z p1 p 2

-1  w GBW  -1  w GBW  = 0 + tan   − 90 − tan   = −180 + PM  z   p 2 

-1  w GBW  -1  w GBW  PM = 90 + tan   − tan    z   p 2 

8 3. Source Follower as DC Level Shifter

We assume the source follower is operating at saturation mode. That is the drain current is given by:

2 I DS = (β / 2)(VGS − VT ) ; VDS > (VGS − VT ) where: β = K(W / L)

Therefore, 2I V − V = DS GS T β or 2I V = V + DS GS T β

2I V = V − V = V + DS GS in o T β

If VBS=0, this is not possible for NMOS transistor in Nwell process. 2I V = V − V = V + DS GS in o TO β

This difference between the voltage level of the input and output can be specified by controlling W/L ratio for a given K and IDS.

In Figure 1(b), VBS=-Vo. Hence, 2I V = V − V = V + γ ( φ + V − φ ) + DS GS in o TO o β

Note Vo appears on both sides of the equation, need iteration to determine the solution.

Common Drain Amplifier or Source Follower Experiments

4. Source Follower as DC Level Shifter

Source follower is a voltage follower, its gain is less than 1. The DC transfer characteristic has a slope of less than 1. First let us determine the maximum output voltage. For source follower this occurs when the input voltage Vin is at maximum or equal to VDD.

VO(max) = VDD - VT = VDD -[VT0 + γ ( φ + VO(max) − φ )]

VO(max) = 5 −[1+1( 0.6 + VO(max) − 0.6)]

VO(max) + 0.6 + VO(max) − 3.26 = 0 9 This a non-linear equation, its solution requires iteration. A MATLAB m file is created to solve this problem. A call to MATLAB fzero function is invoke to obtain the solution as shown below:

*MATLAB m file “srcf.m” stored in \MATLAB directory function y=srcf(vo) y=vo+sqrt(0.6+vo)-3.26

*MATLAB “fzero” function invocation vo=fzero(‘srcf’,1) vo=1.7327

Pspice Vo(max)=1.7595

One can estimate the required bias of M1, using the biasing principle. The transistor M2 is a current sink biased to generate 100uA with a fixed gate to source voltage of VGS=VT0+∆V=1+1.5=2.5. That is the output voltage Vo=∆V=1.5. Since M1 and M2 are connected in series, means their current are the same. With both transistor have the same W/L means that the gate to source must be equal to VT+∆V. But VT for transistor M1 is equal to VTN accounting for the non-zero bulk bias.

VBS = −VO = -1.5

VTN = VT0 + γ ( φ − VBS − φ ) = 1+1( 0.6 − (−1.5) − 0.6) = 1.6745

Vbias = VO + VTN + ∆V = 1.5 +1.6745 +1.5 = 4.6745

Due to gradual slope of the voltage DC transfer characteristic, it is difficult to obtain the proper operating point from Pspice simulation. To help on the bias determination the current DC transfer characteristic is also plotted for transistor M1. We know the bias current was designed for 100 uA. From Pspice simulation DC transfer characteristic, the bias voltage is 4.75V at IDSQ=101.205uA. This is very closed to the theorically calculated value.

Pspice netlist at this operating is simulated to obtain the small signal characteristics. The theoretical small signal parameters are determined and compared with Pspice simulation results.

10  W   9.6E - 6  β N = K N   = (40E - 6)  = 87.3E - 6  L  N  (5.4 -1)E - 6 

 β N  2  87.27E - 6  2 I DSQ = I 2 =  (VGSN - VT0 ) =  (2.5 −1) = 98.21uA  2   2  g m1 = g mN = 2β N I DSQ = 2(87.3E - 6)(98.21E - 6) = 130.95umho γ 1 g mb1 = g m1 = (130.95E - 6) = 45.18umho 2 φ − VBS 2 0.6 − (−1.5) 1 1 rds1 = = = .509M λ N I DSQ (.02)(98.21E - 6) 1 g ds1 = = 1.9642E - 6 rds1 1 1 rds2 = = = .509M λP I DSQ (.02)(98.21E - 6) 1 g ds2 = = 1.9642E - 6 rds2 1 1 ZO = = = 5.6K g m1 + g mb1 + g ds1 (130.95 + 45.18 +1.9642)E - 6

Zi = ∞

g m1 130.95E - 6 A V0 = = = 0.73 g m1 + g mb1 + g ds1 + g ds2 (130.95 + 45.18 +1.9642 +1.9642)E - 6

Comparing with Pspice results of:

Zi=1 E+20 =∞ Zo=5.323K AV0=.7315

*PSpice file for NMOS Inverter with PMOS Current Load *Filename="Lab3.cir" VIN 1 0 DC 4.75VOLT AC 1V VDD 3 0 DC 5VOLT VSS 4 0 DC 0VOLT VG2 5 0 DC 2.5VOLT M1 3 1 2 4 MN W=9.6U L=5.4U M2 2 5 4 4 MN W=9.6U L=5.4U

.MODEL MN NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL MP PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 *Analysis .DC VIN 0 5 0.05

11 .TF V(2) VIN .AC DEC 100 1HZ 10GHZ .PROBE .END

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE

( 1) 4.7500 ( 2) 1.5757 ( 3) 5.0000 ( 4) 0.0000

( 5) 2.5000

**** SMALL-SIGNAL CHARACTERISTICS

V(2)/VIN = 7.315E-01

INPUT RESISTANCE AT VIN = 1.000E+20

OUTPUT RESISTANCE AT V(2) = 5.323E+03

5. Current Source Driven Source Follower As Transimpedance Amplifier

The voltage gain transfer function has two-zero at the LHPand two-pole at the LHP. That is phase plot is expected cancel each other. Hence the dynamic range of the phase angle is small, hence large phase margin. The gain plot is below 0 db. That is the determination of fBW and fGBW is not possible. Source follower does not have a voltage gain but has a transimpedance gain or voltage to current gain. The source follower is re-simulated using a current source input. The gain is highly dependent on the input impedance Rs. The biasing current is determined to established the same bias as in the voltage source. That is the bias current and input impedance Rs must be selected to produce a bias of 4.75V. This can be achieved by a current bias of 100uA and Rs of .0475Meg. The Pspice netlist with this bias is shown below:

*PSpice file for NMOS Inverter with PMOS Current Load *Filename="Lab3a.cir" IIN 0 1 DC 100u AC 1 VDD 3 0 DC 5VOLT VSS 4 0 DC 0VOLT VG2 5 0 DC 2.5VOLT RS 1 0 .0475Meg M1 3 1 2 4 MN W=9.6U L=5.4U M2 2 5 4 4 MN W=9.6U L=5.4U

13 .AC DEC 100 1HZ 100THZ .PROBE .END

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE

( 1) 4.7500 ( 2) 1.5757 ( 3) 5.0000 ( 4) 0.0000

( 5) 2.5000

**** SMALL-SIGNAL CHARACTERISTICS

V(2)/IIN = 3.475E+04

INPUT RESISTANCE AT IIN = 4.750E+04

OUTPUT RESISTANCE AT V(2) = 5.323E+03

6. Current Driven Source Follower High Frequency Model Experiments

The parasitic capacitances will be determined to check the theory against Pspice simulation results. These capacitances will be determined at the operating point. The reverse biases are first calculated, using the node voltages at the operating point from Pspice simulation.

For M1, VDB=V(4)-V(3)=0-5=-5 VBS=V(4)-V(2)=0-1.5757

For M2, VDB=V(4)-V(2)=0-1.5757=-1.5757 VBS=0

The MATLAB program is invoked to obtain the parasitic capacitances.

For M1, [CGS,CGD,CBD,CBS]=CAP(9.6,5.4,-5,-1.5757) CGS=23.2704, CGD=3.84, CBD=15.6331, CBS=39.1607

For M2, [CGS,CGD,CBD,CBS]=cap(9.6,5.4,-1.5757,0) CGS=23.2704, CGD=3.84, CBD=25.0807, CBS=61.84

The small signal low frequency gain is

G O = g mb1 + g ds1 + g ds2 = (45.18 +1.9642 +1.9642)E - 6 = 49.1084E - 6

g m1 R Sg m1 (.0475E6)(130.95E - 6) A Z0 = = = = 34.5K or 90.6db G S (g m1 + G O ) (g m1 + G O ) (130.95 + 49.1084)E - 6

Pspice simulation result is Azo =90.818 db.

In this experiment, only Cgs and Cgd will be included in the simulation. Also, Cs=CL=0.

CO = Csb2 + Cdb2 + Cgd2 + CL = Cgd2 = 3.84fF

(CS + Cgd1 )(g m1 + G O ) = ((0 + 3.84)E −15)((130.95 + 49.1084)E - 6) = 691.42E - 21

G S (Cgs1 + CO ) = (21.05E - 6)((23.2704 + 3.84)E -15) = 570.67E - 21

Cgs1G O = (23.2704 E -15)(49.1084E - 6) = 1142.77E - 21

G S (g m1 + G O ) p1 = − (CS + Cgd1 )(g m1 + G O ) + G S (Cgs1 + CO ) + Cgs1G O (21.05E - 6)(130.95 + 49.1084)E - 6 = - = 1.576G 691.42E - 21+ 570.67E − 21+1142.77E - 21

(CS + Cgd1 )(g m1 + G O ) + G S (Cgs1 + CO ) + Cgs1G O p 2 = − (CS + Cgd1 )(Cgs1 + CO ) + Cgs1CO 691.42E - 21+ 570.67E − 21+1142.77E - 21 = - (0 + 3.84)(23.2704 + 3.84)E - 30 + (23.2704)(3.84)E - 30 = 12.43E9 g 130.95E - 6 z = − m1 = − = 5.63E9 Cgs1 23.2704E -15 z 5.63E9 f = = = 0.896G Z 2π 2π p 1.576E9 f = 1 = = 250M BW 2π 2π w GBW = A Z0p1 = (34.5E3)(1.576E9) = 54.372E12 = 54.372T w f = GBW = 8.65T GBW 2π

-1  w GBW  −1  w GBW  -1  54.372E12  −1  54.372E12  PM = 90 + tan   − tan   = 90 + tan   − tan    z   p 2   5.63E9   12.43E9  = 90 + 89.994 - 89.987 = 90.007

The Pspice simulation results are: f BW = 268.225M f GBW = 8.25T PM = 90.001