23
Common-Drain Amplifier
■ Similar configuration to common collector.
V+ V+
RS
+ v s − + + + VBIAS V + − OUT V vOUT RL I − BIAS − iSUP SUP
−
V − V−
Analysis: much the same as for CC amplifier -- if VSB isn’t zero, then the voltage gain is degraded from about 1 to 0.8-0.9
EECS 105 Fall 1998 Lecture 23 Common-Drain Two-Port Model
■ Two-Port model:
1 + (gm gmb) + +
+ gm vin + v vout − (gm gmb) in − −
If VSB = 0, then the input resistance is Av = 1 and Rout = 1 / gm (for hand analysis) The CD amplifier is a reasonable voltage buffer, especially for large (W / L) --> large gm.
EECS 105 Fall 1998 Lecture 23 Single-Stage Amplifier Configurations
■ Two complemetary versions exist for each amplifier type.
■ CS/CE, CG/CB, and CD/CC have similar topologies (and properties)
Transistor Type Amplifier Type NMOS PMOS npn pnp + + V + V V + V IN iSUP iSUP IN Common Source/ OUT OUT OUT OUT Common IN IN Emitter i i (CS/CE ) SUP SUP
− − − V V V V − + + + V + V V V i IN SUP iSUP IN Common OUT Gate/ OUT OUT Common OUT Base (CG/CB) i iSUP IN SUP IN − V V − V − V − + + V V + V + V IN iSUP IN iSUP Common OUT OUT Drain/ OUT Common OUT IN IN Collector iSUP (CD/CC ) iSUP − − V − V − V V
EECS 105 Fall 1998 Lecture 23 Two-Port Parameters for Single-Stage Amplifiers
Input Resistance Output Resistance Amplifier Type Controlled Source Rin Rout
Common Gm = gm rπ ro || roc Emitter
Common Gm = gm / (1+gmRE) rπ ( 1 + gm RE) roc || [(1 + gmRE)ro] Emitter +RE for rπ >> RE, RS
Common Gm = gm infinity ro || roc Source
Common Ai = -1 1 / gm roc || [(1 + gm(rπ||RS)) ro], Base for gmRS >> 1
Common 1 / gm, (vsb = 0) roc ||[(1 + gm RS)ro], (vsb=0) Gate Ai = -1 -otherwise- -otherwise- 1 / (gm + gmb) roc || [(1+ (gm + gmb)RS) ro] both for gmRS >> 1 β β Common Av = 1 rπ + ο(ro || roc|| RL)(1 / gm ) + RS / ο Collector
Common Av = 1 if vsb = 0, infinity 1 / gm if vsb = 0, Drain -otherwise- -otherwise- gm / (gm + gmb) 1 / (gm + gmb)
Note: appropriate two-port model is used, depending on controlled source
EECS 105 Fall 1998 Lecture 23 Ultra-Simplified Two-Port Parameters
■ gmb = 0, common base has reasonable source resistance --> RS >> rπ
Amplifier Type Controlled Source Input Resistance Ri Output Resistance Ro
Common Gm = gm rπ ro || roc Emitter
Common Gm = gm infinity ro || roc Source β Common Ai = -1 1 / gm roc || ( ro) Base
Common Ai = -1 1 / gm roc ||[(1+gm RS) ro] Gate β β Common Av = 1 rπ + (ro || roc|| RL)(1 / gm ) + RS / Collector
Common Av = 1 infinity 1 / gm Drain
■ this table is adequate for first-cut hand design
EECS 105 Fall 1998 Lecture 23 Multistage Amplifiers
■ Single-stage transistor amplifiers are inadequate for meeting most design requirements for any of the four amplifier types (voltage, current, transconductance, and transresistance.) ■ Therefore, we use more than one amplifying stage. The challenge is to gain insight into when to use which of the 12 single stages that are available in a modern BiCMOS process: Bipolar Junction Transistor: CE, CB, CC -- in npn and pnp* versions MOSFET: CS, CG, CD -- in n-channel and p-channel versions * in many BiCMOS technologies, only the npn BJT is available ■ How to design multi-stage amplifiers that satisfy the required performance goals?
* Two fundamental requirements:
output resistance of stage n, Rout, n and input resistance of stage n + 1, Rin, (n+1), must be in the proper ratio ∞ Rin, (n+1) / Rout, n --> or Rin, (n+1) / Rout, n --> 0
to avoid degrading the overall gain parameter for the amplifier
2. DC coupling: direct connection between stages --> interaction between biasing sources must be considered (later)
EECS 105 Fall 1998 Lecture 23 Cascaded Voltage Amplifier
■ Want Rin --> infinity, Rout --> 0, with high voltage gain. Try CS as first stage, followed by CS to get more gain ... use 2-port models
RS + + + + v g v r r g v r r v R s − vin1 m1 in1 o1 oc1 vin2 m2 in2 o2 oc2 out L
− − − CS CS
■ solve for overall voltage gain ... higher, but Rout = Rout2 which is too large
EECS 105 Fall 1998 Lecture 23 Three-Stage Voltage Amplifier
■ Fix output resistance problem by adding a common drain stage (voltage buffer)
1 (g + g ) RS (ro2 roc2) m3 mb3 + + + + + + v A v v v R s − vin − v in vin3 − in3 out L
− − − CS − CS CD
■ Output resistance is not that low ... few kΩ for a typical MOSFET and bias --> could pay an area penalty by making (W/L) very large to fix.
EECS 105 Fall 1998 Lecture 23 Transconductance Amplifier
■ input resistance should be high; output resistance should also be high
■ initial idea: use CS stages (they are “natural” transconductance amps)
iout RS + + v −g (r r )g v r r s − vin1 m1 o1 oc1 m2 in1 o2 oc2 RL
−
■ Overall Gm = - gm1 (ro1 || roc1) gm2 = Av1 gm2 ... can be very large ■ Output resistance is only moderately large
EECS 105 Fall 1998 Lecture 23 Improved Transconductance Amplifier
■ Output resistance: boost using CB or CG stage
i i RS in3 out +
+ 1 v v A g v (r r ) −i R s − in v1 m2 in o2 oc2 gm3 in3 L
−
CS − CS CG gm3ro3(ro2 roc2) roc3
■ high-resistance current sources are needed to avoid having roc3 limit the resistance
EECS 105 Fall 1998 Lecture 23 Two-Stage Current Buffers
■ since one CB stage boosted the output resistance substantially, why not add another one ...
iin1 iin2 iout
1 − 1 − is R iin1 β r r iin2 R S gm1 o1 o1 oc1 gm2 L
CB CB
β [ gm2ro2(rπ2 o1ro1 roc1)] roc2
nd ■ The base-emitter resistance of the 2 stage BJT is rπ2 which is much less than the 2nd stage source resistance = 1st stage output resistance
β RS2 ==Rout1 o1ro1 roc1
■ Therefore, the output resistance expression reduces to
≈ β Rout gm2ro2rπ2 roc2 = o2ro2 roc2
... no improvement over a single CB stage
EECS 105 Fall 1998 Lecture 23 Improved Current Buffer: CB/CG
■ The addition of a common-gate stage results in further increases in the output resistance, making the current buffer closer to an ideal current source at the output port
iin1 iin2 iout
1 − 1 − is R iin1 β r r iin2 R S gm1 o1 o1 oc1 gm2 L
CB CG
β [gm2ro2( o1ro1 roc1)] roc2
■ The product of transconductance and output resistance gm2 ro2 can be on the order of 500 - 900 for a MOSFET --> Rout is increased by over two orders of magnitude Of course, the current supply for the CG stage has to have at least the same order of output resistance in order for it not to limit the overall Rout. Practical limit ... on the order of 100 MΩ
EECS 105 Fall 1998 Lecture 23