DOCSLIB.ORG

Lecture 25-1

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Lecture 25-1 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-1 Lecture 25 - Frequency Response of Amplifiers (III) Other Amplifier Stages December 8, 2005 Contents: 1. Frequency response of common-drain amplifier 2. Cascode amplifier Reading assignment: Howe and Sodini, Ch. 9, §9.3.3; Ch. 10, §§10.5, 10.7 Announcement: Final exam: December 19, 1:30-4:30 PM, duPont; open book, calculator required; entire subject under examina- tion but emphasis on lectures #19-26. 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-2 Key questions • Do all amplifier stages suffer from the Miller effect? • Is there something unique about the common drain stage in terms of frequency response? • Can we make a transconductance amplifier with a large bandwidth? 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-3 1. Frequency response of common-drain am- plifier VDD signal source RS signal vs + load iSUP R vOUT L VGG - VSS Features: • voltage gain 1 • high input resistance • low output resistance •⇒good voltage buffer 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-4 High-frequency small-signal model: Cgd G D + vgs Cgs gmvgs gmbvbs ro S - - Cdb RS vbs Csb + vs + - B + r oc RL vout - vbs=0 Cgs + vgs - + RS v + Cgd gmvgs Cdb ro//roc//RL=RL' out vs - - gmRL ≤ Av,LF = 1 1+g mRL 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-5 Compute bandwidth by open-circuit time constant tech- nique: 1. shut-off all independent sources, 2. compute Thevenin resistance RTi seen by each Ci with all other C’s open, 3. compute open-circuit time constant for Ci as τi = RTiCi 4. conservative estimate of bandwidth: 1 ωH Στi 2 First, short vs: Cgs + vgs - + RS Cgd gmvgs Cdb RL' vout - 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-6 2 Time constant associated with Cgs: v i + t • 1 t 2 + + vgs - RS gmvgs RL' vout - node 1: vt + vout it − =0 RS node 2: − − vout gmvgs it =0 RL also vgs = vt Solve for vout in 1 and plug into 2: 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-7 vt RS + RL RTgs = = it 1+g mR L Time constant: RS + RL τgs = Cgs 1+g mR L 2 Time constant associated with Cgd: + vgs - + it + RS vt gmvgs RL' vout - - RTgd = RS τgd = CgdRS 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-8 2 Time constant associated with Cdb: + vgs - it + RS gmvgs RL' vt - it + gm RL' vt - 1 R L RTdb = //RL = gm 1+g mRL RL τdb = Cdb 1+g mRL Notice: RTdb = Rout//RL 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-9 2 Bandwidth: 1 1 ωH = + τ + τ + τ RS RL RL gs gd db Cgs 1+ + CgdRS + Cdb 1+ gmRL gmRL 2 If back is not connected to source: VDD signal source RS VSS signal load vs + iSUP vOUT RL - VGG VSS 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-10 Small-signal equivalent circuit: Cgd G D + vgs Cgs gmvgs gmbvbs ro RS - S - Cdb + + vs vbs Csb roc RL vout - - + B Cgs + - + vgs - RS v v + Cgd gmvgs gmbvbs bs Csb ro//roc//RL=RL' out vs - + - Cgs + + vgs - RS v + Cgd gmvgs Csb RL'//(1/gmb)=RL'' out vs - - gmRL ” Av,LF = 1+g mRL ” 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-11 Csb shows up at same location as Cdb before, then band- width is: 1 ωH RS+RL ” RL ” Cgs + CgdRS + Csb 1+gmRL ” 1+gmRL ” Simplify: • CD amp is about driving low RL from high RS ⇒ RS RL”, and 1 ωH Cgs RL ” RS ( + Cgd)+C sb 1+gmRL ” 1+gmRL ” • CD stage operates as voltage buffer with Av,LF ⇒ 1 gmRL ” 1, and 1 ω H Csb C R + gd S gm Since Cgd and 1/gm are small, if RS is not too high, ωH can be rather high (approach ωT ). 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-12 2 What happened to the Miller effect in CD amp? 1 ωH Cgs RL ” RS ( + Cgd)+C sb 1+gmRL ” 1+gmRL ” Miller analysis of Cgs: g R ” 1 − − m L Cgs = Cgs(1 Av )= Cgs(1 )= Cgs 1+g mRL ” 1+g mRL ” agrees with above result. → → Note, since Av 1, Cgs 0. See in circuit: iin C + + + vin Avvin vout - - - CM = C(1 − Av) if Av 1 ⇒ CM 0: bbootstrappingootstr apping 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-13 2. Cascode amplifier Common-source stage: excellent transconductance am - plifier, but bandwidth hurt by Miller effect. What’s a circuit designer to do? Consider CS-CG stage: VDD VDD iSUP1 iSUP2 signal source iOUT signal load RS vOUT1 VG2 VSS RL vs iOUT1 VG1 IBIAS VSS VSS How does this address the problem? • Rin2 very small ⇒ iOU T 1 can change a lot with vOU T 1 changing little ⇒ small voltage gain in CS stage ⇒ no Miller effect ⇒ high bandwidth • CG stage also has high bandwidth 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-14 Before analyzing CS-CG amp, notice that if we make iSUP1 = iSUP2 = iSUP , amplifier drastically simplified: VDD VDD iSUP iSUP signal source iOUT signal load RS vOUT1 VG2 VSS RL vs iOUT1 VG1 IBIAS VSS VSS VDD iSUP iOUT signal load VG2 VSS RL signal RS source vs VG1 VSS 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-15 VDD iSUP iOUT signal load VG2 VSS RL signal RS source vs VG1 VSS Small-signal equivalent circuit model: (gm2+gmb2)vgs2 RS Cgd1 + + - ro2 vs vgs1 Cgs1 gm1vgs1 Cdb1 ro1 vgs2 Cgs2+Csb2 Cgd2+Cdb2 roc//RL=RL ' - + - Time constants associated with Cgs1 and Cgd2 +Cdb2 have not changed. Time constant associated with Cdb1 + Cgs2 + Csb2 small (looking into Rin2 1/gm). 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-16 Focus on time constant associated with Cgd1: vt + - + it RS vgs1 gm1vgs1 gm2+gmb2 - From Lecture 24: 1 gm1 τgd1 =[ + RS (1 + )]Cgd1 gm2 + gmb2 gm2 + gmb2 If transistors identical (gm1 = gm2): τgd1 2RSCgd1 Much smaller than in single stage CS tansconductance amp: τgd =[Rout + RS (1 + gmRout)]Cgd CascoCascode: de: excellent transconductance amplifier with high bandwidth. 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 25-17 Key conclusions • Common-drain amplifier: – Voltage gain 1, Miller effect nearly completely eliminates impact of Cgs (bootstrapping) – if RS is not too high, CD amp has high bandwidth • Cascode amplifier: – effective sharing of current source – Miller effect minimized by reducing voltage gain of CS stage as a result of low input impedance of CG stage – transconductance amplifier with high bandwidth .
Load more

Recommended publications
  • Common Drain - Wikipedia, the Free Encyclopedia 10-5-17 下午7:07
    Common drain - Wikipedia, the free encyclopedia 10-5-17 下午7:07 Common drain From Wikipedia, the free encyclopedia In electronics, a common-drain amplifier, also known as a source follower, is one of three basic single- stage field effect transistor (FET) amplifier topologies, typically used as a voltage buffer. In this circuit the gate terminal of the transistor serves as the input, the source is the output, and the drain is common to both (input and output), hence its name. The analogous bipolar junction transistor circuit is the common- collector amplifier. In addition, this circuit is used to transform impedances. For example, the Thévenin resistance of a combination of a voltage follower driven by a voltage source with high Thévenin resistance is reduced to only the output resistance of the voltage follower, a small resistance. That resistance reduction makes the combination a more ideal voltage source. Conversely, a voltage follower inserted between a small load resistance and a driving stage presents an infinite load to the driving stage, an advantage in coupling a voltage signal to a small load. Characteristics At low frequencies, the source follower pictured at right has the following small signal characteristics.[1] Voltage gain: Current gain: Input impedance: Basic N-channel JFET source Output impedance: (the parallel notation indicates the impedance follower circuit (neglecting of components A and B that are connected in parallel) biasing details). The variable gm that is not listed in Figure 1 is the transconductance of the device (usually given in units of siemens). References http://en.wikipedia.org/wiki/Common_drain Page 1 of 2 Common drain - Wikipedia, the free encyclopedia 10-5-17 下午7:07 1.
    [Show full text]
  • Cascode Amplifiers by Dennis L. Feucht Two-Transistor Combinations
    Cascode Amplifiers by Dennis L. Feucht Two-transistor combinations, such as the Darlington configuration, provide advantages over single-transistor amplifier stages. Another two-transistor combination in the analog designer's circuit library combines a common-emitter (CE) input configuration with a common-base (CB) output. This article presents the design equations for the basic cascode amplifier and then offers other useful variations. (FETs instead of BJTs can also be used to form cascode amplifiers.) Together, the two transistors overcome some of the performance limitations of either the CE or CB configurations. Basic Cascode Stage The basic cascode amplifier consists of an input common-emitter (CE) configuration driving an output common-base (CB), as shown above. The voltage gain is, by the transresistance method, the ratio of the resistance across which the output voltage is developed by the common input-output loop current over the resistance across which the input voltage generates that current, modified by the α current losses in the transistors: v R A = out = −α ⋅α ⋅ L v 1 2 β + + + vin RB /( 1 1) re1 RE where re1 is Q1 dynamic emitter resistance. This gain is identical for a CE amplifier except for the additional α2 loss of Q2. The advantage of the cascode is that when the output resistance, ro, of Q2 is included, the CB incremental output resistance is higher than for the CE. For a bipolar junction transistor (BJT), this may be insignificant at low frequencies. The CB isolates the collector-base capacitance, Cbc (or Cµ of the hybrid-π BJT model), from the input by returning it to a dynamic ground at VB.
    [Show full text]
  • I. Common Base / Common Gate Amplifiers
    I. Common Base / Common Gate Amplifiers - Current Buffer A. Introduction • A current buffer takes the input current which may have a relatively small Norton resistance and replicates it at the output port, which has a high output resistance • Input signal is applied to the emitter, output is taken from the collector • Current gain is about unity • Input resistance is low • Output resistance is high. V+ V+ i SUP ISUP iOUT IOUT RL R is S IBIAS IBIAS V− V− (a) (b) B. Biasing = /α ≈ • IBIAS ISUP ISUP EECS 6.012 Spring 1998 Lecture 19 II. Small Signal Two Port Parameters A. Common Base Current Gain Ai • Small-signal circuit; apply test current and measure the short circuit output current ib iout + = β v r gmv oib r − o ve roc it • Analysis -- see Chapter 8, pp. 507-509. • Result: –β ---------------o ≅ Ai = β – 1 1 + o • Intuition: iout = ic = (- ie- ib ) = -it - ib and ib is small EECS 6.012 Spring 1998 Lecture 19 B. Common Base Input Resistance Ri • Apply test current, with load resistor RL present at the output + v r gmv r − o roc RL + vt i − t • See pages 509-510 and note that the transconductance generator dominates which yields 1 Ri = ------ gm µ • A typical transconductance is around 4 mS, with IC = 100 A • Typical input resistance is 250 Ω -- very small, as desired for a current amplifier • Ri can be designed arbitrarily small, at the price of current (power dissipation) EECS 6.012 Spring 1998 Lecture 19 C. Common-Base Output Resistance Ro • Apply test current with source resistance of input current source in place • Note roc as is in parallel with rest of circuit g v m ro + vt it r − oc − v r RS + • Analysis is on pp.
    [Show full text]
  • ECE 255, MOSFET Basic Configurations
    ECE 255, MOSFET Basic Configurations 8 March 2018 In this lecture, we will go back to Section 7.3, and the basic configurations of MOSFET amplifiers will be studied similar to that of BJT. Previously, it has been shown that with the transistor DC biased at the appropriate point (Q point or operating point), linear relations can be derived between the small voltage signal and current signal. We will continue this analysis with MOSFETs, starting with the common-source amplifier. 1 Common-Source (CS) Amplifier The common-source (CS) amplifier for MOSFET is the analogue of the common- emitter amplifier for BJT. Its popularity arises from its high gain, and that by cascading a number of them, larger amplification of the signal can be achieved. 1.1 Chararacteristic Parameters of the CS Amplifier Figure 1(a) shows the small-signal model for the common-source amplifier. Here, RD is considered part of the amplifier and is the resistance that one measures between the drain and the ground. The small-signal model can be replaced by its hybrid-π model as shown in Figure 1(b). Then the current induced in the output port is i = −gmvgs as indicated by the current source. Thus vo = −gmvgsRD (1.1) By inspection, one sees that Rin = 1; vi = vsig; vgs = vi (1.2) Thus the open-circuit voltage gain is vo Avo = = −gmRD (1.3) vi Printed on March 14, 2018 at 10 : 48: W.C. Chew and S.K. Gupta. 1 One can replace a linear circuit driven by a source by its Th´evenin equivalence.
    [Show full text]
  • Cascode Techniques
    Analysis and Design of Analog Integrated Circuits Lecture 8 Cascode Techniques Michael H. Perrott February 15, 2012 Copyright © 2012 by Michael H. Perrott All rights reserved. M.H. Perrott Review of Large Signal Analysis of Current Mirrors Vdd Δ V2 I I 1 2 1 μ W2 2 λ nCox (VGS2-VTH) (1+ 2Vds2) I2 2 L = 2 I 1 W 2 1 μ C 1(V -V ) (1+λ V ) 2 n ox GS1 TH 1 ds1 M L1 2 ΔV M1 Vds2 > Vdsat2 1 V +ΔV V +ΔV Δ Δ Δ Δ Vss=0 TH 1 TH 2 But, VTH+ V1=VTH+ V2 V1 = V2 λ I2 W2 L1 (1+ 2Vds2) I2 = λ I1 W1 L2 (1+ 1Vds1) M2 in Saturation Current Mismatch setting due to Vds based on difference M2 in Triode geometry Note: for accurate ratio, set L1 = L2 Vds2 Vdsat2 M.H. Perrott 2 The Issue of Vds Mismatch in Current Mirrors V λ dd I2 W2 (1+ 2Vds2) = λ I1 W1 (1+ 1Vds1) I1 I2 Current Mismatch setting due to Vds based on difference geometry V V ds1 ds2 Note: we are assuming L = L M1 M2 1 2 . Issue: Current I2 can vary significantly as a function of the drain voltage of M2 - We often want a tightly controlled current set only by I1 and transistor sizes . How do we improve the current mirror matching performance? M.H. Perrott 3 Cascoded Current Source I Rth R ref d3 thd3 Ibias Vbias V M bias 3 M3 M ro1 2 M1 . Offers increased output resistance - Reduces small signal dependence of output current on the output voltage of the current source - From Lecture 6, we derived: .
    [Show full text]
  • CHAPTER 3 Frequency Response of Basic BJT and MOSFET Amplifiers (Review Materials in Appendices III and V)
    CHAPTER 3 Frequency Response of Basic BJT and MOSFET Amplifiers (Review materials in Appendices III and V) In this chapter you will learn about the general form of the frequency domain transfer function of an amplifier. You will learn to analyze the amplifier equivalent circuit and determine the critical frequencies that limit the response at low and high frequencies. You will learn some special techniques to determine these frequencies. BJT and MOSFET amplifiers will be considered. You will also learn the concepts that are pursued to design a wide band width amplifier. Following topics will be considered. Review of Bode plot technique. Ways to write the transfer (i.e., gain) functions to show frequency dependence. Band-width limiting at low frequencies (i.e., DC to fL). Determination of lower band cut-off frequency for a single-stage amplifier – short circuit time constant technique. Band-width limiting at high frequencies for a single-stage amplifier. Determination of upper band cut-off frequency- several alternative techniques. Frequency response of a single device (BJT, MOSFET). Concepts related to wide-band amplifier design – BJT and MOSFET examples. 3.1 A short review on Bode plot technique Example: Produce the Bode plots for the magnitude and phase of the transfer function 10s Ts() , for frequencies between 1 rad/sec to 106 rad/sec. (1ss / 1025 )(1 / 10 ) We first observe that the function has zeros and poles in the numerical sequence 0 (zero), 2 5 2 10 (pole), and 10 (pole). Further at ω=1 rad/sec i.e., lot less than the first pole (at ω=10 rad/sec), Ts() 10 s.
    [Show full text]
  • Optimal High Performance Self Cascode CMOS Current Mirror
    View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Global Journal of Computer Science and Technology (GJCST) Global Journal of Computer Science and Technology Volume 11 Issue 15 Version 1.0 September 2011 Type: Double Blind Peer Reviewed International Research Journal Publisher: Global Journals Inc. (USA) Online ISSN: 0975-4172 & Print ISSN: 0975-4350 Optimal High Performance Self Cascode CMOS Current Mirror By Vivek Pant, Shweta Khurana Kurukshetra University Kurukshetra Abstract - In this paper the current mirror presented, having low voltage and mixed mode structure has been proposed. The performance of self cascade MOSFET current mirror is optimized with high output impedance and can operate at 1 V or below. Simulation results conform to Analog Mentor tools having Design Architect for schematics and Eldonet for SPICE simulation, with input reference current of 20μA. This review paper presents a comparative performance study of self cascode current mirror with other current mirrors. Keywords : current mirrors, cascode current mirror, low voltage analog circuit. GJCST Classification : I.2.9 Optimal High Performance Self Cascode CMOS Current Mirror Strictly as per the compliance and regulations of: © 2011. Vivek Pant, Shweta Khurana.This is a research/review paper, distributed under the terms of the Creative Commons Attribution-Noncommercial 3.0 Unported License http://creativecommons.org/licenses/by-nc/3.0/), permitting all non commercial use, distribution, and reproduction in any medium, provided the original work is properly cited. Optimal High Performance Self Cascode CMOS Current Mirror Vivek Pantα, Shweta KhuranaΩ Abstract - In this paper the current mirror presented, having I = I (W/L) 2 (1+λVds2) (3) out ref low voltage and mixed mode structure has been proposed.
    [Show full text]
  • A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions
    Brigham Young University BYU ScholarsArchive Theses and Dissertations 2012-01-28 A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions Taylor Matt Waddel Brigham Young University - Provo Follow this and additional works at: https://scholarsarchive.byu.edu/etd Part of the Electrical and Computer Engineering Commons BYU ScholarsArchive Citation Waddel, Taylor Matt, "A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions" (2012). Theses and Dissertations. 2934. https://scholarsarchive.byu.edu/etd/2934 This Thesis is brought to you for free and open access by BYU ScholarsArchive. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of BYU ScholarsArchive. For more information, please contact [email protected], [email protected]. A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions Taylor M. Waddel A thesis submitted to the faculty of Brigham Young University in partial fulfillment of the requirements for the degree of Master of Science David J. Comer, Chair Aaron R. Hawkins Richard H. Selfridge Department of Electrical and Computer Engineering Brigham Young University April 2012 Copyright © 2012 Taylor M. Waddel All Rights Reserved ABSTRACT A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions Taylor M. Waddel Department of Electrical and Computer Engineering, BYU Master of Science Composite cascode stages have been used in operational amplifier designs to achieve ultra- high gain at very low power. The flexibility and simplicity of the stage makes it an appealing choice for low power op-amp designs. Op-amp design using the composite cascode stage is often made more difficult through the lack of a design process.
    [Show full text]
  • Lecture 33 Multistage Amplifiers (Cont.)
    Lecture 33 Multistage Amplifiers (Cont.) DC Coupling: General Trends * Goal: want both input and output to be “centered” at halfway between the positive and negative supplies (or ground, for a single supply) -- in order to have maximum possible swing at the input and at the output. Summary of DC shifts through the single stages: BJT Amp. npn version Type CE positive CB positive CC negative* MOS Amp. n-channel p-channel Type version version CS positive negative CG positive negative CD negative* positive* The DC voltage shifts for CC/CD stages are set by the VBE = 0.7 V drop or by the VGS of the transistor and can be specified by the designer. EE 105 Fall 2001 Lecture 33 DC Coupling Example * Common drain - common collector cascade (infinite input resistance, fairly low output resistance, unity voltage gain ... reasonable voltage buffer) For CC stage, the optimum output voltage of 2.5 V (centered between + 5 V and ground for maximum swing) --> VIN2 = DC input of CC amp = 2.5 + 0.7 V = 3.2 V The DC of the n-channel CD amplifier is then: VIN = DC input of CD amp = VIN2 + VGS1 = 3.2 V + 1.5 V = 4.7 V where we have assumed that VGS1 = 1.5 V as a typical gate-source voltage (actual number comes from ISUP1and (W/L)). * too close to the supply voltage -- input DC level should be centered at or near 2.5 V. EE 105 Fall 2001 Lecture 33 DC Biasing Example (Cont.) * Solution: use p-channel CD amplifier since it shifts the DC level in the positive direction from input to output Selection of large (W/L) for the p-channel --> input DC level can be adjusted closer to 2.5 V.
    [Show full text]
  • Common Gate Amplifier
    © 2017 solidThinking, Inc. Proprietary and Confidential. All rights reserved. An Altair Company COMMON GATE AMPLIFIER • ACTIVATE solidThinking © 2017 solidThinking, Inc. Proprietary and Confidential. All rights reserved. An Altair Company Common Gate Amplifier A common-gate amplifier is one of three basic single-stage field-effect transistor (FET) amplifier topologies, typically used as a current buffer or voltage amplifier. In the circuit the source terminal of the transistor serves as the input, the drain is the output and the gate is connected to ground, or common, hence its name. The analogous bipolar junction transistor circuit is the common-base amplifier. Input signal is applied to the source, output is taken from the drain. current gain is about unity, input resistance is low, output resistance is high a CG stage is a current buffer. It takes a current at the input that may have a relatively small Norton equivalent resistance and replicates it at the output port, which is a good current source due to the high output resistance. • ACTIVATE solidThinking © 2017 solidThinking, Inc. Proprietary and Confidential. All rights reserved. An Altair Company Circuit Topology • ACTIVATE solidThinking © 2017 solidThinking, Inc. Proprietary and Confidential. All rights reserved. An Altair Company Waveforms Input Voltage Output Voltage • ACTIVATE solidThinking © 2017 solidThinking, Inc. Proprietary and Confidential. All rights reserved. An Altair Company The common-source and common-drain configurations have extremely high input resistances because the gate is the input terminal. In contrast, the common-gate configuration where the source is the input terminal has a low input resistance. Common gate FET configuration provides a low input impedance while offering a high output impedance.
    [Show full text]
  • The Bipolar Junction Transistor (BJT)
    The Bipolar Junction Transistor (BJT) Introduction he transistor, derived from transfer resistor, is a three terminal device whose resistance between two terminals is controlled by the third. The term bipolar reflects the fact that T there are two types of carriers, holes and electrons which form the currents in the transistor. If only one carrier is employed (electron or hole), it is considered a unipolar device like field effect transistor (FET). The transistor is constructed with three doped semiconductor regions separated by two pn junctions. The three regions are called Emitter (E), Base (B), and Collector (C). Physical representations of the two types of BJTs are shown in Figure (1–1). One type consists of two n -regions separated by a p-region (npn), and the other type consists of two p-regions separated by an n- region (pnp). Figure (1-1) Transistor Basic Structure The outer layers have widths much greater than the sandwiched p– or n–type layer. The doping of the sandwiched layer is also considerably less than that of the outer layers (typically, 10:1 or less). This lower doping level decreases the conductivity of the base (increases the resistance) due to the limited number of “free” carriers. Figure (1-2) shows the schematic symbols for the npn and pnp transistors 1 College of Electronics Engineering - Communication Engineering Dept. Figure (1-2) standard transistor symbol Transistor operation Objective: understanding the basic operation of the transistor and its naming In order for the transistor to operate properly as an amplifier, the two pn junctions must be correctly biased with external voltages.
    [Show full text]
  • Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages
    Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages Outline • Common-drain amplifier • Common-gate amplifier Reading Assignment: Howe and Sodini; Chapter 8, Sections 8.7-8.9 6.012 Spring 2007 1 1. Common-drain amplifier VDD signal source RS signal vs + load iSUP RL vOUT VBIAS - VSS • A voltage buffer takes the input voltage which may have a relatively large Thevenin resistance and replicates the voltage at the output port, which has a low output resistance • Input signal is applied to the gate • Output is taken from the source • To first order, voltage gain ≈ 1 • Input resistance is high • Output resistance is low – Effective voltage buffer stage How does it work? •vgate ↑⇒ iD cannot change ⇒ vsource ↑ – Source follower 6.012 Spring 2007 2 Biasing the Common-drain amplifier VDD signal source RS VSS signal + load vs iSUP RL vOUT VBIAS - VSS • Assume device in saturation; neglect RS and RL; neglect CLM (λ = 0) • Obtain desired output bias voltage – Typically set VOUT to”halfway” between VSS and VDD. • Output voltage maximum VDD-VDSsat • Output voltage minimum set by voltage requirement across ISUP. VBIAS = VGS + VOUT I V = V (V ) + SUP GS Tn SB W µ C 2L n ox 6.012 Spring 2007 3 Small-signal Analysis Unloaded small-signal equivalent circuit model: D G + gmvgs ro S vin + roc vout - - + vgs - + + vin gmvgs ro//roc vout - - vin = vgs + vout vout = gmvgs(ro // roc ) Then: g A m 1 vo = 1 ≈ gm + ro // roc 6.012 Spring 2007 4 Input and Output Resistance Input Impedance : Rin = ∞ Output Impedance: i + v - t + gs + RS vin gmvgs ro//roc vt
    [Show full text]