Dv/dt-control methods for the SiC JFET/ Si MOSFET cascode . Daniel Aggeler, Member, IEEE, Francisco Canales, Member, IEEE, Juergen Biela, Member, IEEE, and Johann W. Kolar, Senior Member, IEEE „This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of ETH Zürich’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promo- tional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to
[email protected]. By choosing to view this document you agree to all provisions of the copyright laws protecting it.” 4074 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013 Dv/Dt-Control Methods for the SiC JFET/Si MOSFET Cascode Daniel Aggeler, Member, IEEE, Francisco Canales, Member, IEEE, Juergen Biela, Member, IEEE, and Johann W. Kolar, Fellow, IEEE Abstract—Switching devices based on SiC offer outstanding per- formance with respect to operating frequency, junction tempera- ture, and conduction losses enabling significant improvement of the performance of converter systems. There, the cascode consist- ing of a MOSFET and a JFET has additionally the advantage of being a normally off device and offering a simple control via the gate of the MOSFET. Without dv/dt-control, however, the tran- sients for hard commutation reach values of up to 45kV/μs, which could lead to electromagnetic interference problems. Especially in drive systems, problems could occur, which are related to earth currents (bearing currents) due to parasitic capacitances.