Trends in Integrated Circuits Technology

Trends in Integrated Circuits Technology

Prof. Krishna Saraswat

Department of Electrical Engineering Stanford University Stanford, CA 94305 [email protected]

araswat tanford University 1 EE311/ Trends

Miniaturization => Market growth

Market Growth

Investment Better Performance/Cost

Technology Scaling

Semiconductors have become increasingly more important part of world economy

Courtesy Prof. Tsu-Jae King (Sources: VLSI Research Inc.; United Nation yearbook; World Bank Database; IMF)

araswat tanford University 2 EE311/ Trends

1 World IC Market by Technology

Ref: Chang and Sze, ULSI Technology, 1996

Silicon CMOS has become the pervasive technology araswat tanford University 3 EE311/ Trends

Moore’s Law

Transistors Per Die 1011 4G 1010 2G 512M 1G 109 Memory 256M 128M Itanium® 8 Microprocessor 64M 10 Pentium® 4 16M ® 107 4M Pentium III 1M Pentium® II 106 Pentium® 256K i486™ 64K 105 i386™ 16K 4K 16K 80286 104 1K 8080 3 8086 10 4004 2 10 IC Performance to Gordon Moore’s Prediction 101

100 ’60 ’65 ’70 ’75 ’80 ’85 ’90 ’95 ’00 ’05 ’10 Source: Intel araswat tanford University 4 EE311/ Trends

2 Feature Size Trend

1

Generation 0.1

LGATE micron

0.01

0.001 1980 1990 2000 2010 2020

Gate length is not true measure of transistor size

araswat tanford University 5 EE311/ Trends

Example: Microprocessor Evolution

Generation: 1.5µ 1.0µ 0.8µ 0.6µ 0.35µ 0.25µ

Intel386™ DX Processor

Intel486™ DX Processor

Pentium® Processor

Pentium® II Processor

araswat tanford University 6 EE311/ Trends

3 MOS Device Scaling

Constant E Field Scaling All device parameters are scaled by the same factor α. • Gate oxide thickness tox ↓ • Channel length L ↓ • Source/drain junction depth Xj ↓ • Channel doping ↑ • Supply voltage VD ↓ Why do we scale MOS transistors? 1. Increase device packing density ~ α2 2. Improve frequency response (speed) ~ a 3. Power/ckt: ~1/α2, power density constant

4. Improve current drive (transconductance gm)

"ID gm = "VG VD = const

W K o x # µn VD for VD < VDSAT , linear region L to x W K # µ o x V $ V for V > V , saturation region n ( G T ) D DSAT L to x araswat tanford University 7 EE311/ Trends

Intel’s Transistor Research down to 10nm Electronics is Nanotechnology

DNA is 15 nm wide

30nm 20nm 65nm process 15nm 2005 production 45nm process ! 2007 production 32nm process 10nm 2009 production Source: Intel 22nm process 2011 production

araswat tanford University 8 EE311/ Trends

4 Speed increases as a result of scaling

100

10

Gate Delay 1 (ps)

0.1 Limit 0.01 0.001 0.01 0.1 1 LGATE (um)

Source: Mark Bohr, Intel

araswat tanford University 9 EE311/ Trends

Physical Limits in Scaling Si MOSFET

Gate stack • Tunneling current ⇒ Increased Ioff • Gate depletion ⇒ Increased EOT Source/Drain • Contact resistance High E-Field • Doping level, abruptness Gate • Mobility degradation • Reliability Source Drain

Substrat te e Channel • Surface scattering - the “universal mobility” tyranny • DIBL ⇒ drain to source leakage

• Subthreshold slope limited to 60mV/decade (kT/q) ⇒ Increased Ioff • VG - VT decrease ⇒ reduced ION

Net result: Bulk-Si CMOS device performance increase commensurate with size scaling is unlikely beyond the 70 nm node araswat tanford University 10 EE311/ Trends

5 MOSFET Scaling Limit: Leakage Total Leakage Trend Gate Leakage S/D Leakage

Total Power Trends Source: Marcyk, Intel Lo et al.,IEEE EDL, May 1997.

 Ability to control Ioff will limit gate-length scaling – Thermionic emission over barrier – QM tunneling through barrier – Band-to-band tunneling from body to drain  To suppress D/S leakage, need to use: – Higher body doping to reduce DIBL ⇒ lower mobility, higher junction capacitance, increased junction leakage – Thinner gate dielectric to improve gate control ⇒ higher gate leakage – Ultra-shallow S/D junctions to reduce DIBL ⇒ higher R araswat series tanford University 11 EE311/ Trends

MOSFET Scaling Problem: Saturation of IDsat Constant OFF current Limit Relaxed OFF current Limit 5 10 IDsat (A/m)4 (drive current) 800 1.2

µm)

600 mA/ NMOS 0.8 400

200 PMOS 0.25 0.4 Supply Voltage (V)

0.1 0.2 0.3 0.4 0.6 0.8 1.0 Drive Current ( Channel Length (µm) Source: Intel 0 1 log Id 1990 1995 2000 2005 Low Vt • Data from IBM, TI, Intel, AMD, Motorola and High Vt IOFF,low Vt Lucent • Low OFF current desirable

IOFF,high Vt V Changhoon Choi, PhD Thesis, Stanford Univ., 2002 araswat 0 g tanford University 12 EE311/ Trends

6 Effects of Scaling Bulk MOSFET on Mobility

Phonon

µ Coulombic Surface Roughness

Eeff 1 1 1 1 = + + µeff µC µ ph µ sr S. Takagi et al., IEEE TED, 41 (1994) 2357. q E eff = (Ndep + # $ NChannel ) Ndep= depletion charge density "Si NChannel = charge induced in the channel

 Increases in substrate doping ⇒ Ndep ⇑  Gate oxide thickness decrease ⇒ N ⇑ ! Channel  Eeff increases with scaling ⇒ µ ⇓  Reduced gate oxide thickness increases remote charge scattering ⇒ µ ⇓  High k dielectrics have higher coulombic scattering due to surface states and phonon scattering ⇒ µ ⇓ araswat tanford University 13 EE311/ Trends

New Structures and Materials for Nanoscale MOSFETs Top Gate 5 G 3 4 S C D Si Source Drain 2 SiO2 1 Bottom Gate High µ High-K Si channel BULK SOI Double gate

1. Electrostatics - Double Gate - Retain gate control over channel - Minimize OFF-state drain-source leakage 2. Transport - High Mobility Channel - High mobility/injection velocity - High drive current for low intrinsic delay 3. Parasitics - Schottky S/D - Reduced extrinsic resistance 4. Gate leakage - High-K dielectrics - Reduced power consumption 5. Gate depletion - Metal gate araswat tanford University 14 EE311/ Trends

7 Combining New Device Structures with New Materials

We will be here with these innovations

We are here today

• With better injection and transport we may be able to

improve MOSFET ION • With better electrostatics we may be able to minimize Ioff araswat tanford University 15 EE311/ Trends

Nanotechnology Eras 0.1 100 65 nm 45 nm Generation 32 nm LGATE 22 nm 16 nm 11 nm micron 0.01 8 nm 10 nm

Evolutionary Revolutionary CMOS CMOS Exotic

0.001 1 2000 2010 2020 Reasonably Nanotubes Really Familiar Nanowires Different araswat Source: Mark Bohr, Intel tanford University 16 EE311/ Trends

8 Scaling of MOS Gate Dielectric

K I ! g ! D m thickness

(Ref: S. Asai, Microelectronics Engg., Sept. 1996)

Gate SiO2 thickness is approaching < 10 Å to improve device performance • How far can we push MOS gate dielectric thickness? • How will we grow such a thin layer uniformly? • How long will such a thin dielectric live under electrical stress? • How can we improve the endurance of the dielectric? araswat tanford University 17 EE311/ Trends

Problems in Scaling of Gate Oxide

Polysilicon gate electrode

Dopant Leakage current penetration

gate oxide

Reliability due to Defects and charge injection nonuniformity of film Dielectric breakdown Si substrate

•Below 20 Å problems with SiO2 – Gate leakage => circuit instability, power dissipation – Degradation and breakdown – Dopant penetration through gate oxide – Defects

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9 Dielectric Degradation

• Degradation during device operation due to high E field causing current injection • Degradation during fabrication due to charging in plasma processing

Eox e E cathode

oxide N(E)

Anode

What are the mechanisms for damage and breakdown? How can we engineer the gate dielectric to minimize the damage?

araswat tanford University 19 EE311/ Trends

Gate Oxide Scaling Issues: Leakage 1000

) Ion m µ / 10 A µ (

t

n 0.1 e r r Ioff u 0.001 C

Source G. Bersuker, et al. Sematech Igate 0.00001 50 70 100 130 180 Technology Generation (nm)

• Ion is not increasing with scaling • Igate ⇑, power dissipation ⇑ • Circuit instability araswat tanford University 20 EE311/ Trends

10 High-k MOS Gate Dielectrics

Ichannel ∝ charge x source injection velocity ∝ (gate oxide cap x gate overdrive) vinj ∝ Cox (VGS - VT) Esource µinj

Historically Cox has been increased by decreasing gate oxide thickness. It can also be increased by using a higher K dielectric K I "C " Long term D ox thickness

Today Near future 100 Å high K 40 Å K ≈ 20 20! Å SiO2 K ≈ 4 Si3N4 K ≈ 8 Si

Higher thickness -> reduced gate leakage araswat tanford University 21 EE311/ Trends

Capacitance and Leakage for High-k Gate Dielectric Films Grown Using ALCVD

V 0 Germanium 10 Silicon 1m

) )

2 c 2 -2 m ±V/ m 10 SiO

2 c c / AB/ A

A (

F( ( @ V

-4 2.5 nm 1 e

10 +

g B F e a 2 ) V k g

a @ e -6 ALCVD a 10 t L n k ZrO e e 2 r

t

a r

a -8 u

e G 10 C

L 4 nm e t a 10-10 G 0 0.05 0.1 0.15 0.2 1/C' (µm2/fF) ox Equivalent SiO2 Thickness (nm)

Perkins, Saraswat and McIntyre, Chui, Kim, Saraswat and McIntyre, Stanford Univ. 2002 Stanford Univ. 2004

araswat tanford University 22 EE311/ Trends

11 Subthreshold Behavior

OFF V - V DD T ION ID (log scale) Fermi Dirac ON distribution VDD V T !V source S = G !(ln I ) draine D VG ILEAK or 60 mV/decade IOFF

VG • Diffusion of carriers over the barriers to the channel. q#s /kT QI " e • Fermi-dirac distribution of 1 -E/kT !s = f (VG ) = VG carriers: e " • Gate reduces the barrier to q VG /# kT current flow. ID "QI " e 1 q$ N Where " =1+ s a 2C # | % | araswat ox p tanford University 23 EE311/ Trends

Effect of Reducing Channel Length  In devices with long channel lengths, the gate is completely responsible for

depleting the semiconductor (QB). In very short channel devices, part of the depletion is accomplished by the drain and source bias

 Since less gate voltage is required to deplete QB, VT↓ as L↓. Similarly, as VD

↑, more QB is depleted by the drain bias, and hence VT↓. These effects are particularly pronounced in lightly doped substrates. poly gate VT n+ n+

p-substrate junction Drawn Channel Length, L depleted by depletion gate charge poly gate region VT

n+ n+

! p-substrate araswat Supply Voltage, VD ! tanford University 24 EE311/ Trends !

12 Drain-Induced Barrier Lowering (DIBL)

• Exacerbates subthreshold leakage in short-channel devices • Soft punchthrough induced by drain-to-substrate depletion region

• |VT | ↓ as VD ↑ [drain-induced short channel effects (SCE)] • VD ↑  drain-to-substrate depletion region grows with more reverse bias • Lateral electric fields in drain-induced depletion region lowers source-to- channel barrier, allowing more carriers to diffuse from source to channel

VDD

poly gate poly gate n+ n+ n+ n+

p-well p-well

source drain CB reduction of electron barrier height in conduction band (CB) VDD at edge of source araswat tanford University 25 EE311/ Trends

Why do we need to scale junction depth?

Gate

L N+ source Depletion N+ drain region L! rj P-Si

QB depleted QB depleted by source by drain

* $ - QB 2 " W ' rj V = V ! 2 "# ! " 1 ! & 1+ !1) " T FB F C , r L / ox + % j ( .

•Roll-off in threshold voltage as the channel length is reduced

•VT roll-off is reduced as junction depth(rj) is decreased •Sheet resistance increases as junction depth is reduced

L. Yau, Solid-State Electronics, vol. 17, pp. 1059, 1974 araswat tanford University 26 EE311/ Trends

13 Source/Drain Resistance

) s 140 m

y = 0 h NMOS o 120 (

Scaled by ITRS Roadmap e 100 Rov c

SiO Gate n 2 a 80 t

s i Rext Metal s 60

x e Nov(y) R R 40 Rdp Rc R ov s

R ext e dp i 20 R r c e

N (x) S 0 ext 30 nm 50 nm 70 nm 100 nm Physical Gat e Length

Source: Jasonn Woo, UCLA Problem in junction scaling: • Sheet resistance of a junction is a strong function of doping density • Maximum doping density is limited by solid solubility and it does not scale

• Silicidation can minimize the impact of junction sheet resistance (Rs,Rd) • Contact resistance Rc is one of the dominant components for future technology araswat tanford University 27 EE311/ Trends

Contact Resistance

Specific contact resistivity

$ * ' 2" B #sm 2 !c = ! co exp& ) ohm * cm % qh N (

Doping density

PROBLEMS • Contact resistance is a strong function of doping density at the metal/silicon interface

• Solid sulubility of dopants does not scale !

araswat (Ref: S. Swirhun, PhD Thesis, Stanford Univ. 1987) tanford University 28 EE311/ Trends

14 Solutions to Shallow Junction Resistance Problem

Extension implants Elevated source/ drain

Silicidation Schottky Source/Drain araswat tanford University 29 EE311/ Trends

Problems with Poly-Si Gate.

This occurs because of high E - field due to a combination of higher supply voltage and thinner gate oxide.

Poly-Si gate Oxide

Gate depletion tox(electrical)

tox(physical)

Substrate

• Effect of depletion is to increase effective tox and thus reduce Cox • A reduced Cox implies reduction in gm and thus ID(on) • Ionized impurities in the gate electrode cause “remote charge scattering” ⇒ Reduced mobility Need metal gate electrode with proper workfunction araswat tanford University 30 EE311/ Trends

15 Evolution of MOSFET Structures

BULK Ultra-Thin Body Single Gate SOI

Gate Source SOI Drain Si

SiO2 TBOX

Silicon Substrate Advantages of Ultra-Thin Body SOI • Depleted channel ⇒ no conduction path Ultra-Thin Body Double is far from the gate Gate SOI • Short channel effects controlled by geometry Gate 1 Vg • Steeper subthreshold slope • Lower or no channel doping Source SOI Drain Si • Higher mobility • Reduced dopant fluctuation Tox Gate 2 araswat Ref: Philip Wong, IEDM Short Course, 1999 tanford University 31 EE311/ Trends

Non Planar MOSFETs

Vertical FET Double Gate FinFET Tri Gate FET Gate Channel

Source Drain

SiO2

Gate Drain Source

Stanford, AT&T UC Berkeley Intel araswat tanford University 32 EE311/ Trends

16 Transport: Effects of Biaxial Tensile Strain on Si Energy Bands Hoyt, 2002 Strained Si grown on Relaxed Si1-xGex [001] biaxial tension Δ2 Bulk Si Strained Si Δ Δ4 6 Δ E ~ 67 meV/ Conduction Band [010] Ec s Additional splitting: 10% Ge Δ Band repopulation Δ4 2 [100] Single ellipsoid - reduced intervalley ml scattering mt m < m - smaller in-plane effective ! m t l µ = q * t transport mass mc

Valence Band Bulk Si E Strained Si E out-of- HH/LH degeneracy lifted at Γ Γ k in-plane plane Δ E ~ 40 k - reduced interband scattering HH s meV/10% Ge - smaller in-plane transport mass due to band deformation LH Spin-Orbit araswat tanford University 33 EE311/ Trends

Mobility Enhancements in Strained-Si MOSFETs o i n+ poly t NMOS LTO PMOS a gate oxide spacer r Strained Si

n+ n+ t Relaxed Si1-xGex n e Si1-xGex Graded layer m e c Si Substrate n 2.0

r a o

t V = 10 mV h DS c

a n 1.8 300 K F

t e n

e 1.6

m y e

c t

n 1.4

a i Measured, J. Welser, et al., h

n l IEDM 1994.

E 1.2 i y t i

l b i Calculated for strained Si b o 1.0

o MOS inversion layer

M S. Takagi, et al., J. Appl. Phys. 80, 1996. 0.80 0.0 0.10 0.20 0.30 0.40 Substrate Ge fraction, x

Gibbons Group, Stanford Intel araswat tanford University 34 EE311/ Trends

17 Nanowire and Nanotube FETs Ge NW Growth ALD HfO Coated of Ge NW FET Ge 2 Containing Channel metal Vapor dielectric ~20nm semiconductor Au Nanoparticle ~10nm

drain gate source Ge Nanowire Carbob Nanotube MOSFET Carbob Nanotube Growth Gate

HfO2 D S

10 nm SiO2

p++ Si CnHm C H Fe n m Catalyst Support Key Challenge: Controlled growth araswat tanford University 35 EE311/ Trends

Seemingly Useful Devices

Limited Current Drive Limited Fan-Out Cryogenic operation Critical dimension control Challenging fabrication and process integration

B

+ = ~ 2 nm

Spintronics Carbon Need high spin injection Nanotubes and long spin coherence time Limited thermal stability Controlled growth New architectures needed araswat tanford University 36 EE311/ Trends

18 • In general this device scaling methodology does not take into account many other chip performance and reliability issues, e.g., interconnects, contacts, isolation, etc.

• These factors are now becoming an obstacle in the evolution of integrated circuits.

araswat tanford University 37 EE311/ Trends

Device Isolation pitch as a function of minimum dimension 2.5

) 2.0

m 16M

µ

(

h 1.5 64M

c

t

i

p

a

e 1G

r 1.0

A

e

v

i

t

c 0.5 P. Fazan, Micron, IEDM-93

A

0.0 0.0 0.2 0.4 0.6 0.8 1.0 Minimum dimension [µm] With decreasing feature size the requirement on araswat allowed isolation area becomes stringent. tanford University 38 EE311/ Trends

19 Scaling of Device Isolation

Semi-recessed LOCOS Nitride Nitride Pad oxide

Field oxide

After field oxidation LOFullyC recessedOS b aLOCOSsed isolation technologies have serious problems in lNitrideoss of area due to bird’s beak. Pad oxide Shallow trench isolation

After field oxidation P-substrate N-well

Deep trench isolation

Trench isolation can minimize area loss araswat tanford University 39 EE311/ Trends

Scaling of interconnections

New (scaled) Old

• Bigger chip => longer interconnects • Scaling to smaller dimensions => reduced cross section • Larger R, L and C araswat tanford University 40 EE311/ Trends

20 Interconnect Delay Is Increasing scaling

• Chip size is continually increasing due to 101 )

increasing complexity s Longest Interconnect Delay n ( – Increase in R, L and C e 0

m 10 i T

• Device performance is y a l improving but interconnect e 10-1 delay is increasing D Typical Gate Delay -2 • Need better materials 10 60 80 100 120 140 160 180 – Metal with lower resistivity Technology Node (nm) – Dielectrics with lower K – Other solutions, e.g., 3D, araswat optical interconnects tanford University 41 EE311/ Trends

Advances in Backend Technology

1970’s Poly-Si gate Aluminum

1980’s Aluminum alloys Silicide contacts Polycide gates Local planarization

1990’s Layerd aluminum/titanium Salicides CVD tungsten plugs Shallow trench isolation Global planarization araswat tanford University 42 EE311/ Trends

21 Current Interconnect Technologies

Copper 6

Copper 5

Copper 4

Copper 3

Copper 2 Copper 1

Tungsten Local Interconnect

Current Al technology Current Cu technology (Courtesy of Motorola) (Courtesy of IBM) araswat tanford University 43 EE311/ Trends

Why Cu and Low-k Dielectrics?

14 13

12 Al & SiO2 (! = 4) 11 Cu & SiO2 (! = 4) global 10 9 8 7 semiglobal 6 5 4 Al & low-! (! = 2) local 3 2 Cu & lo w- ! ( ! = 2) 1 0.09 0.13 0.18 0.25 0.35 µm 2007 2004 2001 1998 1995 Year Tec hnology Generation Source: Y.Nishi Reduced resistivity and dielectric constant results in reduction in number of metal layers as more wires can by placed in lower levels of metal layers. araswat tanford University 44 EE311/ Trends

22 Cu Resistivity: Effect of Line Width Scaling

• Effect of Cu diffusion Barrier • Barriers have higher resistivity • Barriers can’t be scaled below a minimum thickness

• Effect of Electron Scattering • Reduced mobility as dimensions decrease

• Effect of Higher Frequencies • Carriers confined to outer skin increasing resistivity

Problem is worse than anticipated in the ITRS 1999 roadmap

araswat tanford University 45 EE311/ Trends

Problems in Scaling of Interconnections

AS λ DECREASES Surrounded Interconnect Cu Barrier • Resistivity increases as grain size decreases ρav Layered Interconnect

Al Barrier • Resistivity increases as

main conductor size Al decreases but not the Pure Metal Interconnect surroundingbarrier size Cu Minimum Feature Size (λ)

araswat tanford University 46 EE311/ Trends

23 3-D Integration: Motivation

2D Area = A

Very Long Wire

3D A/2

A/2 2-D System 3-D System Shorter Wire

s t • Integration of heterogeneous technologies c

e

n possible, e.g., memory & logic, optical I/O n (Log-Log Plot)

o

c

r • Reduce Chip footprint

e 2-D IC

t

n

I 3-D IC

• Replace long horizontal wires by short

f

o

vertical wires

r

e b • Interconnect length ⇓ and therefore R, L, C ⇓

m

u

N Wire-length – Power reduction – Delay reduction araswat tanford University 47 EE311/ Trends

3-D Motivation: Integration Density m e

Source: D. Radack, DARPA t

Repeaters or s / Gate optical I/O devices / y n+/p+ n+/p+ 3D batch s

p

y M4 i t n i i h M3 l

c M2 a / 3 M1 n s Memory Gate r m o or T2 i n+/p+ n+/p+ Analog c o t

t M’2 c r s 3-D Packaging i M’1 n e

s Gate Logic u p n+/p+ n+/p+ T1

n F s / a f r r r o T t e

. s P i o s N 2-D Batch n a r T

. o N

12-15 years Time End-of-Moore’s Law! The Best Integrators of Electronic Devices Will Own the Heart of Every System – We have <15 Years to Figure it out

araswat tanford University 48 EE311/ Trends

24 Can Optical Interconnects help?

40Tb/sO Opticaln-Ch I/Oip1024 O px OC-768tical 100Tb/sInterc On-ChiponneBisectioncts BWPMM64 Tiles64b Processor+ 4MB DRAM Chip-to-chip Optical Interconnects

Can potentially address many problems of Cu/low-k wires  On-Chip Links Reduce delay  Clocking and Synchronization Reduce jitter and skew  High Bandwidth off-chip Links araswat  Reduce power tanford University 49 EE311/ Trends

Result: scaling of power components

Chandra, Kapur and Saraswat, IEEE IITC, June 2002

ITRS projections for total power dissipation on chip

• Dynamic Power: CV2f • Leakage power: devices • Short circuit power during switching • Static power, e.g., analog components (sense amps etc.) Power increasingly becoming the performance bottleneck for high-end microprocessors araswat tanford University 50 EE311/ Trends

25 Thermal Behavior in ICs ]

2 T m J t 30 5 h c n 4 1.2 m e

/ a ax r

25 t 4 m s

1 W

a

n 20 3 [ [ W l

o 3

0.8 M C y

C

t 15 /

i o A

m c

s 2 n

i 2 0.6 10 r n / K d t

e c u

c 1

0.4 ] D

5 m c e

l 1 t r i e 2 v e i 0.2 0 0

] i D w t

y 35 50 70 100 130 180 0 0 o

[ 35 50 70 100 130 180 P Technology Node [nm] Technology Node [nm]

• Thermal conductivity of low-k insulators is poor • Thermal impedance increases • Energy dissipated (CV2f) is increasing as performance improves • Average chip temperature is rising

araswat Source: ITRS tanford University 51 EE311/ Trends

The problems Caused by Increased Power RELIABILITY Electromigration induced hillocks and voids Metal Void Dielectric Hillock Metal

Mean time to failure A " E % >100A will flow on these wires MTF = exp$ a ' r m J n # kT & 10°C ⇑ , MTF ⇓ 50% PERFORMANCE ! As T ⇑ R ⇑, RC delay ⇑ 10°C ⇑ , Speed ⇓ 5%

araswat tanford University 52 EE311/ Trends

26 Conclusion: Technology Progression

Bulk CMOS Feature Size FD SOI CMOS 3D ICs Strained Si Wafer bonding Crystallization

Si Nanowires (tensile)

Cu interconnect Si0.8Ge0.2

Si1-xGex Optical interconnect Low-k ILD Si Double-Gate CMOS Metal gate Gate Detectors, lasers, High k gate dielectric Source Drain modulators, waveguides Ge/Si Heterostrcture Single e transistor Ge on Si hetroepitaxy Ge on Insulator Molecular device Nanowire

B Nanotube + = Spin device Time 2 nm araswat tanford University 53 EE311/ Trends

Summary

MOS Transistor in 2010 A Circuit in 2010 A Factory in 2010

Gate oxide thickness < 1nm Approaching $10 billion Channel Length < 2nm 1010 components Junction depth < 1-2nm Integrated digital, analog, sensors Size of an atom ~ 5 Å Questions we are trying to answer • How can we continue the Moore’s law • What will be new materials, devices, circuits, sensors, equipment, simulators, etc. • How will we design them? araswat • How will we manufacture them? tanford University 54 EE311/ Trends

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