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THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING Enabling Systems in your Pocket and Beyond

PARTICIPATING COMPANIES:

• ADVANCED BIONICS • JAWBONE • CORPORATION • KYOCERA CORPORATION • AMKOR TECHNOLOGY • MULTEK CORPORATION • , INC. • SARCINA TECHNOLOGY LLC • ASE (US) INC. • SILICIUM ENERGY • ASE • CATALYST • CACTUS INC. • • , INC. • TECHSEARCH INTERNATIONAL, INC. • GEORGIA INSTITUTE OF TECHNOLOGY • INC. • GLOBALFOUNDRIES INC.

NOVEMBER 10 &11, 2015 BILTMORE HOTEL, SANTA CLARA, CA

Diamond Sponsor Gold Sponsor Gold Sponsor Gold Sponsor Reception Sponsor Association Sponsor

Media Sponsors 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

CONTENTS

AGENDA

SPONSOR AND EXHIBITOR DIRECTORIES

PARTICIPANT BIOGRAPHIES

DAY ONE – NOVEMBER 10TH

SESSION ONE THE GENIUS OF CARS – AND WHY MATTER Session Chair: Joel Camarda, SemiOps

SESSION TWO HIGH SPEED COMPONENTS AND PACKAGING Session Chair: Li Li, , Inc.

KEYNOTE ENABLING A CONNECTED WORLD IN THE AGE OF INTELLIGENCE Joan Vrtis, Ph.D., Multek Corporation

SESSION THREE MEDICAL AND WEARABLES FOR HUMAN HEALTH: CONNECTING THE DOTS FROM SILICON THROUGH PACKAGING Session Chair: Sesh Ramaswami,

SESSION FOUR POWER MANAGEMENT AND ENERGY HARVESTING: OPPOSITE SIDES OF THE SAME Session Chair: Paul Werbaneth, Invetac

DAY TWO – NOVEMBER 11TH

SESSION FIVE MULTI DIE INTEGRATION Session Chair: Ivor Barber, Xilinx Inc.

SESSION SIX ON THE ROAD TO SIP AND MODULES Session Chair: Eelco Bergman, ASE

KEYNOTE ENABLING THE NEXT GENERATION OF SEMICONDUCTOR STARTUPS Tarun Verma, Ph.D., Silicon Catalyst

SESSION SEVEN IC-PACKAGE-SYSTEM CO-DEVELOPMENT IN THE NEW SIP-ERA Session Chair: Jenny Jiang, Altera Corporation

SESSION EIGHT WRAP-UP PANEL DISCUSSION – THE GREAT CONSOLIDATION Session Chair: Paul Werbaneth, Invetac

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING Technology Enabling Systems in your Pocket and Beyond

DAY ONE - NOVEMBER 10TH MORNING AGENDA

7:30 am Registration Opens

8:45 am – 9:00 am Welcome and Introduction

SESSION ONE THE GENIUS OF CARS – AND WHY SEMICONDUCTORS MATTER

9:00 am - 9:30 am System Scaling, A New Fundamental Frontier Technology Professor Rao Tummala, Georgia Institute of Technology

9:30 am - 10:00 am Packaging ICs to Survive The Automotive Environment Prasad Dhond, Amkor Technology

10:00 am - 10:30 am Title TBA Presenter TBA

10:30 am - 11:00 am Morning Break and Exhibits

SESSION TWO HIGH SPEED COMPONENTS AND PACKAGING

11:00 am - 11:30 am High Speed ASIC Packaging Trend: Integration, SKU, and 25G Larry Zu, Ph.D., Sarcina Technology

11:30 am - 12:00 pm Narrowing the Gap Between Packaging and System Ou Li, ASE Group

12:00 pm - 12:30 pm Package Technology and Design Enablement to 56Gbps Transceivers Hong Shi, Ph.D., Xilinx Inc.

12:30 pm - 1:30 pm Lunch and Exhibits

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING Technology Enabling Systems in your Pocket and Beyond

DAY ONE - NOVEMBER 10TH AFTERNOON AGENDA

1:30 pm - 2:00 pm KEYNOTE Enabling a Connected World in the Age of Intelligence Joan Vrtis, Ph.D., Multek Corporation

SESSION THREE MEDICAL AND WEARABLES FOR HUMAN HEALTH: CONNECTING THE DOTS FROM SILICON THROUGH PACKAGING

2:00 pm - 2:30 pm Miniaturization of Cochlear Implants Kurt Koester, Advanced Bionics Medical

2:30 pm - 3:00 pm Design for Miniature Implantable Medical Devices Andy Kelly, Cactus Semiconductor

3:00 pm - 3:30 pm Afternoon Break and Exhibits

SESSION FOUR POWER MANAGEMENT AND ENERGY HARVESTING: OPPOSITE SIDES OF THE SAME COIN BATTERY?

3:30 pm – 4:00 pm Gallium Nitride: A New Multifunctional Sensing Platform Debbie Senesky, Ph.D., Stanford University

4:00 pm – 4:30 pm 22FDX Technology Enables Energy Harvesting Solutions Jamie Schaeffer, Ph.D., GLOBALFOUNDRIES Inc.

4:30 pm – 5:00 pm Energy Harvesting Technology Based on Next-generation Thermoelectric Devices Douglas Tham, Ph.D., Silicium Energy

5:00 pm – 6:30 pm Reception and Exhibits

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING Technology Enabling Systems in your Pocket and Beyond

DAY TWO - NOVEMBER 11TH MORNING AGENDA

7:15 am Registration Opens

8:15 am – 8:30 am Welcome and Introduction

SESSION FIVE MULTI DIE INTEGRATION

8:30 am – 9:00 am Cost Effective Multi Die Integration Solutions for IoT Trevor Yancey, TechSearch International, Inc.

9:00 am – 9:30 am Silicon Interposers for Multi Die Integration Ivor Barber, Xilinx Inc.

9:30 am – 10:00 am Challenges in the Development of Cost Effective Multi Die Integration Solutions Vincent Liao, ASE

10:00 am – 10:30 am Morning Break

SESSION SIX ON THE ROAD TO SIP AND MODULES

10:30 am – 11:00 am SiP and Heterogeneous Integration: An IC Manufacturer’s Perspective Mike DeLaus, Analog Devices, Inc.

11:00 am – 11:30 am Co-Design for High Density SiP Module: OSAT Point of Vie Harrison Chang, Ph.D. , ASE Taiwan

11:30 am – 12:00 pm SiP from a Systems Perspective Ilyas Mohammed, Ph.D., Jawbone

12:00 pm - 1:00 pm Lunch

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING Technology Enabling Systems in your Pocket and Beyond

DAY TWO - NOVEMBER 11TH AFTERNOON AGENDA

1:00 pm – 1:30 pm KEYNOTE Enabling the Next Generation of Semiconductor Startups Tarun Verma, Ph.D., Silicon Catalyst

SESSION SEVEN IC-PACKAGE-SYSTEM CO-DEVELOPMENT IN THE NEW SIP-ERA

1:30 pm – 2:00 pm Product Co-Development in the New SiP Era Hui Lui, Altera Corporation

2:00 pm – 2:30 pm Chip-Package-Board Pathway Design Flows Tom Whipple, Cadence Design Systems, Inc.

2:30 pm – 3:00 pm Advanced Organic Package Including Interposer and Embedded Package Tomoyuki Yamada, Kyocera Corporation

3:00 pm – 3:30 pm Afternoon Break

SESSION EIGHT WRAP-UP PANEL DISCUSSION – THE GREAT CONSOLIDATION

3:30 pm – 4:30 pm Panel Moderator: Paul Werbaneth, Intevac, Inc.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

A SPECIAL THANKS TO OUR EVENT SPONSORS

DIAMOND SPONSOR GOLD SPONSOR GOLD SPONSOR

Kulicke & Soffa Amkor Technology www.kns.com www.amkor.com Kulicke & Soffa is a global leader in the design and manufacture of semiconductor, LED and elec- Amkor Technology, Inc. is one of the world’s larg- tronic assembly equipment. As a pioneer in this ASE Group est providers of advanced semiconductor assem- industry, K&S has provided customers with mar- bly and test services. Founded in 1968, Amkor www.aseglobal.com ket leading packaging solutions for decades. K&S has become a strategic manufacturing partner Alongside a broad portfolio of established comprehensive solutions include ball bonding, for many of the world’s leading semiconductor technologies, ASE is also delivering innovative wedge bonding, wafer level bonding, thermo- companies and electronics OEMs, providing a advanced packaging and System-in-Package compression bonding, flip chip, FOWLP, WLP, SIP, broad array of advanced package design, assem- solutions to meet growth momentum across a PoP and Embedded Die. K&S has also increase bly and test solutions. Amkor’s operational base broad range of end markets. For more about our its participation in the automotive and industrial encompasses more than 5 million square feet of advances in Cu Wire, SiP, WLP, Fan Out, Flip Chip, markets via Advanced SMT. Combined with its manufacturing facilities, product development MEMS & Sensors, and, 2.5D, 3D & TSV technolo- extensive expertise in process technology, K&S is centers, and sales & support offices in Asia, Europe gies, all ultimately geared towards applications well positioned to help customers meet the chal- and the . Amkor offers a suite of to improve lifestyle and efficiency, please visit our lenges of assembling the next-generation semi- services, including electroplated wafer bumping, website. conductor, LED devices and electronic devices. probe, assembly and final test. Amkor is a leader in advanced copper pillar bump and packaging technologies which enables next generation flip chip interconnect.

GOLD SPONSOR RECEPTION SPONSOR ASSOCIATION SPONSOR

Global Semiconductor Alliance SMART Microsystems www.gsaglobal.org www.smartmicrosystems.com The Global Semiconductor Alliance (GSA) is the SMART Microsystems creates turn-key solutions Advanced Component Labs voice of the global with for microelectronic package assembly challenges www.aclusa.com nearly 400 member companies throughout 32 to move your MEMS sensor technology from Advanced Component Labs, Inc. is the USA’s countries and representing over 75% of the indus- development to production. With an engineering try revenues. GSA provides a neutral environ- team experienced in manufacturing and state-of- leading fabricator of “Time Critical” High Density Interconnects. With a sharp focus directed ment for semiconductor executives to meet and the-art facilities, SMART Microsystems accelerates collaborate on ways to improve efficiencies and the transition of your new MEMS sensor product towards the semiconductor packaging and test communities, ACL’s HDI fabrications offer a direct address industry wide topics and concerns. In to the market. Microelectronic package assembly addition to hosting leading events that are tai- is a key part of the manufacturing process for response to the market’s constantly increasing need for shorter lead times and improved device lored specifically to the semiconductor ecosys- MEMS sensor products. Our core capabilities and tem, GSA also offers its members opportunities expertise support development and prototyping, performance. ACL’s current process technologies include 15µm circuit geometries, 20µm dielectric for thought exchange and relationship develop- environmental life testing, and manufacturing of ment with other industry executives through vari- designs provided by our customers. layers, 50µm laser vias, multi layer build ups and a strong comprehension of both high frequency ous forums, leadership groups, and committees, and high speed package requirements. By select- and much more. ing ACL for your program, you are choosing an ITAR registered, US fabricator with an unparal- leled record for quality, on-time delivery perfor- mance and world class capabilities.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA Wear Sense Move it. it. it.

Innovative IC, System-in-Package, and MEMS packaging portfolio for today’s miniaturization, mobility, and IoT needs.

Wire Flip 2.5D WLP Fanout SiP Bond Chip & 3D

Package it. Visit: aseglobal.com Your Microelectronic Package Assembly Solution for MEMS Sensors

SMART Microsystems creates turn-key solutions CAPABILITIES for microelectronic package assembly challenges n Test and Inspection to move your MEMS sensor technology from de- n Dicing velopment to production. With an engineering n Die Attach / Flip Chip team experienced in manufacturing and state-of- n Wire Bonding the-art facilities, SMART Microsystems accelerates n Encapsulation the transition of your new MEMS sensor product n Environmental Life Test to the market. SERVICES Microelectronic package assembly is a key part of the manufacturing process for MEMS sensor n Prototype Development products. Our core capabilities and expertise sup- n Environmental Life Test port development, testing, and manufacturing of n Manufacturing Services designs provided by our customers. For niche ap- plications, our package assembly solutions offer MARKETS more flexibility, faster lead times, and lower cost n Industrial Controls than system on chip approaches. n Medical n Call us today at 877-637-6278 or visit our website Aerospace at www.smartmicrosystems.com for more infor- mation about SMART Microsystems capabilities and services.

www.smartmicrosystems.com Connecting People and Technology

As one of the world’s largest suppliers of outsourced semiconductor packaging design, assembly and test services, Amkor helps make “next generation” products a reality. Our continuous path of innovation, improvement and growth has led us to be a strategic and trusted packaging partner for many of the world’s leading semiconductor companies. As industry moves aggressively toward new and more complex technologies, our unique expertise in high-volume manufacturing techniques and the ability to solve technological challenges are among our greatest strengths. Customers also benefit from our extensive and expanding global footprint, enabling us to easily handle large orders and offer quick turnaround times. Amkor is positioned to deliver end-to-end solutions that meet the requirements for a broad range of product designs today, and in the future.

www.amkor.com 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

THANKS TO OUR MEDIA SPONSORS

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

EXHIBITOR DIRECTORY

Advanced Component Labs ing, probe, assembly and final test. Amkor is bining strengths and resources to become www.aclusa.com a leader in advanced copper pillar bump and more globally competitive. packaging technologies which enables next The FOA-PT (Packaging & Test) is the Advanced Component Labs, Inc. is the USA’s generation flip chip interconnect. recently launched membership for semicon- leading fabricator of “Time Critical” High ductor packaging, test owners and industry Density Interconnects. With a sharp focus AmTECH Microelectronics, Inc. suppliers. FOA-PT has close to two dozen directed towards the semiconductor packag- www.amtechmicro.com member companies. ing and test communities, ACL’s HDI fabrica- tions offer a direct response to the market’s MICROELECTRONICS Manufacturing Services Kulicke & Soffa including Advanced Packaging, Die bond, constantly increasing need for shorter lead www.kns.com times and improved device performance. Wire Bond, and Encapsulation with mixed ACL’s current process technologies include technology and SMT Assembly RoHS solder Kulicke & Soffa is a global leader in the design 15µm circuit geometries, 20µm dielectric lay- on PCB, PCF, Ceramic, Silicon or other type and manufacture of semiconductor, LED and ers, 50µm laser vias, multi layer build ups of substrate materials. We can support high electronic assembly equipment. As a pioneer and a strong comprehension of both high complexity and small miniature assemblies in this industry, K&S has provided custom- frequency and high speed package require- from PROTOTYPE to PRODUCTION. Our facility ers with market leading packaging solutions ments. By selecting ACL for your program, you includes 2,500 square feet Cleanroom ISO 7 for decades. K&S comprehensive solutions are choosing an ITAR registered, US fabricator with Engineering support, new cutting edge include ball bonding, wedge bonding, wafer with an unparalleled record for quality, on- technology and fully automated equipment. level bonding, thermo-compression bonding, time delivery performance and world class We can support fully automated and precision flip chip, FOWLP, WLP, SIP, PoP and Embedded capabilities. Die Bond, Wire Bond (Au ball, Au Wedge, Al Die. K&S has also increase its participation Wedge, and Ribbon), Dam & Fill, Glob Top, UV in the automotive and industrial markets via AIR-VAC Engineering Curable materials and Flip Chip. In addition Advanced SMT. Combined with its extensive www.air-vac-eng.com we have full capabilities for SMT Assembly expertise in process technology, K&S is well down to 0.3mm pitch, 0201, µBGA, QFN and positioned to help customers meet the chal- AIR-VAC Engineering is a manufacturer of WLCSP components on 100-200 µm thick PCF lenges of assembling the next-generation Die Bonding and Micro-Assembly Equipment (Printed Circuit ) and 200-500 µm thick semiconductor, LED devices and electronic for the Semiconductor, Photonic and SMT PCB (Printed Circuit Boards) including XRAY devices. markets. Systems can be table-top designs or and AOI Inspection. Contact AmTECH at (408) full production cells. Features include eutectic 612-8888 or at www.amtechmicro.com. NTK Technologies ovens, wafer ejectors, dispensing and curing, www.ntktech.com feeders, component flippers and tool chang- ASE Group NTK Technologies is a leader in IC Ceramic ers. Applications for die attach, component www.aseglobal.com sorting, rework and repair, gold/tin, lead-free, Packaging. With global service centers, NTK epoxy are some examples. Alongside a broad portfolio of established offers a wide range of packaging materials technologies, ASE is also delivering innovative and design services for Opto, FPGA, CPU, Amkor Technology, Inc. advanced packaging and System-in-Package MPU, MCM, RF, CMOS Image Sensors, Hi-Rel, www.amkor.com solutions to meet growth momentum across Satellite, Automotive, LED, and Medical appli- a broad range of end markets. For more about cations. Optimum package designs for 10G, Amkor Technology, Inc. is one of the world’s our advances in Cu Wire, SiP, WLP, Fan Out, Flip 40G, and 100G. NTK also offers an advanced largest providers of advanced semiconductor Chip, MEMS & Sensors, and, 2.5D, 3D & TSV technologies for probe card substrates includ- assembly and test services. Founded in 1968, technologies, all ultimately geared towards ing ceramic single thin film and Hybrid ceram- Amkor has become a strategic manufactur- applications to improve lifestyle and efficien- ic, copper/polyimide multilayer substrates, ing partner for many of the world’s leading cy, please visit our website. among other materials. semiconductor companies and electronics OEMs, providing a broad array of advanced Fab Owners Association PROMEX package design, assembly and test solutions. www.waferfabs.com www.promex-ind.com Amkor’s operational base encompasses more than 5 million square feet of manufacturing The Fab Owners Association (FOA) is an inter- PROMEX, a division of PROMEX Industries, facilities, product development centers, and , nonprofit, trade association of semi- offers complete turnkey microelectronics sales & support offices in Asia, Europe and conductor & MEMS fab owners and industry assembly, advanced packaging and semi- the United States. Amkor offers a suite of suppliers who meet regularly to discuss and conductor assembly services to the medical, services, including electroplated wafer bump- act on common manufacturing issues, com- biotech, commercial semiconductor and mili-

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

EXHIBITOR DIRECTORY tary markets. Our world class technical staff SHENMAO America, Inc. SMART Microsystems applies process expertise and technical skills www.shenmao.com www.smartmicrosystems.com to our broad process capabilities. Promex is a recognized leader in custom process devel- SHENMAO America, Inc., a subsidiary of SMART Microsystems creates turn-key solu- opment and assembly of complex system- SHENMAO Technology, Inc., the third largest tions for microelectronic package assembly in-package and medical microelectronics, Solder Materials Provider founded in 1973, challenges to move your MEMS sensor tech- including Class III and bioscience microfluid- produces SMT Solder Paste in its San Jose, nology from development to production. ics devices. Turnkey package design services, CA, USA facility, markets Semiconductor With an engineering team experienced in simulation, characterization and test acceler- Packaging Solder Spheres, Wafer Bumping manufacturing and state-of-the-art facilities, ate products to market. Customers are pro- Solder Paste, Dipping Flux, Wave Solder Bar, SMART Microsystems accelerates the transi- vided with immediate volume manufacturing, Solder Wire, Flux and Solder Preforms from 10 tion of your new MEMS sensor product to the or the product development steps of pro- worldwide locations as the strategic manufac- market. Microelectronic package assembly is cess development, prototypes, new product turing partner of leading OSAT’s, the top EMS a key part of the manufacturing process for introduction, scale up and onshore produc- and OEM’s. SHENMAO BGA Solder Spheres MEMS sensor products. Our core capabili- tion. Full turnkey materials and supply chain for PBGA, CBGA, TBGA, CSP and Flip Chip ties and expertise support development and management available. ISO 13485:2003, ISO Assemblies are made by UMT (Ultra Micron prototyping, environmental life testing, and 9001:2008 certified and ITAR registered. Technology) from highly pure metals pro- manufacturing of designs provided by our duced to various exact Alloy compositions customers. Quik-Pak using Piezoelectric Droplet Jet Technology in www.icproto.com high volumes to accurate diameter uniformi- Universal Instruments ty, bright shiny surface finishes and high qual- www.uic.com Quik-Pak, a division of Promex Industries, pro- ity sphericity. SHENMAO MICRO MATERIAL vides IC packaging, assembly, and wafer prep- INSTITUTE 36 applications engineers devel- Universal Instruments’ core products include a comprehensive surface mount platform port aration services in its ISO 9001:2008 registered oped the Bumping Solder Paste Formula with - facility in San Diego, California. Quik-Pak excellent stencil printing transfer rate and the folio; leading-edge advanced semiconductor packaging solutions; a through-hole lineup manufactures overmolded and pre-molded lowest Void to optimize manufacturing pro- that is the industry standard for productivity open cavity QFN packages that provide a cess performance. SHENMAO strives to offer and reliability; flexible automation cells for fast, inexpensive solution for prototype to full the best quality without compromising cost odd-form or light mechanical and back-end production needs. Same-day assembly ser- and time-to-market while providing maxi- assembly; line software to manage manufac vices are provided to shorten time to market. mum value to all customers. - In addition to wire bond assembly for MW/ turing activities; and industry-leading support RF applications, the company assembles flip SHINKO ELECTRIC INDUSTRIES and services worldwide. chips, BGAs, sensors, MEMS, and chip-on- CO., LTD. board and chip-on-flex assemblies. www.shinko.com SEMI SHINKO ELECTRIC INDUSTRIES CO., LTD. is a www.semi.org leading manufacturer of products used in the assembly of IC’s such as; Organic Substrates, SEMI is the global industry association serving Etched and Stamped Leadframes, TO Packages the nano- and micro-electronic manufactur- and Integrated Heatspreaders. SHINKO manu- ing supply chains. Our 1,900 member com- factures a full line of Organic Substrate struc- panies are the engine of the future, enabling tures including coreless options offering smarter, faster and more economical products enhanced electrical performance and pack- that improve our lives. Since 1970, SEMI has age size reduction. SHINKO can also pro- been committed to helping members grow vide subcontract IC assembly services with more profitably, create new markets and meet an emphasis on packaging solutions such as common industry challenges. SEMI maintains PoP, SiP and Camera Modules utilizing our offices in Bangalore, Beijing, Berlin, Brussels, advanced package assembly technologies, Grenoble, Hsinchu, Moscow, San Jose, Seoul, including our molded core embedded pack- Shanghai, , Tokyo, and Washington, age (MCeP™). SHINKO is located in Nagano, D.C. Japan and provides the ultimate in service and solutions for our customers with Sales and Engineering support worldwide.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

BIOGRAPHIES

SYMPOSIUM CO-CHAIRS

Joel Camarda is an industry consultant, concentrating on manufacturing operations management and packaging technology. He is well known in the international packaging community via his work his- tory of 30+ years in the USA and Asia. He has been active in IMAPS and is an advisor for MEPTEC. Joel has held several executive management positions: Sr. Director of Process Manufacturing Technology at Amonix CPV Solar; VP Operations at Sipex/Exar Semiconductor; President of K&S Flip Chip Technology; and Director of Worldwide Assembly-Test Manufacturing and Packaging at . He started his career at National Semiconductor.

Rich Rice currently serves as Senior Vice President of Business Development for ASE (U.S.) Inc., with responsibilities within the North America region, where he leads ASE’s technology promotion on SiP, inclusive of all key semiconductor assembly technologies. Appointed in 2003, Mr. Rice has held positions within ASE to oversee sales and applications engineering support. In his 30 years in the semiconductor industry, he has held various engineering and business development positions at Amkor Technology and National Semiconductor Corporation. Mr. Rice actively serves in advisory roles for the iMAPS Executive Council and Global Business Council, MEPTEC, and the IC packaging advisory board for SEMI. He holds a BS degree in Agricultural Engineering from the University of Illinois.

SESSION CHAIRS

lvor Barber graduated from Napier University in Edinburgh, in 1981 with a Bachelors degree in Technology. He has worked in package assembly and design at National Semiconductor, and VLSI Technology. lvor spent 23 years at LSI Corporation in Milpitas in various Engineering and Management positions in Assembly, Package Characterization and Package Design. lvor is currently Senior Director of Package Technology Development at Xilinx. lvor holds 13 US patents related to package design.

Eelco Bergman is a 30+ year semiconductor industry veteran with extensive sales, marketing and busi- ness development experience. He currently serves as Sr. Director of Sales & Business Development with ASE Group where he is focused specifically on the enablement and growth of SiP opportunities with system OEM customers. Before joining ASE, Eelco was the Director of Product Marketing for Advanced Interconnect with Global Foundries. He has provided strategic sales, marketing and operational consult- ing services to numerous fabless semiconductor companies and also spent 14 years as SVP of Business Development & Marketing with Amkor Technology. Eelco started his career with during their formative years, where he held a variety of engineering management positions. Eelco has a Bachelor’s of Science degree in Aerospace Engineering from the University of Michigan.

Jenny Jiang is a Principal Design Engineer at Altera Corporation where she has worked for 10 years. Her primary focus is on high-speed high-performance Silicon/Package/Board co-design and technol- ogy development. Prior to Altera, she was with Lucent Technologies Inc. in Murray Hill, NJ, and BigBear Networks in Sunnyvale, CA, focusing on package SIPI and electrical design. She has authored and co- authored over 20 refereed journal and conference papers and has over 10 published/pending patents. Her interests involve IC-PKG-system co-design through SIPI optimization; 2.5D stacked die SIP packag- ing technologies, high speed transceiver design, simulation and integration. Jiang received a BS degree in electrical engineering from Nanjing Institute of Technologies (now Southeast University, Nanjing, ), and an MS degree in electrical engineering (RF/microwave design and technologies) from École Polytechnique de Montréal, Canada. (continued)

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Li Li is a Distinguished Engineer at Cisco Systems, Inc. where he leads an initiative on 3D IC integration and advanced packaging development. He has been with Cisco for about 10 years and has 18 years indus- try experience in IC packaging design, technology development and qualification. He was promoted to a Cisco Distinguished Engineer in 2008 for his outstanding contributions in advanced technology and sup- ply chain development. Dr. Li began his career at IBM as an Advisory Engineer. He was part of the team who developed the industry first Flip Chip Plastic Ball Grid Array (FC-BGA) for fast SRAM applications. He led a cross-functional team to develop an optoelectronics package for Philips Electronics’ Liquid Crystal on Silicon (LCOS) devices before joining Cisco System. He received his M.S. and Ph.D. degrees in Mechanical Science and Engineering from the University of Illinois at Urbana-Champaign.

Sesh Ramaswami is Managing Director, Packaging Technologies, Applied Materials Inc. In this capacity, his responsibilities include program definition and execution, defining and driving external collaboration and co-leading internal process integration programs for the TSV initiative. Sesh has over 25 years of semi- conductor industry experience. Over the past 15 years at Applied Materials, he has had varied technical and business experience in product management and product development and advanced materials development. Prior to joining Applied Materials in 1994, Sesh had thin film process development respon- sibilities for seven years at and four years at National Semiconductor. A holder of 35 US patents and several publications, Sesh has undergraduate and graduate degrees in Chemical Engineering from Indian Institute of Technology, Kanpur, and Syracuse University respectively and a MBA from San Jose State University.

Paul Werbaneth is the Global Product Marketing Director at Intevac, Inc. Since entering the semiconduc- tor industry in 1980 he has been a hands-on Process Sustaining Engineer in an wafer fab; a Senior Plasma Etch Process Engineer with Hitachi High Technologies; the Country Manager for Tegal Japan Inc.; the Vice President of Marketing and Applications at Tegal Corporation; a Business Development Manager at EV Group; and an independent consultant and writer. Paul is a member of the SEMI Advanced Semiconductor Manufacturing Conference steering committee, and was the ASMC 2004 Conference Co-Chair. Paul’s writing activities include his frequent contributions on heterogeneous inte- gration and 2.5-D/3-D IC technology and commercialization to the website 3D InCites; his work as a Guest Editor for IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING; the contributed chapter on TSV etching in the book 3D Integration for VLSI Systems; and an extensive number of articles, papers, and blogs regarding the semiconductor capital equipment business. Paul received the B.S. degree in chemical engineering from Cornell University, Ithaca, NY, and recently completed studies in spoken Japanese from the Cornell Summer FALCON Program, and in Marketing Strategy, also through Cornell.

SYMPOSIUM COMMITTEE

William Chen (Bill) is a Fellow of ASE, where he currently holds the position of Senior Technical Advisor at ASE (U.S.) Inc. Prior to joining the ASE Group, Bill was Director of the Institute of Materials Research & Engineering (IMRE), located in the National University of Singapore. Previously, Bill worked for over thirty three years performing various R&D and management positions at IBM Corporation, where he was elected to the IBM Academy of Technology. He is currently the co-chair of the International Technology Roadmap for Semiconductors (ITRS) Assembly and Packaging International Technical Working Group. Bill has been an associate editor of the IEEE/CPMT transactions, and the ASME Journal of Electronic Packaging, and has published extensively in the fields of microelectronics packaging and mechanics of materials. He held the position of President of the IEEE Components, Packaging and Manufacturing Technology Society (CPMT) from 2006-2009. Bill has been elected a Fellow of IEEE and a Fellow of ASME. In 2011, he was awarded the University Medal from Binghamton University. Bill has held adjunct faculty appointments at Cornell University, Binghamton University, University of Washington, and a visiting faculty appointment at University of Science of Technology. He received his B.Sc. at University of London, M.Sc at Brown University and PhD at Cornell University.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Tom Salmon is Vice President, Global Member Services and Standards, SEMI. He has global responsibil- ity for Member Services as well as the SEMI International Standards Program. In this role, he works with SEMI global staff to ensure delivery of value to SEMI members, as well as standards users and volunteers. In addition, Salmon also manages a number of business and technology programs, including device manufacturer outreach, the Chemical & Gas Manufacturers Group (CGMG), Advanced Packaging and the Secondary Equipment & Applications group. Previously, Salmon held management positions in Standards, Business Development and Customer Outreach at SEMI. Before joining SEMI, he worked in a number of management roles in manufacturing, logistics, customer relations and sales in Japan. He holds a BA in History from the University of Minnesota, as well as a Level 1 Proficiency Certificate from the Ministry of Education in Japan. Salmon is a member of IEEE, the American Society of Association Executives (ASAE) and the USA Cycling Association.

John Yuan Lin Xie, Ph.D. is currently Director of Packaging Technology R&D. He has been with Altera Corporation over 15 years where he leads the Packaging Technology Research and Development team at Altera. His responsibilities include interconnect and packaging technology research and development, new product development and introduction, 2.5D/3DIC integration design and manufacturing enable- ment, strategic supply chain development and strategic customer engagement. Prior to Altera, he was a technology development manager at Prolinx Labs. Corporation (San Jose, CA). Dr. Xie graduated from Department of Physics, Peking University, and holds a Ph.D. Degree in Physics from Institute of Physics, Chinese Academy of Sciences and Post-Doctoral from Department of Physics, University of California at Berkeley and Lawrence Berkeley Laboratory. Dr. Xie has 28 published patents; and over 50 academic and technical publications.

KEYNOTE SPEAKERS

Tarun Verma is a Partner at Silicon Catalyst, where he is an interconnectologist – driving the integration of packaging value proposition onto product portfolio development. He is a semiconductor technical and operations executive with more than 20 years of experience in all aspects of backend semiconductor engineering including supply chain management and fabless semiconductor operations. Previously he was Senior Director of Packaging Engineering at Altera.

Joan K. Vrtis, Ph.D. is the Chief Technology Officer at Multek, subsidiary of Flex, leading sketch to scale solutions company that designs and builds intelligent products for a connected world. Multek is one of the world’s leading printed circuit board suppliers with eight production sites globally and a comprehen- sive product portfolio that extends beyond standard printed circuit boards to high density interconnects, flexible printed circuits, rigid-flex, flexible circuit assemblies, flexible materials and printed electronics. Dr. Vrtis’ core focus is on the advancement of interconnect technologies leveraging printed circuits, printed electronics and advanced assembly technologies enabling the Intelligence of Things (IoT). Throughout her tenure with Multek, she has presented its advanced technology at multiple consortia and technical conferences, expanded its intellectual property portfolio and introduced novel interconnect solutions in the product markets serviced by Multek. Prior to Multek, Dr. Vrtis was Chief Operating Officer of Shocking Technologies, an embedded ESD protection product company, and Chief Operating Officer of Kemeta, LLC, a medical device start-up company that developed biofeedback devices. Between 2004 and 2007, she was a principal owner and Chief Technology Officer of FlipChip International, a leading wafer bump- ing services and advanced packaging provider headquartered in with operations in Phoenix and Shanghai China. Dr. Vrtis started her microelectronics career in the early 1990s at Intel Corporation developing polymer and substrate solutions for the Pentium product line. She has been awarded several patents and holds advanced degrees in polymer engineering (PhD, MS. Univ. of Massachusetts), metal- lurgy (MS, Illinois Institute of Technology), chemistry (BS. Univ of Illinois, Chicago) and a master’s degree in business administration (MBA, DePaul University).

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TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

PRESENTERS

lvor Barber graduated from Napier University in Edinburgh, Scotland in 1981 with a Bachelors degree in Technology. He has worked in package assembly and design at National Semiconductor, Fairchild Semiconductor and VLSI Technology. lvor spent 23 years at LSI Corporation in Milpitas in various Engineering and Management positions in Assembly, Package Characterization and Package Design. lvor is currently Senior Director of Package Technology Development at Xilinx. lvor holds 13 US patents related to package design. Dr. Harrison Chang received his Ph.D. degree from Electrical Engineering Department, University of Maryland College Park, in 1993. He was an Associate Professor in the Huafan University from 1993 to 1996. From 1996 to 1998, he worked at Inc. in San Diego on IS-95 CDMA and CDMA2000 reference design. He worked at Acer Peripheral, which later became Qisda, from 1998 to 2007, as AVP on handset and ODM business. He then founded and became the CEO of Indigo Communications. In 2000, he joined USI, a subsidiary company of ASE Group, and worked on highly integrated, miniaturized module of system in package. He has more than 30 related technical papers and patents.

Mike DeLaus manages the Wafer-Level Package Development Group at ADI. He received his B.S. degree in Materials Science Engineering from MIT in 1982. He joined the Advanced Process Development Group at Analog Devices as a front-end process development engineer in 1988. Since 2005, he has managed ADI’s wafer-level package development activities, responsible for wafer-level and flip chip packaging as well as Through-Silicon Vias (TSVs) and 3D technologies.

Prasad Dhond joined Amkor in 2014 and manages the Quad and Dual Leadframe product lines. Prior to joining Amkor, Prasad worked at for 12 years where he held roles in product definition and marketing in the Analog product group. He holds a BSEE degree from The University of Texas at Austin and an MBA from the Southern Methodist University.

Andrew Kelly is an IC/Systems Architect at Cactus Semiconductor Inc. in Chandler, Arizona. Prior to join- ing Cactus Semiconductor he was a Senior Principal IC Design Engineer at the Medtronic Microelectronics Center in Tempe, Arizona. In his 27 year career, he has defined and designed dozens of Full Custom Mixed- Signal ICs for a wide range of Portable and Implantable Medical Devices such as; Glucose Meters, Hearing Aids, Neuro-Stimulators, Drug Infusion Pumps, Bio Sensors, Orthopedic Sensors, and Cardiac Pacemakers.

Kurt Koester is the Director of Implant Technologies at Advanced Bionics. His team is responsible for identifying, evaluating, and developing technology platforms that enable unique and compelling device designs and features. Research areas include novel materials, hermetic packaging, electrode array design and fabrication methods, and electrochemistry. Prior to joining Advanced Bionics Kurt conducted research on the mechanics of biological tissues and the impact of aging, disease, and drug treatments on these tissues.

Ou Li is Director of Engineering, based within the System Group of ASE (US) Inc. In her current role, Ou is responsible for new product introduction, customer technical support, business engagement, as well as technology development and promotion. Ou has accumulated over eighteen years working experience within the semiconductor industry. Prior to joining ASE, she worked in product engineer- ing and technology development at LSI Logic, AMD and Spansion. Ou received B.S. and M.S. degrees in Electrical Engineering from Xi’an Jiaotong University, China. She also received a M.S. degree in Electrical Engineering from National University of Singapore.

Vincent Liao received his M.S. degree in electrical engineering from the National Chung Hsing University in Taiwan in 2012. For his thesis, he developed and characterized EMI shielding structures with metal coat- ings on plastic encapsulated semiconductor packages. He has more than 10 years’ experience in wireless system in package (SiP) design and product engineering in ASE and holds more than 30 patents.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Hui Liu is a Senior Manager in Design Engineering at Altera Corporation. He is leading a package design team that co-develops high end products with cross-function teams in terms of product definition, silicon and SiP architecting, and cost optimization. Before joining Altera, he was with Cisco System as a system design engineer. Mr. Liu has broad experience in the semiconductor industry and has deep experience in Signal and Power Integrity Analysis, especially in 40G and above applications and optical MCM. He is also interested in R&D for future packaging technologies, such as MCM WLFO, 2.1/2.5D and 3D integration. Mr. Liu holds ten granted patents and gives numerous talks in ECTC, DesignCon, EMC-SIPI, etc. He has a MSEE degree from University of Washington and a Master of Engineering Management degree from University of Ottawa.

Ilyas Mohammed is the Sr. Director of Product Design and Development at Jawbone. He is engaged in wearable products from concept to manufacturing. Previously, he was at Tessera, where he worked on inventing, developing and licensing semiconductor packaging technologies. He obtained his B. Tech. from the Indian Institute of Technology, Madras, India and Ph.D. from The University of Texas at Austin. He has about 100 issued US patents and has authored dozens of publications.

Jamie Schaeffer is currently a Director of Product Line Management at GLOBALFOUNDRIES. Current responsibilities include defining semiconductor technologies, identifying target markets and customers, establishing the product development and manufacturing strategy, and managing program execution to meet the technology and financial objectives of the corporation. Schaeffer joined GLOBALFOUNDRIES in 2009 where he has worked on multiple projects inside the technology development organization. Most notably, Schaeffer helped lead the Front-End-of-the-Line platform development of both the 28nm HKMG and 28nm Poly/SiON technologies including the transfer into volume manufacturing for Fab1 in Dresden, . Prior to joining GLOBALFOUNDRIES, Schaeffer worked as a Member of Technical Staff at and its predecessor, Motorola’s Semiconductor Products Sector since 1997. Schaeffer holds a bachelor’s degree in materials science and engineering from Cornell University and a Ph.D. in materials science and engineering from The University of Texas at Austin.

Debbie G. Senesky received the B.S. degree in mechanical engineering from the University of Southern California in 2001. She received the M.S. and Ph.D. degrees in mechanical engineering from the University of California, Berkeley in 2004 and 2007, respectively. From 2007 to 2008, she was a Design Engineer for GE Sensing (formerly NovaSensor). From 2008 to 2012, she was a research specialist at the Berkeley Sensor and Actuator Center developing silicon carbide (SiC) sensing technology for extreme harsh envi- ronments. In 2012, she was appointed to the faculty in the Aeronautics and Astronautics Department at Stanford University. In recognition of her research, she has received the Early Faculty Career Award from the National Aeronautics and Space Administration.

Hong Shi is director of package design at Xilinx, driving architecture and product development along with design methodology for FPGA packaging platforms supporting ultrahigh speed signaling, IO, AMS, fabric and processors. Prior to Xilinx, he was senior manager of package development at Altera, leading product designs for high-end, mid-range and low-cost FPGA from 65nm to 14nm. Previously, he also worked at Hewlett-Packard microwave division and Agilent lightwave division, developing microwave circuits, optical front-end, and Infinium DCA 40-70GHz sampling module. Hong is recognized by the industry for his pioneering work in 28-Gbps FPGA package, 3D IC packaging, switching noise theory and simulation methodology, power supply noise to jitter transfer theory, lightwave instrumentation, and femtosecond photonics. Hong Shi holds a Ph.D. in Electrical Engineering from the CREOL School of Optics, University of Central Florida; MSc. in Physics from DePaul University; MSEE, BSEE from Xi’an JiaoTong University. He holds 30 patents and has authored over 60 technical articles and one book chapter in ref- ereed journals and conference proceedings. In recent events, he is co-chair of the high performance high density 3D/2.5D package panel at DesignCon 2014. He is the keynote speaker in SEMICON China/CSTIC 2014 Package and Assembly Symposium, and plenary speaker of IoT forum at IEEE EPTC 2014 Singapore.

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TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Douglas Tham began his journey in with double degrees in Materials Science and Chemistry from the University of , where his research focused on tuning the properties of semiconductors such as silicon by altering their nanostructure. He then received a PhD in Chemistry from the California Institute of Technology, where he co-discovered high performance silicon thermoelectrics. With financing from Khosla Ventures, Douglas co-founded Silicium Energy to bring this revolutionary technology to market. He is now living his dream of building a high tech company as CTO at Silicium.

Prof. Rao Tummala is a Distinguished and Endowed Chair Professor at USA. He is well known as an industrial technologist, technology pioneer, and educator. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering such major technologies as the industry’s first plasma display and the first and next three generations of 100 chip multi-chip packaging. He is the father of LTCC and System- On-Package technologies. As an educator, Professor Tummala was instrumental in setting up the largest Academic Center in Electronic Systems at Georgia Tech involving more than 100 Ph.D and MS students, 25 faculty from ECE, ME, MSE and CHE, and 70 companies from the U.S., Europe and Asia, all working together with an integrated approach to research, education and industry.

Tom Whipple graduated with a Bachelor of Science in Electrical and Engineering from Brigham Young University and a Master of Science in ECE from the University of Arizona. He designed PC chip-sets at VLSI Technology Inc. for four years, and has been at Cadence Design Systems for twenty two years. The past eleven years he has worked as a Product Engineering Architect on chip-package-board co-design solutions.

Tomoyuki Yamada received the master degree of material science from Osaka University in Japan in 1997. He joined the IBM Microelectronics division in Japan as technical manager, and in 2003, he joined Kyocera SLC technologies and transferred to Kyocera America in 2007 as Sr. FAE. Currently, he is in charge of promoting new organic substrate technologies as well as PCBs for Kyocera in North America.

Trevor Yancey is senior analyst for TechSearch International. He has more than 25 years experience ana- lyzing and predicting semiconductor market and technology trends. Before joining TechSearch in 2015, he was vice president and co-founder of IC Insights, responsible for the company’s research analysis of chip fabrication and packaging technology advancements. He also developed market forecasts using both supply-side and demand-side research, including analysis of wafer fab capacity levels, R&D spend- ing, IC manufacturing costs, and end-use system requirements. Trevor received his BS degree in Electrical Engineering from Arizona State University. He is a member of IEEE CPMT and SSCS.

Larry Zu is the founder and President of Sarcina Technology LLC. Sarcina provides leading U.S. companies with semiconductor package design, simulation, final test, and one-stop turnkey service. Larry Zu is an industrial veteran who has previously worked at AT&T , DEC, Intel, and TSMC with a proven track record to deliver successful products. At Bell Labs he worked on MCM technology and RF device integra- tion. He was a DEC Alpha package designer. At Intel he was the lead package design engineer for the Itanium 2 microprocessor. He then managed the microprocessor package design team for Pentium 4 at ATD. Afterwards, he managed the 10G optical transponder product engineering group. During his last 2 years at Intel, he focused on RF front-end module design by integrating all active and passive components on Si and laminate substrate. At TSMC he managed the XBOX 360 package design program. Larry received his B.S. in physics from Peking University and his Ph.D. in electrical engineering from Rutgers University. He has multiple IEEE journal papers and US patents.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

SESSION ONE

The Genius of Cars – and Why Semiconductors Matter

Joel Camarda SemiOps

The automobile industry is experiencing rapid change, mostly due to the rate at which technology is changing personal transportation every year. Cars are becoming highly computerized systems, with many automakers now showcasing concept cars sporting very advanced features. Some of these technologies are still far from mainstream but others are quickly finding their place in showrooms as consumer awareness and demand grows. Sophisticated features, such as autonomous vehicle systems, driver override systems, biometric vehicle access systems, and many more, will heavily rely on the semi- conductor industry to help make them reality. This session will explore the automotive semiconductor landscape, delve into emerging application trends, then examine the semiconductor technologies being developed to help bring these to market while meeting increasingly stringent safety, reliability and energy efficiency requirements.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

System Scaling, A New Fundamental Electronics Frontier Technology for , Automotive Electronics and Other Heterogenous Electronics Systems

Prof. Rao R. Tummala Joseph. M. Pettit Chair Professor and Director, 3D Systems Packaging Research Center Georgia Institute of Technology

This presentation will highlight the need for a new fundamental system scaling technology. Semiconductor and systems landscape is changing dramatically. ICs, on one hand, for the most part, are becoming commodities, providing much lower profit margins than ever before, leading to industry consolidation to less than five companies within the next decade, worldwide. In addition, the cost and complexity of scaling is growing exponentially. There is no longer a cost reduction as the next node is introduced with higher transistor density. The driving engines for electronic systems, on the other hand, are also changing dramatically to smart, wearable, wireless healthcare and wireless networks, requir- ing an entirely different vision and strategy than transistor scaling alone that was practiced during the last 60 years. These systems are small to ultra-small systems and yet must perform dozens of functions that include Wireless, Health-Care, Wearable, MEMS and Sensors, Camera, mm-wave, Digital, Photonics, Analog, Power, and many others, all in a thickness of no more than 6000 microns at a cost that every consumer could afford.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Challenges and Solutions in Automotive IC Assembly

Prasad Dhond Senior Director, Quad and Dual Leadframe Products Amkor Technology

Automotive electronic systems represent some of the harshest application conditions for integrated circuits (ICs). The packaging for these ICs must withstand a variety of tests that go well beyond conditions prevalent in consumer, com- mercial and even industrial qualifications. To survive these tests and operate properly over their expected lifetime in a variety of vehicles and systems, assembly processes for automotive ICs have several unique aspects to ensure packaging reliability and durability. This presentation will explain several key factors that must be considered when assembling an automotive IC.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

SESSION TWO

High Speed Components and Packaging

Li Li Distinguished Engineer Cisco Systems, Inc.

This session will cover components, modules and novel packaging technology solutions for high-frequen- cy, high-speed wired and wireless applications, as well as emerging packaging technologies including embedded/integrated chips & passives, sensors, RFID, and RF MEMS. We will also address package design and development for RF, millimeter-wave & THz applications, and wearable, flexible & printed electronics, SiP, heterogeneous integration for communication applications.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

High Speed ASIC Packaging Trend: Integration, SKU, and 25G

Larry Zu, Ph.D. Founder and President Sarcina Technology LLC

Today, high speed ASIC packaging has replaced microprocessor packaging as the driver for high performance semicon- ductor package design, simulation, substrate manufacturing and assembly. In this area, multi-die integration has been used for many years. The concerns about module yield and the technical challenge of warpage-induced PCB assembly yield loss for large packages have been resolved. After the multi-die single package’s wide adoption, the single-die multi- package approach has started to gain traction. Due to increased package cost, demand for small packages that fit into a small network card, high tape out costs for new chips and the time to market requirement, more and more companies today design an ASIC die with multiple packages. This approach offers minimum cost and most importantly, provides the shortest time to market. Finally, package design for 25G+ SerDes has become a popular topic. The wild differential impedance variation caused by BGA ball and other vertical interconnections creates reflection and degrades eye height. Traditional design tricks effective for 10G SerDes no longer work at the data rates for 25G+ SerDes.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Narrowing the Gap Between Packaging and System

Ou Li Director of Engineering, System Group ASE (US) Inc.

With fast growing of today’s electronic world, system integration is realized through multiple aspects. Advanced pack- aging technologies and system in module and package are proliferating. Furthermore, early design stage collaboration among chip, package and system are also critical. Chip-Packaging-System co-design is becoming a more imminent for performance, form factor, cost and time to market. This presentation talks about advanced packaging solutions for system integration, and how Chip-packaging-system co-design is enabling the “Virtual IDM” in electronic ecosystem. The presen- tation will also cover typical co-design tool box, development flow and few case studies. The ultimate goal is to narrowing the gap among chip, packaging and system level through partnership and collaboration.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Package Technology and Design Enablement to 56Gbps Transceivers

Hong Shi, Ph.D. Director, Package Design Xilinx Inc.

The demand to 400G/1TB data path requires ultrahigh speed transceiver operating at 56Gbps for low power and eco- nomical system implementation. While system architects continue debating whether 56G NRZ or 56G PAM-4 should prevail, the package and interconnect designers would need to prepare well for either or both to come into implementa- tion. Because 56G NRZ and 56G PAM-4 carries distinctly unique characteristics, the challenge to package development is different.

This talk will cover recent studies performed in understanding unique requirements from 56G NRZ and PAM-4 to next generation packages. The package development is addressed from both enabling substrate technology and design solu- tion in meeting greater than 30GHz bandwidth and as low as -70dB lane-to-lane cross-coupling. All has to be achieved at same or lower cost than the 28Gbps generation.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

KEYNOTE

Enabling a Connected World in the Age of Intelligence

Joan Vrtis, Ph.D. Chief Technology Officer Multek Corporation

Innovation is accelerating smart, connected devices enabling the Intelligence of Things™. Dr. Vrtis will discuss the systems, packaging and circuit technologies that are converging and enabling opportunities in legacy markets and the creation of new markets such as wearable technologies, connected home, auto and more.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

SESSION THREE

Medical and Wearables for Human Health: Connecting the Dots from Silicon Through Packaging

Sesh Ramaswami Managing Director, Packaging Technologies Applied Materials Inc.

Enhancing human health and quality of life has been and will increasingly become a highly valued societal aspiration. This aspiration will be enabled by technology driven products that drive advances in design, silicon processing, novel materials, imaging, sensing and application specific packaging technologies. This session focuses on the market and application spectrum of this continuum and is designed to cover ideas and products ranging from ingestible capsules, implantable devices, analytical equipment for assays and wearable systems for monitoring or augmenting human body function.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Miniaturization of Cochlear Implants

Kurt Koester Director of Implant Technologies Advanced Bionics

This talk will cover the trend towards the miniaturization of medical devices by reviewing the history and experience in the cochlear implant field and discuss some of the challenges that size reduction imposes on the design of active implant- able devices. To successfully achieve miniaturization targets, it is generally necessary to simultaneously decrease the size of hermetic packaging and the electronics and component payload inside the device. Other aspects of the cochlear implant application, e.g., head-level device placement, designing systems with implantable and body worn components, and covering the pediatric and adult use-cases make device miniaturization desirable. However, these issues drive differ- ent designs considerations, test requirements, device characterization, and longevity expectations relative to other active implantable devices and these issues will also be discussed.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Integrated Circuit Design for Miniature Implantable Medical Devices

Andrew Kelly IC/Systems Architect Cactus Semiconductor Inc.

A new generation of Miniature Implantable Medical Devices (MIMDs) has arrived. Thanks to advances in micro-electro- mechanical systems (MEMS), electronics packaging, and battery technologies, coupled with some creative integrated circuit (IC) design, these new devices are a fraction of the size of traditional Implantable Medical Devices (IMDs). The new MIMDs can be implanted at the point of therapy or sensing, thus eliminating the need for long leads, and enabling minimally invasive surgical procedures. To maximize the benefits of various new technologies, the electronic circuits in MIMDs must be designed specifically to their unique characteristics and requirements. This presentation describes design approaches that help to capitalize on the available opportunities, and enable the dramatic miniaturization required for the new generation of MIMDs.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

SESSION FOUR

Power Management and Energy Harvesting: Opposite sides of the Same Coin Battery?

Paul Werbaneth Global Product Marketing Director Invetac

Fully depleted silicon-on-insulator (FD SOI) technologies are making noise these days in the semicon- ductor industry as a result of their advantages in the faster speed / lower power consumption race. ST Microelectronics, for example, has chosen FD-SOI over FinFETs as a result of FD SOI’s ability to cut gate leakage (and thereby power consumption) to a minimum. And, somewhere in the near future, there will be a convergence of low-power devices and energy harvesters in sensors reporting from potentially anything that moves or vibrates. Are power management and energy harvesting opposite sides of the same coin? Are they pulling on the same oar? Speakers in this session and Energy examine both sides of the coin to understand how the industry will extend itself to the network’s very edge, where the IoT lives, reporting to the cloud.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Gallium Nitride: A New Multifunctional Sensing Platform

Prof. Debbie G. Senesky, Ph.D. EXtreme Environment Microsystems Laboratory (XLab) Stanford University

AlGaN/GaN high electron mobility (HEMTs) are being exploited in the design of high-frequency power elec- tronic devices. The two-dimensional electron gas (2DEG) at the interface of this unique heterostructure can also be leveraged for the development of multifunctional sensing technology as GaN is simultaneously piezoelectric, piezoresis- tive and pyroelectric. It is envisioned that a multitude of devices such as inertial sensors, chemical sensors, bolometers, micromechanical resonators and energy harvesters can be microfabricated in a monolithic fashion with this material platform. However, the technological challenges (e.g., packaging, catalyst integration and temperature compensation) of this aggressive integration approach have yet to be mitigated: leaving room for intense research activities and product development. Also, the temperature-tolerance, radiation-hardness and biocompatibility of this material set can be used to extend the operation regime of micro- and nano-scale devices to extreme harsh environments (e.g., deep space, sub- surface environments, combustion environments, and the human body).

In this talk, a review of the advancements in microfabrication technology for GaN-based devices will be presented. In addition, the compelling results of GaN device operation at temperatures as high as 600˚C and in high-radiation environ- ments will be reviewed. The talk will close a future vision for GaN-based sensors and electronics.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

22FDX Technology Enables Energy Harvesting Solutions

Jamie Schaeffer, Ph.D. FDSOI Product Line Manager GLOBALFOUNDRIES Inc.

22FDX technology is a novel semiconductor technology with features including software controlled body-biasing, ultra- low power operation, and integrated RF that when used in conjunction with energy harvesting can help to reduce service costs and extend the operational life of IoT edge nodes. This talk will review the compute, power, connectivity, storage, and low cost needs of pervasive and intelligent IoT applications. IoT edge nodes that are remotely located or inaccessible will utilize energy harvesting techniques placing further demands on the power management, serviceability, and reli- ability requirements. This talk will discuss how 22FDX is uniquely positioned to address these challenges with the ability to minimize active (0.4v operation) and standby (~1pA/µm) power consumption, provide low-power RF connectivity, and deliver dynamic configurability of the transistor in reaction to the environmental conditions of the energy harvesting system.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Energy Harvesting Technology Based on Next-Generation Thermoelectric Devices

Douglas Tham, Ph.D. Co-Founder & CTO Silicium Energy

Energy harvesting technology based on next-generation thermoelectric devices is now coming to the commercial market, offering unprecedented performance advantages designed to revolutionize wearables and the IoT. The silicon- based thermoelectric devices developed by Silicium leverage heat emanating from the body or from infrastructure to create electrical power, via the thermoelectric effect, to drive wearable devices and industrial sensors. This presentation describes the Silicium technology itself, the story of how it was created at Caltech and at the University of Michigan, and details how Silicium’s silicon-based thermoelectric devices are manufactured, utilizing a “fab-less” approach using off-the- shelf silicon wafers.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

SESSION FIVE

Multi Die Integration

Ivor Barber Senior Director of Package Technology Development Xilinx Inc.

Multi Die Integration is coming of age as a strategy for system integration enabled by a plethora of matur- ing technologies such as POP, chip scale, wafer level packaging, 2.5 & 3D Die stacking, integrated CAD tools and continued substrate innovation.

Motives include performance – putting components in close physical proximity – system miniaturization, and integrating disparate solutions such as non-scaling linear, power or opto components or commodity memory stacks with a microprocessor, ASIC or FPGA in the latest logic node.

As the need for “Fogging” (distributed computing at the edge of the Network) increases, so will the need for Multi Die Integration in relatively low cost environments such as autonomous vehicles, smart homes and medical implants. The session will showcase technologies and highlight challenges in the development of cost effective Multi Die Integration solutions for these emerging applications.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

The Development of Cost Effective Multi Die Integration Solutions for Emerging Connectivity (IoT) Applications

Trevor Yancey Senior Analyst TechSearch International, Inc.

Growing demand for connected devices and systems (commonly referred to as The Internet of Things (IoT) or the Internet of Everything) and the increased deployment of smart devices to collect data, transmit and/or process information is driving new requirements for semiconductor packaging. This translates into an increasing number of MEMS and sensors, processors, and RF devices. This presentation examines trends in multi die integration that are considered cost effective for the growing connectivity requirements. Formats include a variety of packages such as leadframe, laminate substrates, fan-out wafer level packages, and other alternatives. Many of these packages fall into the category of system-in-package (SiP).

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Silicon Interposers for Multi Die Integration

Ivor Barber Senior Director of Package Technology Development Xilinx, Inc.

Motives for adopting silicon interposer technologies include Performance Gain, Miniaturization, Integration of Disparate Silicon Technologies and Cost Reduction.

Xilinx introduced SSIT (Stacked Silicon Interposer Technology) with TSV (Through Silicon Vias) to reduce the cost of cre- ating high end FPGA’s for applications such as next-generation wired communications, high-performance computing, medical image processing, and ASIC prototyping/emulation.

This presentation will show how SSIT reduced high end FPGA product cost and how recent advances are allowing even larger devices to be created. Lastly the presenter will discuss integration and cost reduction strategies to address emerg- ing opportunities in IOT and Edge Computing (distributed computing at the edge of the Network) to facilitate multi die integration in relatively low cost environments such as autonomous vehicles, automated factories and smart homes.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Challenges in the Development of Cost Effective Multi Die Integration Solutions

Vincent Liao Technical Director ASE Group

System-in-Package (SiP) modules play an important role to make portable and wearable devices thinner and smaller, to integrate more functions, and to reduce time to market. For multi-die SiP module designs, package level EMI shielding, Antenna on Package (AoP), Double Sided molding, and embedded die substrates have been proposed and developed by Advanced Semiconductor Engineering (ASE), Inc. to be implemented for complex but cost effective, miniaturized solu- tions. This presentation will discuss the challenges for development and implementation of these technologies in high volume applications.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

SESSION SIX

On the Road to SiP and Modules

Eelco Bergman Sr. Director, Sales & Business Development ASE Group

The IoT era is taking shape with a plethora of products now hitting the market, from wearables to health, automotive to industrial, and many more on the horizon, each with its own unique application space, value proposition and price point. With emphasis on function, performance, efficiency, and fashion, these emerging products are poised to create huge impact across the broad spectrum of global lifestyle. Both electronics and IC Packaging are playing key roles, and the industry is developing technologies to address requirements to enable and optimize the functionality of semiconductor devices. System-in-Package (SiP), modules, and heterogeneous integration technologies continue to play a vital role in bringing products from conception to market.

This session will address the core technologies, ecosystem collaborations, and volume manufacturing requirements for SiP and modules, which form the building blocks for IoT. SiP and modules both call for highly miniaturized device integration that breaks new frontiers in performance and efficiency. We’ll look at the opportunities and challenges. We’ll also discuss the technical innovation in SiP and heterogeneous integration that is helping our industry deliver so global societies can all ultimately realize the IoT era.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

SiP and Heterogeneous Integration: An IC Manufacturer’s Perspective

Mike DeLaus Manager, Wafer-Level Package Development Group Analog Devices, Inc.

The Internet of Things (IoT) era is driving profound changes in the semiconductor industry. IC manufactures, like Analog Devices, have had to adapt to these changes both in terms of the products they offer and the technologies that they employ. The increased emphasis on integration coupled with the limitations of device scaling are driving the need for packaging solutions like System in Package (SiP) and innovative heterogeneous integration schemes. This presentation will discuss how Analog Devices is meeting these challenges and providing their customers with more integrated solu- tions. The product development process will be described and the increased importance of collaboration, simulation and enhanced testing will be highlighted. Examples of ADI’s next generation devices, which seek to grab more of the signal chain, will be discussed.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Co-Design for High Density SiP Module: OSAT Point of View

Harrison Chang, Ph.D. VP Miniaturized Product Corp R&D ASE Tiawan

New generation of consumer electronics for smartphone and beyond smartphone (i.e. IoT, Wearable, and 5G) calls for high density integration of heterogeneous SiP module. For high density SiP Module, the component counts could be in the ranges of hundreds, and is being delivered in the semi-conductor industry. This new level of integration requires closer working relationship between IC House and OSAT than the industry is usually practicing. Among them, design for miniaturized manufacturing, leveled test development approaches, and structured failure analysis are crucial for the high density SiP Module projects to achieve low cost and time to market. In this presentation, several generations of manu- facturing processes and structures of such high density, heterogeneous SiP Module are introduced, and the new working relationship will be illustrated.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

SiP from a Systems Perspective

Ilyas Mohammed, Ph.D. Sr. Director, Product Design and Development Jawbone

Abstract not available at time of printing.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

KEYNOTE

Enabling the Next Generation of Semiconductor Startups

Tarun Verma, Ph.D. Partner Silicon Catalyst

This is one of the most exciting times to be innovating with semiconductors. Mega-trend opportunities in IoT, biotech, wearables, energy, transportation, and mobile will all have new semiconductor innovation at their core. These mar- kets enable novel and valuable products that do not require leading-edge technologies and enormous R&D budgets. However, many of these startups require innovative packaging solutions both from a product design and technology perspective to meet cost performance and form factor requirements. This presentation will provide real examples and insights into such innovations.

These new semiconductor start-ups face challenges including fierce competition for funding, expensive design costs, and complex processes for bringing new designs to market. Reducing upfront costs creates start-ups that become much bet- ter investments and follow-on funding can go to true innovation and value creation. Developing an ecosystem of leading companies and experienced individuals that offer needed capabilities under a framework that recognizes the challenges of this space is an approach that is gaining traction. Startups in this space need an ecosystem of silicon experts encom- passing tools, testing, packaging, production, and financing to make this happen.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

SESSION SEVEN

IC-Package-System Co-Development in the New SIP Era

Jenny Jiang Principal Design Engineer Altera Corporation

With silicon scaling running into increased road blocks, the SoC preference has gradually been mov- ing towards SIP to integrate the needed feature and IP within the time and cost budget. This eventually becomes a sub-system level product instead of traditional simple SoC as simple component. It requires more complete and holistic planning and consideration of IC-PKG co-design and extended into system level design as well. This also calls for advancing the IC-PKG-System co-design to co-development and to co-architecting. This is an exciting new trend in microelectronic design field as well as new opportunities for designers of all disciplines, fabless companies, EDA tool vendors and system houses.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Product Co-Development in the New SiP Era

Hui Liu Senior Manager, Design Engineering Altera Corporation

As silicon node scaling faces more and bigger challenges, such as power and SI/PI issues, reliability and yield issues, cost and IP integration issues, SiP solution becomes more and more attractive over single chip SoC. At the same time, SiP solu- tion faces new challenges as well due to design and manufacturing complexity. To address these challenges effectively, this presentation introduces a new front-end co-development concept vs. the traditional backend co-design approach.

This presentation focuses on component level SiP solution co-development by IC and Packaging Engineering and Marketing. Specifically the presentation will cover:

• A multi-dimensional view (IC integration, packaging integration, co-development, and application) of the IC industry evolution • SiP challenges in the new era • Front-end co-development vs. backend co-design • Front-end co-development attributes and methodology flow

The presentation will also give two specific cases showing how co-development/co-architecting in SiP impacts product definition, helps reducing silicon and package cost, and enhances features and performance.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Chip-Package-Board Pathway Design Flows

Tom Whipple Product Engineering Architect Cadence Design Systems, Inc.

Today’s IC design process can no longer be done in a vacuum ignoring the realities of the package and PCB implementa- tion. Package ball maps are typically created in a spreadsheet and PCB and IC pinout and component breakout are done without a view for how the pieces will fit together. The parts are brought together in a BGA and an attempt to resolve the many net crossings is made in the package layout tool. This is a tedious and error-prone process for even a single die package. This problem is exacerbated by shrinking feature size and increasingly difficult design, timing and power constraints that significantly reduce design margins. System on Chip designs are yielding to System in Package designs due to difficulties in scaling to advanced technology nodes. Designers require a hierarchical environment that enables a system-level exploration of topological solutions of the components in the design followed by pathway exploration. This should include the component routing breakouts on all substrates, and the optimal pin assignment to package, inter- poser and die components in the context of the whole system. Results from the pathway exploration must drive directly into physical implementation tools for physical layout and analysis.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

Organic Interposer Technology and Embedded Passive/Active PCB

Tomoyuki Yamada Sr. Field Applications Engineer, Organic Products Kyocera America

This presentation consists of the development of a low CTE organic package for 2.5D interposer and the embedded passive/active PCB technologies. The new material set, identified as advanced organic package, combines low CTE core and build-up Dielectric materials to achieve a composite laminate CTE of 9-12 ppm / ˚C, which is positioned in between the device silicon and conventional board CTE. The technology roadmap of organic interposer technology including fine pitch flip chip, line and space etc. will be discussed. On embedded active/passive package, technical capabilities and challenges are discussed.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA 2015 MEPTEC/SEMI SYMPOSIUM - THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING

SESSION EIGHT

Wrap-Up Panel Discussion: The Great Consolidation

Paul Werbaneth Global Product Marketing Director Invetac

The big story of 2015, one that gained strength and momentum as the year progressed, is consolidation. Be it on the device maker-side, the OSAT-side, the capital equipment supplier-side, or the end customer-side, consolidation has its benefits, primarily in achieving ever greater business efficiencies, but consolidation also has its costs, hidden or otherwise. The panelists will discuss, with active audience participation, the merits and drawbacks of the consolidation spree as they see it, and will consider how con- solidation will affect our industry’s ability to embrace the challenges presented by the new era of mobile miniaturization.

TUESDAY, NOVEMBER 10 & WEDNESDAY, NOVEMBER 11, 2015 • SANTA CLARA, CALIFORNIA About MEPTEC

MEPTEC is a trade association of semiconductor companies and professionals involved in the manufacturing, packaging, assembling and testing of integrated circuits. Since its inception over 30 years ago, MEPTEC has provided a forum for the semiconductor industry to learn and exchange ideas through our monthly luncheons, conferences, and our quarterly publication, the MEPTEC Report. With the support of an Advisory Board consisting of individuals from all segments of the industry, MEPTEC has, over the years, kept current not just with semiconduc- tor industry developments, but has expanded its scope to cover relevant industry segments such as MEMS and medical electronics.

For more information about MEPTEC events and membership please visit www.meptec.org.

About SEMI

SEMI is the global industry association serving the nano- and micro-electronic manufacturing supply chains. Our 1,900 member companies are the engine of the future, enabling smarter, faster and more economical products that improve our lives. Since 1970, SEMI has been com- mitted to helping members grow more profitably, create new markets and meet common industry challenges. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C.

For more information about SEMI events and membership please visit www.semi.org.