The LSI Data Acquisition Peripheral of the Future

Coorganizers: John A. Schoeff - Advanced Micro Devices, Inc., Sunnyvale, CA

James Solomon - National Semiconductor Corp., Santa Clara, CA

Moderator: Ray Stata, Analog Devices, Inc., Norwood, MA

Designers of A/D and D/A converters are beginning to use the same LSI technologies that are available to microprocessor and memory designers, since they offer the potential for large increases in circuit complexity.

In exploring the approaches available for tapping this potential, it is also necessary to consider which tech- nologies are most attractive for data acquisition ICs and what are the analog and digital performance limits of these technologies, and within the expected limits, what types of complex data acquisition ICs would be the most interesting to make.

In considering the initial problem panelists are expected to weigh the MDS advantage of high digital density against the bipolar advantage of analog precision. It is felt by some that switched-capacitor techniques will allow MOS to equal the analog accuracy of bipolar.

For severalyears, wafer level trim (WLT) techniques havebeen pushed as the answer to the monolithic accuracy problem. Progress to dateon WLTwill be reviewed and compared with competing non-trim approaches.

Thus, in addressing the fabrication aspect, the panel will review the variety of data acquisition subsystems presently being built at the PC-board level, such as the traditional A/D, reference, mux, S/H amplifier and bus interface. The feasibility, desirability and economics of including multiple designs in a single LSI circuit will be considered.

An attempt will also be made to explore new avenues for data acquisition LSI. For example, the usefulness of the smart A/D or A/D plus a simple microprocessor will be considered. This IC could be configured to per- form a variety of tasks, including: (1) - digitally-based auto-zeroing and correction of long and short term drift in the analog front end; (2) - digital PROM correction for analog nonlinearities such as thermocouple characteristics; (3) - digital preconditioning of the analogsignal by predetermined techniques as directed by a configuration word from the main CPU, and (4) - configuration via on-chip ROM to provide standard RS-232C 1/0 protocol or any other serial format for remote operation from the CPU.

Panel Members

D. Bailey, Hewlett-Packard Data Systems Division, Cupertino, CA P. Holloway, Analog Devices, Inc., Wilmington, MA B. Conant, Burr-Brown Research Corp., Tucson, AZ J. A. Schoeff, Advanced Micro Devices, Inc., Sunnyvale, CA B. M. Gordon, Analogic Corp., Wakefield, MA J. E. Solomon, National Semiconductor Corp., Santa Clara, CA P. Sylvan, Teradyne, Inc., Boston, MA