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CIS 501 Computer Architecture This Unit Readings Review

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CIS 501 Computer Architecture This Unit Readings Review This Unit • Technology basis • Transistors & wires • Cost & fabrication CIS 501 • Implications of transistor scaling (Moore’s Law) Computer Architecture Unit 3: Technology Slides originally developed by Amir Roth with contributions by Milo Martin at University of Pennsylvania with sources that included University of Wisconsin slides by Mark Hill, Guri Sohi, Jim Smith, and David Wood. CIS 501 (Martin/Roth): Technology 1 CIS 501 (Martin/Roth): Technology 2 Readings Review: Simple Datapath • Chapter 1.1 of MA:FSPTCM + 4 • Paper Register • G. Moore, “Cramming More Components onto Integrated Circuits” Data Insn File PC s1 s2 d Mem Mem • How are instruction executed? • Fetch instruction (Program counter into instruction memory) • Read registers • Calculate values (adds, subtracts, address generation, etc.) • Access memory (optional) • Calculate next program counter (PC) • Repeat • Clock period = longest delay through datapath CIS 501 (Martin/Roth): Technology 3 CSE 371 (Roth): Performance 4 Recall: Processor Performance Semiconductor Technology gate gate • Programs consist of simple operations (instructions) insulator • Add two numbers, fetch data value from memory, etc. source drain source drain channel • Program runtime = “seconds per program” = Substrate (instructions/program) * (cycles/instruction) * (seconds/cycle) channel • Basic technology element: MOSFET • Instructions per program: “dynamic instruction count” • Solid-state component acts like electrical switch • Runtime count of instructions executed by the program • MOS: metal-oxide-semiconductor • Determined by program, compiler, instruction set architecture (ISA) • Conductor, insulator, semi-conductor • Cycles per instruction: “CPI” (typical range: 2 to 0.5) • FET: field-effect transistor • On average, how many cycles does an instruction take to execute? • Channel conducts source!drain only when voltage applied to gate • Determined by program, compiler, ISA, micro-architecture • Channel length: characteristic parameter (short ! fast) • Seconds per cycle: clock period, length of each cycle • Aka “feature size” or “technology” • Inverse metric: cycles per second (Hertz) or cycles per ns (Ghz) • Currently: 0.032 micron (µm), 32 nanometers (nm) • Determined by micro-architecture, technology parameters • Continued miniaturization (scaling) known as “Moore’s Law” • This unit: transistors & semiconductor technology • Won’t last forever, physical limits approaching (or are they?) CIS 501 (Martin/Roth): Technology 5 CSE 371 (Roth): Performance 6 Complementary MOS (CMOS) Basic CMOS Logic Gate • Voltages as values • Inverter: NOT gate • One p-transistor, one n-transistor • Power (VDD) = “1”, Ground = “0” power (1) • Basic operation • Two kinds of MOSFETs 0 p-transistor • Input = 0 1 • N-transistors input output • P-transistor closed, n-transistor open • Conduct when gate voltage is 1 (“node”) • Power charges output (1) • Good at passing 0s • Input = 1 n-transistor • P-transistors • P-transistor open, n-transistor closed • Conduct when gate voltage is 0 • Output discharges to ground (0) ground (0) • Good at passing 1s 1 0 • CMOS • Complementary n-/p- networks form boolean logic (i.e., gates) • And some non-gate elements too (important example: RAMs) CIS 501 (Martin/Roth): Technology 7 CIS 501 (Martin/Roth): Technology 8 Another CMOS Gate Example • What is this? Look at truth table A B • 0, 0 ! 1 • 0, 1 ! 1 output • 1, 0 ! 1 A • 1, 1 ! 0 B • Result: NAND (NOT AND) • NAND is “universal” A • What function is this? B Technology Basis of Clock Frequency output A B 9 CIS 501 (Martin/Roth): Technology CIS 501 (Martin/Roth): Technology 10 Technology Basis of Clock Frequency Resistance • Physics 101: delay through an electrical component ~ RC • Channel resistance 1 • Resistance (R) ~ length / cross-section area • Wire resistance • Slows rate of charge flow • Negligible for short wires • Capacitance (C) ~ length * area / distance-to-other-plate 1!0 • Stores charge • Voltage (V) • Electrical pressure 1 • Threshold Voltage (Vt) • Voltage at which a transistor turns “on” I 0!1 • Property of transistor based on fabrication technology 1!0 • Switching time ~ to (R * C) / (V – V ) t 1!0 • Two kinds of electrical components • CMOS transistors (gates) • Wires CIS 501 (Martin/Roth): Technology 11 CIS 501 (Martin/Roth): Technology 12 Capacitance Transistor Geometry: Width Length" Gate • Gate capacitance 1 Drain Source • Source/drain capacitance Gate • Wire capacitance 1!0 Width • Negligible for short wires Source Drain Width" 1 Bulk Si Length I Diagrams © Krste Asanovic, MIT 0 1 1!0 ! • Transistor width, set by designer for each transistor • Wider transistors: 1!0 • Lower resistance of channel (increases drive strength) – good! • But, increases capacitance of gate/source/drain – bad! • Result: set width to balance these conflicting effects • Implication: number of “outputs” of gate matters CIS 501 (Martin/Roth): Technology 13 CIS 501 (Martin/Roth): Technology 14 Transistor Geometry: Length & Scaling Wire Geometry Pitch Length" Gate Drain Source Gate Width Height Source Drain Width" Length Bulk Si Length Width Diagrams © Krste Asanovic, MIT IBM CMOS7, 6 layers of copper wiring • Transistor length: characteristic of “process generation” • Transistors 1-dimensional for design purposes: width • 45nm refers to the transistor gate length, same for all transistors • Wires 4-dimensional: length, width, height, “pitch” • Shrink transistor length: • Longer wires have more resistance • Lower resistance of channel (shorter) – good! • “Thinner” wires have more resistance • Lower gate/source/drain capacitance – good! • Closer wire spacing (“pitch”) increases capacitance • Result: switching speed improves linearly as gate length shrinks CIS 501 (Martin/Roth): Technology 15 CIS 501 (Martin/Roth): Technology From slides © Krste Asanovic, MIT 16 Increasing Problem: Wire Delay RC Delay Model Ramifications • RC Delay of wires • Want to reduce resistance • Resistance proportional to: resistivity * length / (cross section) • Wide drive transistors (width specified per device) 1 • Wires with smaller cross section have higher resistance • Short gate length • Resistivity (type of metal, copper vs aluminum) • Short wires • Capacitance proportional to length • Want to reduce capacitance 1!0 • And wire spacing (closer wires have large capacitance) • Number of connected devices • Permittivity or “dielectric constant” (of material between wires) • Less-wide transistors (gate capacitance 1 • Result: delay of a wire is quadratic in length of next stage) I • Short wires 0 1 • Insert “inverter” repeaters for long wires 1!0 ! • Why? To bring it back to linear delay… but repeaters still add delay • Trend: wires are getting relatively slow to transistors 1!0 • And relatively longer time to cross relatively larger chips CIS 501 (Martin/Roth): Technology 17 CIS 501 (Martin/Roth): Technology 18 Cost • Metric: $ • In grand scheme: CPU accounts for fraction of cost • Some of that is profit (Intel’s, Dell’s) Desktop Laptop Netbook Phone $ $100–$300 $150-$350 $50–$100 $10–$20 % of total 10–30% 10–20% 20–30% 20-30% Fabrication & Cost Other costs Memory, display, power supply/battery, storage, software • We are concerned about chip cost • Unit cost: costs to manufacture individual chips • Startup cost: cost to design chip, build the manufacturing facility CIS 501 (Martin/Roth): Technology 19 CIS 501 (Martin/Roth): Technology 20 Cost versus Price Manufacturing Steps • Cost: cost to manufacturer, cost to produce • What is the relationship of cost to price? • Complicated, has to with volume and competition • Commodity: high-volume, un-differentiated, un-branded • “Un-differentiated”: copper is copper, wheat is wheat • “Un-branded”: consumers aren’t allied to manufacturer brand • Commodity prices tracks costs closely • Example: DRAM (used for main memory) is a commodity • Do you even know who manufactures DRAM? • Microprocessors are not commodities Source: P&H • Specialization, compatibility, different cost/performance/power • Complex relationship between price and cost CIS 501 (Martin/Roth): Technology 21 CIS 501 (Martin/Roth): Technology 22 Manufacturing Steps Transistors and Wires • Multi-step photo-/electro-chemical process • More steps, higher unit cost + Fixed cost mass production ($1 million+ for “mask set”) ©IBM From slides © Krste Asanovi!, MIT CIS 501 (Martin/Roth): Technology 23 CIS 501 (Martin/Roth): Technology 24 Manufacturing Defects Unit Cost: Integrated Circuit (IC) Correct: • Defects can arise • Chips built in multi-step chemical processes on wafers • Under-/over-doping • Cost / wafer is constant, f(wafer size, number of steps) • Over-/under-dissolved insulator • Chip (die) cost is related to area Defective: • Mask mis-alignment • Larger chips means fewer of them • Particle contaminants • Cost is more than linear in area • Why? random defects • Try to minimize defects • Larger chips means fewer working ones Defective: • Process margins • Chip cost ~ chip area#" • Design rules • # = 2 to 3" • Minimal transistor size, separation Slow: • Wafer yield: % wafer that is chips • Or, tolerate defects • Die yield: % chips that work • Redundant or “spare” memory cells • Yield is increasingly non-binary - fast vs slow chips • Can substantially improve yield CIS 501 (Martin/Roth): Technology 25 CIS 501 (Martin/Roth): Technology 26 Additional Unit Cost Fixed Costs • After manufacturing, there are additional unit costs • For new chip design • Testing: how do you know chip is working? • Design & verification: ~$100M (500 person-years @ $200K
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