1 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. eFPGAs Visionary Industrial Survey of Programmable Technologies Visionary SurveyIndustrial of Programmable : Architectural Explorations, System Integration & a Explorations,Integration System Architectural : PhD Presentation Defense Wed. Wed. June Syed Zahid syed 22 , - Montpellier, FRANCE Montpellier, [email protected] 2011 , 14 : 30 h, LIRMM seminar hall seminar LIRMM h, Ahmed 2 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Sources for values: for Sources Segment: FPGAs ( Industry Semiconductor INTRO [ INTRO Flexibility iSuppli 1 , Gartner , / 3 ] Becoming Becoming Prog FPGAs (~ 4 B$) Industrial Industrial Survey . SoC , ASICs/ASSPS, eFPGA: eFPGA: Inverse reduce of FPGA, FPGA Hard for What, Why,Where eFPGAs? ASIC/ASSP guys to drop their product to FPGAs their product to drop guys ASIC/ASSP all for/to provider System to become vendors FPGA 2009 - 10 : ) (~ (~ eFPGA Arch. Arch. & CAD eFPGA 80 230 Lower B$) ASICs B$) FPGA FPGA - end vs eFPGA eFPGA thin boundary Mid/High ASICs/ASSPs Beyond Beyond eFPGA Arch. Exploration Arch. eFPGA 65 - end nm SoC vs Costs: Costs: ASIC gap 50 Seeking Seeking limited +M$ flexibility eFPGA in in Systems eFPGA SoCs Silicon - Efficiency END 3 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. INTRO [ INTRO eFPGAarchitecture conventional (LUT eFPGAs Global Overview literature, patents, press news Survey& Analysis 2 Potentials Potentials of emerging trends FPGA the State of Art: … node (tech. Soft eFPGAs independent) Creation CAD of Tools infrastructure Exploration of / 3 ] Industrial Industrial Survey efficient! FPGA - based) - eFPGA Arch. Arch. & CAD eFPGA like B of Thesis Work/Contributions e FPGA iPhD R eFPGA Arch. Exploration Arch. eFPGA G … Survey Semiconductor industry analysis beyond classic (MRAM etc.) eFPGAs eFPGAin system … Case studies perspectives for of eFPGAs as eFPGAs applications/challenges of of Programmable technologies Reconf eFPGA in in Systems eFPGA . accelerators END 4
© SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. [ INTRO FPGA/eFPGA FPGA/eFPGA State Art of the iTalk 3 & Industrial Survey &Industrial / 3 ] Industrial Industrial Survey [ 4 ] Arch. Arch. &CAD eFPGA Arch. & CAD CAD & Arch. eFPGA eFPGA Talk Outline [ 4 ] Arch. Arch. Exploration eFPGA Arch. Arch. Exploration eFPGA eFPGA [ 13 In In Systems ] eFPGA eFPGA in in Systems eFPGA [ 7 Concl ] . & Future . & END END [ 3 ] 5 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. FPGA/eFPGA FPGA/eFPGA State Art of the Only Basics iTalk FPGA FundamentalsFPGA Industrial survey (key conclusions for eFPGAs) eFPGAs) for conclusions (key survey Industrial the Art State of FPGA/eFPGA & Industrial Survey &Industrial INTRO INTRO “ Survey Survey of new forProgrammable inIndustry MPPAs, trends hardware: FPGAs, Survey is published in detail in Industrial Survey Industrial [ 0 / Arch. Arch. &CAD 4 ] eFPGA eFPGA Arch. & Arch. CAD eFPGA FPL - 10 Outline Arch. Arch. Exploration eFPGA eFPGA Arch. Exploration Arch. eFPGA MPSoCs , Structured Asics, eFPGAs and of inand FPGAs wave eFPGAsnew innovation Structured ,Asics, In In Systems eFPGA eFPGA in in Systems eFPGA Concl . & Future . & END ” 6 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. INTRO INTRO Most Topology widely used Island Island Style FPGA Industrial Survey Industrial [ 1 / 4 ] FPGA Fundamentals eFPGA Arch. & Arch. CAD eFPGA (Vender Independent) (Vender eFPGA Arch. Exploration Arch. eFPGA Gates BLEs to LBPlacement to Gates HDL BLEsLB to LBRouting eFPGA in in Systems eFPGA Programming Flow END 7 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Adv. Adv. Research: Mainstream: Key New Trends in leading FPGAs: Startups Xilinx Some other notable: UBC, LIP Lattice INTRO INTRO Highest work Citation:VPR Univ. Toronto Hard Processors, Processors, Hard ( Async ( Async Academics (FPGA Academics (FPGA Arch.) Achronix (* *Tier Logic * Industrial Survey Industrial Actel AboundLogic RIP ., ., Packet Altera . . FPGAs) 2010 ( MicroSemi - ) based routing, New Memories…) ( 3 FPGA/eFPGA State of theArt 3 D stacking, ESL stacking, D D FPGA, Easy ASIC migration) ASIC EasyFPGA, D (Ultra high density Low Cost FPGAs) Cost Low density high (Ultra (Low Power FPGAs) Power (Low [ 2 SiliconBlue 6 / The The 4 , Cornell Cornell , Univ.,UCLA … ] ) BIG eFPGA Arch. & Arch. CAD eFPGA Atmel Atmel - 2 (> 80 (Time Multiplexed FPGAs) (Time Multiplexed % market share of % PLD) QuickLogic Tabula eFPGA Arch. Exploration Arch. eFPGA Some Some eFPGAs Attempts of M eFPGA in in Systems eFPGA 2000 Actel Adaptive Adaptive ( Silicon Only one current current Only company one Leopard Leopard Logic ( IBM Last known warrior known Last /Abound /Abound ( Varicore - Xilinx ( Xilinx MENTA (RIP: year)~Death 2008 2002 ( 2002 2001 2001 END / 2010 ) ) ) ) ) 8 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. What is What is right with thisWhat one? is right Grain Grain INTRO INTRO Processor Processor Soft/Hard Fine/Coarse (Well known success) (Well known problematic Reconf FPGA Industrial Survey Industrial . Unit . Key perspectives for eFPGAs in System from FPGA/eFPGA &visionaryindustrialsurvey with this one? failed failed why? often often fail/ [ 3 / 4 ] VS eFPGA Arch. & Arch. CAD eFPGA End End result: often Chaos - - customer ok with it? - Cons: Pros: Processor Who is provider?end Programming challenge? Processor/ Best Best Performance (example: Servers, MCUs,Intel’s WhichProcessor??? What one? with is betterthis Potentials Potentials of eFPGAs (SIP/ SoC vendor, end eFPGA Arch. Exploration Arch. eFPGA FPGA FPGA Stellarton SoC communication Cons: modal like FPGAs Pros: ) ) eFPGA in in Systems eFPGA Similar more independent More More cyclewaste in END 9 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Fab exploitationby Pure HDL for quickand portability Soft Implementation of of coarse grain (wider applicationsscope) FPGA FPGA INTRO INTRO /Process node - like LUT - like Architecture Industrial Survey Industrial - SoC basedinsteadconventional on any Key research motivations for eFPGA from FPGA/eFPGA &visionaryindustrialsurvey [ 4 / 4 ] eFPGA Arch. & Arch. CAD eFPGA eFPGA eFPGA Arch. Exploration Arch. eFPGA arch. in terms of Area, Power, Speed) Architecturalinnovations (silicon GUI infrastructure for exploring Customization Infrastructure (migrate/reuse) . . RTL Programming Standard Programming Exploitation Exploitation IP of Exploitation ESL of eFPGA in in Systems eFPGA - Ecosystem Ecosystem - efficient END 10 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. FPGA/eFPGA FPGA/eFPGA State Art of the iTalk & Industrial Survey &Industrial INTRO Industrial Industrial Survey INTRO eFPGA creation/exploration infrastructure (eFPGA Creator™) (eFPGA infrastructure creation/exploration eFPGA Programmer™) (eFPGA CAD programming eFPGA Fundamentals,Differentiations Arch. eFPGA Arch. Arch. &CAD eFPGA Arch. & CAD & eFPGA Arch. eFPGA Outline [ 0 / Arch. Arch. Exploration 4 ] ] eFPGA eFPGA Arch. Arch. Exploration eFPGA In In Systems eFPGA eFPGA in in Systems eFPGA Concl . & Future . & END 11 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Unified SB Island Uni INTRO Industrial Industrial Survey INTRO classical classical Interconnect) Local - - Directional Directional Routing style ( (No Connection Block No No Block Connection (No 2 D Mesh) Arch. Mesh) D eFPGA Architecture Fundamentals eFPGA Arch. & CAD & eFPGA Arch. LUT Size: LUT Size: NO Local Interconnect SB - eLB Muxes BLE BLE K Cluster Cluster Size: - - N [ 1 1 / 4 ] ] eLBin N eFPGA Arch. Arch. Exploration eFPGA (K*N) eLBout (N) Channel Channel Width/Size U = W/2 U = eFPGA in in Systems eFPGA : W SB - Routing Routing END Mux 12 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Contribution of this Thesis! of Contribution eFPGA Programmer is not Programmer eFPGA INTRO Industrial Industrial Survey INTRO MGTECH library Arch. Files The programming tools suite of eFPGA tools suite The programming eFPGA Arch. & CAD & eFPGA Arch. eFPGA Programmer™ eFPGA eFPGA Programmer™ Synopsys® (DC) Placement Clustering Synthesis Bitstream Mapping Routing Source [ 2 HDL / 4 ] ] To eFPGA Core To eFPGA eFPGA Arch. Arch. Exploration eFPGA Standard Standard RTL programming flow like FPGAs Constraints eFPGA in in Systems eFPGA END 13 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. INTRO Industrial Industrial Survey INTRO eFPGA Creator™ GUI tools suite eFPGA Arch. & CAD & eFPGA Arch. for creatingCustomized eFPGAs Key Motivations Component Component Editors some snapshots for general feeling for general some snapshots Industrialscenario (companyproduct) Architecturalinfrastructureexploration (Library Manager) Analyzers [ Creator 3 / eFPGA eFPGA 4 ] ] (Architecture (Architecture Manager) Architecture Architecture Editors Hardware Hardware +Scripts ™ eFPGA Arch. Arch. Exploration eFPGA Generators eFPGA in in Systems eFPGA END 14 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. INTRO Industrial Industrial Survey INTRO Exploration Flow eFPGA architectural exploration/creation eFPGA architecturalGUI toolssuite eFPGA Arch. & CAD & eFPGA Arch. eFPGA Creator™ [ 4 / 4 ] ] eFPGA Arch. Arch. Exploration eFPGA Key Differentiations exploration Key Contributions of this thesis Advanced Advanced GUI (Qt to some previous works ( Enhanced what Product marketing Product Analyzers Analyzers infrastructure for architectural Hardware generation system Components customization systems scenario industrial General in motivations - if exploration ease compared in Systems eFPGA - based) based) infrastructure e.g VPR) END 15 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. FPGA/eFPGA FPGA/eFPGA State Art of the iTalk LUT size, Cluster size, Channels sizes sizes etc. size, Channels size, Cluster LUT Basic explorations Phase & Industrial Survey &Industrial INTRO Industrial Industrial Survey INTRO - 1 : Pre - eFPGA eFPGA Creator Arch. Arch. &CAD eFPGA Arch. & Arch. CAD eFPGA eFPGA Outline Arch. Arch. Exploration eFPGA Arch. Exploration [ Exploration eFPGA Arch. eFPGA Switch block Depopulation (SB Depopulation Switch block Advanced Customizations Phase 0 / 13 In In Systems ] eFPGA - 2 : Post eFPGA in in Systems eFPGA - eFPGA Creator - RSB & Concl . & Future . & - eLB END ) 16 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Key Key Objectives INTRO Industrial Industrial Survey INTRO Analysis Architectural LUT size/mapping Channel width Channel Clustering eFPGA Exploration(General) Architectural Channelpacking SB SB traffic (Hop)Routing eFPGA Arch. & Arch. CAD eFPGA Tile Phase eFPGA Arch. Exploration [ Exploration eFPGA Arch. - 1 elements(LUT, Conf., SB, buffering…) ( Silicon Analysis Area, Area of distributionfundamental Basic Basic Timing Power 1 / 13 ] (Static& PessimisticDynamic) eFPGA in in Systems eFPGA 90 , 65 , 45 nm) END 17 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. INTRO Industrial Industrial Survey INTRO Lut Adaptable VHDL , Cluster, Channel, Arr Channel, , Cluster, Basic Basic Explorations ay parameters Parameters eFPGA Tile eFPGA Arch. & Arch. CAD eFPGA Process/constraints MCNC bench. Synopsys® Experimentation Methodology eFPGA eFPGA CAD DC™ Phase Mapping, Clustering, Area, Area, Power*, Speed PAR statistics PAR statistics eFPGA Arch. Exploration [ Exploration eFPGA Arch. Analyzer tools - 1 2 / 13 ] eFPGA in in Systems eFPGA END 18 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. voltage on static power andspeed Power (long/diagonalwires) Routing HOP: routing) requirements of (perspectives applicationsfor beyond classical Routing Challenges: in same proportion clustersize as size: Cluster& Channel LUT size: MostPhaseof INTRO Industrial Industrial Survey INTRO vs Biggerhave LUTspoor mappingefficiency Speed in beyondin Speed Importance of Heterogeneousrouting tracks - 1 Results Published in detailin ReCoSoC’Results Published Highly fluctuating channel size Highly fluctuatingchannel Channeldemandsize does notgrow 90 nm: eFPGA Arch. & Arch. CAD eFPGA Effect of threshold Phase Key Findings eFPGA Arch. Exploration [3/13] Exploration eFPGA Arch. - 08 1 eFPGA in in Systems eFPGA END 19 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. tracks tracks (<= From routing eLBout Size of each No. of Key Objective: INTRO Industrial Industrial Survey INTRO Muxes (N SB - 4 bits) - U eLB Mux - bits) = K*N Muxes <= Reduce 4 U+ N SIZE SwitchDepopulationMultiplexers Block eFPGA Arch. & Arch. CAD eFPGA of SB - eLB What/Why Depopulation? What/Why & SB Phase - R *Fs = SB flexibility Muxes eFPGA Arch. Exploration [ Exploration eFPGA Arch. - while maintaining maintaining efficiency while routing good 2 eLBout 4 / 13 ] Size Size of each No. of Fs* (N - eFPGA in in Systems eFPGA - bits) bits Muxes SB - Mux R = Muxes 4 U <=N + Fs END 20 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Cluster Cluster size (N) = LUT (K)size = Fixed Parameters Channel Channel size (W)= Only this one will be presented INTRO Industrial Industrial Survey INTRO 4 48 4 Switch Block Multiplexers Depopulation (Methodology) SwitchDepopulationMultiplexers Block eFPGA Arch. & Arch. CAD eFPGA Phase eFPGA Arch. Exploration [ Exploration eFPGA Arch. - 2 5 / 13 ] eFPGA in in Systems eFPGA END 21 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. 3 U+eLBout = U+eLBout STRATEGY Base Flexibility) Base Case (High 7 - SB bit INTRO Industrial Industrial Survey INTRO - eLB 76 - - 1 bit N Port Cut : Ports Clipping: Ports BLE Case eLBout - 1 SB 3 - bit - R (FIXED) + Fs = + Fs 7 - bit eFPGA Arch. & Arch. CAD eFPGA 2 U+eLBout = U+eLBout 6 - bit SB SB - eLB - eLB Phase 52 N+E Port Cut - bit Explorations Case BLE eFPGA Arch. Exploration [ Exploration eFPGA Arch. Size = - eLBout 2 - 3 SB - 2 bit - 4 7 SB R (FIXED) U+eLBout = U+eLBout - + Fs = + Fs bit - eLB 7 Mux - bit 100 BLE 6 / 2 - 13 bit U+eLBout = U+eLBout ] 6 - 3 SB bit Size = - bit - eLB 50 SB eFPGA in in Systems eFPGA % of NSEWall Ports Cut - eLBout 52 R Mux - bit BLE (FIXED) + Fs = + Case eLBout 7 - 3 3 - SB - bit bit - R (FIXED) + Fs = + Fs END 7 - bit 22 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. U+eLBout In_ In_ In_ In_ (NSEW) Tracksall from cluster For in BLEs all STRATEGY 3 2 1 0 7 SB - bit INTRO Industrial Industrial Survey INTRO - tracks{( tracks{(U/ tracks{(U/ tracks{ eLB = DIVERSITY 28 Case - - 0 bit 2 3 to to (U/ U/ : Complex Patterns : Complex 2 4 - BLE 1 4 ( to ) (U/ to ) ) to U to ) 4 ) 3 - U/ 1 eLBout - 3 }+ 2 1 - 4 ) }+ SB bit - ) 1 eLBout - 1 }+ - eLBout R (FIXED) }+ + Fs = + Fs eLBout eLBout 7 - bit eFPGA Arch. & Arch. CAD eFPGA In_ In_ In_ In_ (NSEW) Tracksall from cluster in For BLEs all 3 2 1 0 U+eLBout 7 - tracks{( tracks{( tracks{( tracks{( bit SB SB - eLB DIVERSITY+ - = eLB Phase 3 2 1 0 28 Case + + + + 4 4 4 4 - t), for for t t), for t t), for t),t for t t), bit Explorations BLE - eFPGA Arch. Exploration [ Exploration eFPGA Arch. 2 0 0 0 0 eLBout to (U/ to (U/ to (U/ to (U/ to - 3 SB - 2 bit - R (FIXED) 4 4 4 4 + Fs = + Fs ) ) ) ) - - - - 1 1 1 1 }+ }+ }+ }+ 7 eLBout eLBout eLBout eLBout - bit 7 / U+eLBout 13 ] 7 - SB bit - eLB In_ In_ In_ In_ cluster in For BLEs all eFPGA in in Systems eFPGA = 28 3 2 1 0 - bit One Port per pin tracks{all S port} S port} tracks{all + tracks{allE port} + N port} tracks{all+ W port} tracks{all + BLE VPR Case - like eLBout - 3 3 SB - bit - R (FIXED) + Fs = + Fs END eLBout eLBout eLBout eLBout 7 - bit 23 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs.
Tile Area (um²) 10000 12000 14000 16000 INTRO Industrial Industrial Survey INTRO
LD (LUT4/mm²) 2000 4000 6000 8000 250 300 350 400 450 0 BASE STRATEGY SB - eLB eFPGA Arch. & Arch. CAD eFPGA - 1 explorations: Silicon StatisticsSiliconexplorations: (ST STRATEGY Phase eFPGA Arch. Exploration [ Exploration eFPGA Arch. - 2 - 2 SB SB eLB Conf. Buff. - - R eLB 65 STRATEGY STRATEGY 8 / 13 nm LP) nm ] - - eFPGA in in Systems eFPGA 2 (S2) : Complex Patterns 1 (S 1 ) : Ports ): Ports Clipping END 24 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. 10 15 20 25 30 35 40 0 0 0 1 1 1 0 5 ...... 1 4 6 8 2 4 6 INTRO Industrial Industrial Survey INTRO Base Routing Routing S 1 _Case Relative Gains in Area, Speed&Power* STRATEGY Statistics: Statistics: win near - 1 S 1 _Case - 1 eFPGA Arch. & Arch. CAD eFPGA - 2 SB - win win situation for Strategy S 2 - _Case eLB STRATEGY - explorations: Tradeoffs explorations: 1 Phase S 2 _Case eFPGA Arch. Exploration [ Exploration eFPGA Arch. - 2 - 2 - - 2 2 Iterations Routing Channel Avg. Max. Channel Power Speed Logic Density 9 / STRATEGY STRATEGY 13 ] eFPGA in in Systems eFPGA - - 2 1 (S (S 2 1 ) : Complex ): Complex Patterns ): Ports Clipping END 25 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. INTRO Industrial Industrial Survey INTRO In a similar fashion like SB RESULT: ~ 1 . 2 eFPGA Arch. & Arch. CAD eFPGA X AREA Improvement & Improvement AREA X Size = SB - 4 eLB - U+eLBout = eLB Mux , SB SB (FIXED) Phase - 100 - R Explorations R BLE - bit Muxes eFPGA Arch. Exploration [ Exploration eFPGA Arch. Size <= - ~ Explored Explored in Detail 2 1 SB . 45 - eLBout R X SPEED X Mux + Fs 10 Improvement / 13 ] eFPGA in in Systems eFPGA END 26 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. 0 0 0 1.2 1 1 1 ...... 1 4 6 8 4 6 8 BASE INTRO Industrial Industrial Survey INTRO SB Good for Speedfor Good - R Exploration Detailed exploration Saga and finding of Golden Tiles of Golden finding and Saga explorationDetailed Relative Relative Gains in Area, Speed &Power * eFPGA Arch. & Arch. CAD eFPGA SB - eLB Good for Area for Good Exploration Phase eFPGA Arch. Exploration [ Exploration eFPGA Arch. - 2 Exploration Exploration of Mix of GOLDEN TILESGOLDEN SB - R & SB best best of - 11 eLB / 13 ] eFPGA in in Systems eFPGA STRATEGY Power Speed Density Logic STRATEGY Complex Complex Patterns Ports Ports Clipping - - 1 2 (S (S 1 2 END ): ): 27 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. V. Betz & J. Rose VPR Arch ~ RoseArch VPRV. J. Betz & FPGA FPGA Architectures'', IEEE Transactionson VLSI Systems, February * Equiv. Soft VPR arch. replica according to published* results: to published* according replica Soft VPREquiv. arch. CB CB A. A. Marquardt,V. BetzJ. and Rose, ``Speed Area and Tradeoffsin Cluster 5 29 bit Widely explored arch. in academics ( Mux INTRO Industrial Industrial Survey INTRO bit Fc,in 4 LI bit 14 = 0 Mux bit . 6 W, Fc,out What achieved with SB with What achieved BLE 1997 = W/N{ (Toronto Univ.) (Toronto CB CB still still is 1 bit 2 combined? bit eFPGA Arch. & Arch. CAD eFPGA Mux Fs ) 2000 = 2 W - Based bit SB 3 , 3 (Channel size) = (Channel size) K bit Mux } (LUT size) = size) (LUT - R & SB Phase eFPGA Arch. Exploration [ Exploration eFPGA Arch. - eLB 4 , 48 N - 2 multiplexers depopulation multiplexers , (Cluster size) = size) (Cluster U (W/ 2 Unified SB with diverse SB )= eFPGA eFPGA SB - SB 24 eLB 5 bit - 12 eLB 28 = U+N, SB / 4 13 bit Mux - ] R, SB - eLB eFPGA in in Systems eFPGA BLE - R = Fs+1 { best best results found eLB SB connections 2 separately bit - 4 R bit Mux END } 28 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. INTRO Industrial Industrial Survey INTRO Power at 100MHz (uW) 1000 1200 0 1 2 200 400 600 800 . . . 5 5 5 0 1 2 0 Power Relative Speedup benchmarks for on LPLVT LPLVT vs LPSVT LPSVT Speed: Effect of Threshold Voltage and Process(ST type and Voltage Effect ofThreshold Speed: LPHVT LPHVT eFPGA Arch. & Arch. CAD eFPGA GPLVT GPLVT 65 nm process types Phase GPSVT GPSVT eFPGA Arch. Exploration [ Exploration eFPGA Arch. GPHVT GPHVT - 2 Static Dynamic Multiple Electrical Implementations 13 of same Logical of sameLogical Architecture / 13 ] eFPGA in in Systems eFPGA 65 nm) END 29 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. FPGA/eFPGA FPGA/eFPGA State Art of the iTalk Ok Now we got eFPGA, what to do with it! Beyond Classics (MRAMs) case study, Test Chips! Test study, case (MRAMs) Beyond Classics & Industrial Survey &Industrial INTRO Industrial Industrial Survey INTRO Reconf . Acceleration Experiments (Usual Suspect (Usual Experiments Acceleration . Arch. Arch. &CAD eFPGA Arch. & Arch. CAD eFPGA eFPGA Outline Arch. Arch. Exploration eFPGA Arch. Arch. Exploration eFPGA eFPGA ) In In Systems eFPGA in Systems eFPGA in [ eFPGA 0 / 7 ] Concl . & Future . & END 30 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. speedup X design ease) some worksprevious Key differentiation compared to Phase ESL exploitation perspectives Standard RTL flow Conventional FPGA Silicon tradeoffs tradeoffs Silicon visualization INTRO Industrial Industrial Survey INTRO LUT Step - 1 - - eFPGA usedfor experiments - 6 factor!) 1 Published Published in , Cluster : eFPGA with - 4 , Channel ReConFig - like eFPGA Mlite Reconfigurable Acceleration - 2008 - processor 32 (HW/SW co (HW/SW (not just eFPGA Arch. & Arch. CAD eFPGA - Step eFPGA Arch. Arch. Exploration eFPGA
32 - Unit Int. 2 : eFPGA LEONwith K/
32 K Cache MUL/DIV Only this one will be presented be will one Only this LEON3
Published Published in eFPGA 3 RAM AMBA (Co eFPGA in Systems eFPGA in [ - DATE processor & FunctionalUnit) - 2009
Controller Co Configurator eFPGA 1 / - Processor 7 ] END 31 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. INTRO Industrial Industrial Survey INTRO C/C++ Leon Profiling (HW/SW Partitioning) (HW/SW Profiling Application (C/C++) 3 VHDL/Verilog eFPGA eFPGAProgrammer C/C++ (Mentor Graphics®) (Mentor Conf. Catapult™ ExperimentationFlow eFPGA Arch. & Arch. CAD eFPGA eFPGA Arch. Arch. Exploration eFPGA eFPGA in Systems eFPGA in [ 2 / 7 ] END 32 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. AES&DES applications INTRO Industrial Industrial Survey INTRO - ability LUTsof of - - Bit Bit level operations AES explained is Suitable for analyzing levelbit random logic mapping Function Function name AddRoundKey KeyExpansion eFPGA MixColumns ShiftRows SubWord RotWord SubByte Product main AES Called eFPGA Arch. & Arch. CAD eFPGA 576 10 10 11 10 10 ApplicationAnalysis 1 9 1 1 execution 100.0% 54.6% 16.9% 17.0% 81.9% 0.8% 2.2% 8.9% 9.1% 9.1% % of eFPGA Arch. Arch. Exploration eFPGA } { void for( } { for( for( int short MixColumns for(j= } { for(j= for(j= i,j,k i i i = = = int 0 0 0 ;i< ;i< ;i< T[ } { for(k= C[ (Product(T[k][j],Matrix[ ; i i C[ 0 0 0 4 4 4 ][j]=C[ ][j]= ;j< ;j< ;j< ;i++) ;i++) ;i++) 4 (short ][ 0 4 4 4 C[ ;k< 4 ;j++) ;j++) ;j++) 0 ]; i ; ][j]= i 4 ][j]; ;k++) int eFPGA in Systems eFPGA in [ T[ 4 ][ 4 ]) i ][k]))^ (C[ 3 / 7 ] END i ][j]); 33 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. INTRO Industrial Industrial Survey INTRO eFPGA Arch. & Arch. CAD eFPGA HW - SW SW Partitioning eFPGA Arch. Arch. Exploration eFPGA Pure Soft (Cycles) STEP STEP STEP STEP 40358 - - - - 4 3 2 1 Why Gains so similar for both cases ? cases both similar Why for so Gains (Cycles) Pipeline eFPGA 16244 23752 30722 30430 eFPGA in Systems eFPGA in [ LEON eFPGA and operatingat same ( frequency Attention: Approx. Assumption(but basedon rough facts!) Gain Gain X Times 2.484 1.699 1.313 1.326 Co (Cycles) - eFPGA Processor 16265 23767 30735 30447 4 / 7 ] END Gain Gain X Times 2.481 1.698 1.313 1.325 100 MHz) 34 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Cache(LPSVT) Core Core (LPLVT) INTRO Industrial Industrial Survey INTRO Analysis on ST Areaand power of LEON 65nm LP 32K/32K Total (mm 0.191 0.591 Area 0.4 2 ) What What will 65 Static Power nm LP CMOS Silicon Tradeoffs ( 25 110.93 3 25.63 o 85.3 C ( eFPGA Arch. & Arch. CAD eFPGA ( Core+Cache reconf uW ) . acceleration luxury cost! Dynamic Power 100MHz 100MHz ( 20.65 14.9 5.75 ) mW ) eFPGA Arch. Arch. Exploration eFPGA DP( DP( @(Tr DP(mW) mW mW Static Power ( 65nm LP process ) @(Tr ) ) @(Tr ) 65 Pessimistic assuming all inputsof TILEstoggling - - - 0.25,Stp nm) 1.0,Stp 0.50,Stp mW - ) - Systems eFPGA in [ 0.50) - power power of eFPGA ( 0.25) 0.5) 95.36 47.6 1.27 LVT 23 5 / 93.36 0.105 484 46.6 SVT 7 22 ] LUT 6 END ) 107.8 0.011 HVT 53.8 25 35 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. • • • INTRO Industrial Industrial Survey INTRO Functional Functional unit ESL Importance of Silicon Gap vs Key Key Findings from Hand Hand coded RTL vs Co eFPGA Arch. & Arch. CAD eFPGA - Processor Reconf eFPGA Arch. Arch. Exploration eFPGA . Acceleration experiments eFPGA in Systems eFPGA in [ 6 / 7 ] END 36 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. PCM (Samsung is focused) FRAM (TI is focused) Chief of MRAMsCompetitors Processor (multifunction) M INTRO Industrial Industrial Survey INTRO - eFPGA (co virtually virtually possible) - Dynamic Shadowed - - - Multi M Increased computation Increased computation efficiency Change Change highly highly attractive cofor overhead silicon low - - processor) eFPGA like a dream come true for embedded Computing for embedded true like come adream - Context config eFPGA Arch. & Arch. CAD eFPGA . on the fly! (inherent . on the fly! (inherent Rad - save power - - Non Volatile Re Full/Partial shut down to Live at power power Live up at **** - programmalbe - vs Hard - processing SRAM/Flash Reconf ** MRAMs * . 2 *** contexts contexts eFPGA Arch. Arch. Exploration eFPGA based http://www.eetimes.com/electronics taped http://www.eetimes.com/electronics World’s World’s First MRAM ST - - FPGA out 130 Arch.: Arch.: LUT - architecture Die= nm CMOSnm + CROCUS eFPGA in Systems eFPGA in [ 20 - mm 4 1444 , Cluster , ² - - news/ products/other/ ;Core= LUT 4084935 - 4 , Channel 4 /Updated - 15 4200035 based based FPGA! 7 120 / . 64 7 - ] Researchers /First nmMRAM mm - 16 - MRAM ² - END present - based - - FPGA MRAM - - 37 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. FPGA/eFPGA FPGA/eFPGA State Art of the iTalk & Industrial Survey &Industrial INTRO Industrial Industrial Survey INTRO Arch. Arch. &CAD eFPGA Arch. & Arch. CAD eFPGA eFPGA Outline Arch. Arch. Exploration eFPGA Arch. Arch. Exploration eFPGA eFPGA In In Systems eFPGA in in Systems eFPGA eFPGA Concl END [ END . & Future . & 0 / 3 ] 38 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. • • • • • • • INTRO Industrial Industrial Survey INTRO eFPGAs are Future to key Heterogeneous Perspectives emerging of technologies for FPGAs/eFPGAs eFPGAs have strong potentials for embedded Reconfigurable computing Silicon CAD tools Infrastructure for architecturalexploration eFPGAsof Importance and potentials FPGAof Importance Standards of in Industry – – – – MRAMs have interesting properties for Future FPGAs/eFPGAs Future for properties interesting have MRAMs memories configuration and arch. routing classical beyond for think toNeed to Up with eFPGAs Soft Block Switch Unified to styles depopulated diverse in connected Block Logic with architectures Innovative - efficient efficient eFPGAssoft 400 Conclusions& Future eFPGA Arch. & Arch. CAD eFPGA + LUT + 4 /mm 2 - like like eFPGAs at 65 nm were achieved were nm MPSoC eFPGA Arch. Arch. Exploration eFPGA Platforms eFPGA in in Systems eFPGA END [ END 1 / 3 ] 39 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. INTRO Industrial Industrial Survey INTRO specific) application + purpose (depopulation)efficiency Architecture Near Near Term Enhanced CAD and tools and CAD Enhanced (general Heterogeneity wires Long silicon of enhancement Further Conclusions& Future eFPGA Arch. & Arch. CAD eFPGA eFPGA Arch. Arch. Exploration eFPGA Mid Term enhancements System System level experiments + arch. arch. + level experimentsSystem Standards Industryusing Integration eFPGA in in Systems eFPGA END [ END 2 / 3 ] 40 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. INTRO Industrial Industrial Survey INTRO We We are not Heterogeneous Reconfigurable too far from them them fromfarIndustrially & Academically! (eFPGAs are key) (eFPGAs eFPGA Arch. & Arch. CAD eFPGA Conclusions Conclusions & Future Long term future perspectives termfuture Long eFPGA Arch. Arch. Exploration eFPGA MPSoCs Future Future based based interconnectivity with Heterogeneous elements processing 3 - , graphics, (memories, interface analog/mixed, Specialized 2 Large (Bigsingle/multi Boss!) CPU core 1 classic configuration) configuration) classic Ec PEx architecture/configurationclassic etc.) context, conventional/beyond heterogeneous, Ex Px Description of Elements PHD eFPGAs - - : Conventional : have beyond (can Conventional eFPGA : Plurality of custom eFPGAs (simple, multi (simple, : eFPGAs Plurality of custom : Plurality : Plurality Memory RISC of Small + ASD ASD GPD : Px eFPGA in in Systems eFPGA (Programmable (Programmable Hybrid Domain SoCs with with coEx etc.) (Application (Application Specific Domain) (General (General Purpose Domain) IPs Will have Will have - processor 3 END [ END Domains 3 / NoC 3 ] - - - ) 41 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. co for uniquepotentialsFPGAs'' FPGAs International Publications International Conf. Contributions Industrial Panels - ReCoSoC’ ReConFig’ DATE’ IPESC’ ReConFig’ ERSA’ FPL’ IP’ IP’ IP’ processor'' ReConFig’ 08 07 08 ” (my precious!) 10 : : : 10 09 09 Session Chairman (Prototyping Chairman (Prototyping Session “IP/ “ : : SoC : S. Z. Ahmed et al, : : 08 08 09 L. L. Torres Y. S. Z. Ahmed et al, SoC S. Z. Ahmed et al, 09 Configurability : , ReConFig’ , : : S. Z. Ahmed et al, Prototyping”. With Bull, ST, Mentor Graphics, EVE, S. Z. Ahmed et al, Y. Guillemenet Guillemenet 10 - “ Balancing Manufacturing and R/D Costs”. With Gartner, ARM, ST, MIPS, Survey of of newinSurveyfor trendshardware: IndustryProgrammable FPGAs, MPPAs, ''Exploration of ''Exploration of power andreductionenhancementLEON performancein ''FPGA GUI DesignerTools AhardwareSuite: complete and software infrastructurefor creatingeFPGAcustomizable IP of blocks : , S. Z. Ahmed et al, PC member Track HPRC Trackmember PC ''eFPGA architecture''eFPGA CAD explorations:of andbeyondanalysis Silicon ''Power processors''Power reduction inperformanceexplorationsESL smallconsumption byeFPGAs''reprogrammable using enhancing , S. Z. Ahmed, Major PhD Contributions 2 ) “A Dynamic Reconfigurable MRAM basedFPGA”DynamicMRAM“A Reconfigurable ''MRAM based eFPGAs: programming and silicon flows, exploration environments, MRAM currentstateMRAM in basedflows, and''MRAM eFPGAs: Industryandexploration itsenvironments,programming silicon Synplicity and Menta 3 90 processor ESL eFPGAaswith and processor reprogrammablea in pipeline nm technologies to investigate new dimensions of futureinnovations''of newto nm dimensions investigatetechnologies MPSoCs , Structured, eFPGAsAsics,and new wave in of innovation Transmeta and Menta. Me nta'' 42 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. & now & now Thanks for watching: hope u enjoyed Thankshope u ????? forwatching: “Return of the
FPL-10: http://conferenze.dei.polimi.it/FPL2010/presentations/W1_B_1.pdf JURY Thesis dedicated Slidehas tothis !!” Prof. Reiner Hartenstein Reiner Prof. in inspiration of/from his amazing keynotes andamazing ininspirationhiskeynotes contributions of/fromto Education 43 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Karlsruhe, Karlsruhe, GERMANY Technologies at KIT Senior Scientist Reconfigurable Mr. Michael Examiner Karlsruhe, Karlsruhe, GERMANY Officer (CHEO) at KIT Prof. & Chief Higher Education Mr. Reviewer Montpellier Montpellier FRANCE Research Director at CNRS Mr. Gilles Co Jürgen - adviser H Becker ü Sassatelli bner Lords of the Jury Thesis Thesis Bearer ( Public Public Defense!) You Lorient, Lorient, FRANCE Prof. at UBS Mr. Guy President Gogniat Paris, FRANCE Prof. at UPMC Mr. Reviewer Montpellier, Montpellier, FRANCE Prof. at UM Mr. Lionel Torres Adviser Montpellier, Montpellier, FRANCE Founder & CEO Menta Mr. Laurent Rougé Examiner/co Habib 2 Mehrez / Polytech - adviser 44 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. 45 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. EXTRA Q&A SLIDESfor 46 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. not thisspectrumconsideredin *PC/Serversis market) (Standalone immense - - accelerators, DSPs… - ASSPs ( ( In future opportunity IPs Programmable In future opportunity Big Players (Intel) also preparing! preparing! also Big (Intel) Players Single/ eFPGAs SoC Future is cloudy, H Platforms, Platforms, MCUs…) Mutlicore , Coarse/Mix Grain Coarse/Mix IPs…) Grain , CPU with numerous HW HW numerous with CPU Industry Industry heading towards platformcollisions eFPGA -- - Heterogeneity ContinuedFPGAs Is Hard Processors Embedded FPGAs themselves are becoming FPGAs becoming themselvesare eFPGA Collisions Collisions in Future in a wide sense! awide in e who who win????will te a missingIP ? r o g eneit SoC y + seems imminent Heterogeneity - CPUs/ALUs/Hard blocks - MPPAs, Coarse/Mixed Grain Parallel arrays Processing using of In future opportunity for for opportunity future In vs FPGAs eFPGAs for for 47 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Graveyard Graveyard of Reconfigurable Computing Tales Tales from Proceedings of International FPGAs FPGAs cleverly enjoyed/exploited: FPGAs Nice Nice party Scenario vs CG (Coarse Grain) (Coarse 3 Coarse Coarse unfortunately suffered: Grains wars: Hardware + Language + Near Solo Adventure in Desert in Adventure Solo /CG - like story like - no - IP 48 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Images source: open webopen source: Images (m2000/ Olivier Jonathan Jonathan Greene Kamal Sinan Michael Hutton (Xilinx/ Vaughn Betz Vaughn Inventor of modern FPGAs Xilinx (co Ross Freeman ( ( Altera Altera ( ( Kaptanoglu Actel Actel Lepape Chaudhary Achronix AboundLogic ) ) ) ) Some Some Architecture FPGA Key fromScientists Industry & Academia - founder) ) ) ( 1948 - 1989 ) (m Raminda Stephen M. Steven Fredric Fredric David Lewis Steven Young P. (Xilinx (Xilinx LEGEND) 2000 * (Tabula) 150 Rajit ( Altera (Xilinx (Xilinx LEGEND) 150 ( / + Patents Altera Robert F. Hartmann TierLogic AboundLogic Teig Reblewski Manohar U. + Patents ) Madurawe Trimberger (co ) ( - Achronix founder) ) Alphabetical Lists & In way no Alphabetical Lists cover all, but indeed indeed many! but cover all, ) Telecom Telecom authors) post junior authors) hero students, grad of scene (first not forget behind the &dozens let’s Guy Guy Lemieux Jean Jason Cong * Jason Anderson Jonathan Jonathan Rose (Toronto Univ.) Toronto Univ. Toronto Rajit Cornell Univ. Cornell VPR VPR legend UCLA UBC - Luc Danger Manohar ParisTech a gift from this thesis thisfrom a gift images images phdcomics.com Cham,© J. Steve Wilton Imperial Imperial College Russell - RWTH RWTH Aachen Alan Alan Habib Tobias G. Noll Tobias docs … docs Berkeley Univ. Wayne UMASS UBC Mischenko LIP ! Mehrez Tessier 6 Luk 49 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Phase misex3 s38584 s38417 ex1010 Circuit elliptic bigkey apex2 apex4 diffeq tseng clma ex5p s298 frisc dsip spla alu4 pdc des seq - 1 inputs (LUT mapping with SIS) 131 229 256 229 62 38 29 10 16 20 16 38 41 64 14 14 52 4 9 8 outputs 122 304 106 114 116 197 245 197 14 19 63 82 10 40 46 35 39 8 6 3 MCNC benchmarks LUT No. of 8383 6447 6406 4598 4575 3604 3556 3690 1931 1707 1591 1878 1750 1370 1497 1522 1397 1262 1047 1064 - 4 Phase S S No. 11 10 9 8 7 6 5 4 3 2 1 - 2 Circuit misex3 ex1010 apex2 apex4 diffeq tseng ex5p s298 alu4 (LUT mapping with eFPGA Programmer) seq k2 inputs 10 45 38 41 64 14 14 52 4 9 8 outputs 122 10 45 35 39 14 19 63 6 3 8 I/Os 174 20 10 90 41 76 31 22 28 28 71 LUT4 922 856 546 714 781 714 614 426 742 743 240 50 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Conf. bits Area Normalized to F Power (um²) ST _1.3V 65LPSVT Area Logic Logic Density (LUT4/mm²) m40C Static (nW) (uW/MHz) SBOX R SBOX L SBOX Conf. Total Total Buff. Dyn. Dyn. eLB eLB Phase - tse_4448_F 15023 6720 2440 1402 4043 Base 3.67 1.00 400 468 452 266 418 68 - 2 tse_4448_noN 13550 SB 1394 4066 5232 2440 3.45 0.90 415 295 418 400 468 68 - eLB tse_4448_noN Theme 1 11769 1351 3960 3600 2440 2.87 0.78 365 340 418 384 452 68 E Silicon Stats tse_4448_50p 11758 1340 3960 3600 2440 2.91 0.78 365 340 418 384 452 All 68 tse_4448_c1 1229 3810 1984 2440 9881 2.44 0.66 304 405 418 368 436 68 Theme 2 tse_4448_ 1229 3810 1984 2440 9881 2.41 0.66 304 405 418 368 436 68 c2 tse_4448_ 1229 3810 1984 2440 9881 2.42 0.66 304 405 418 368 436 68 c3 51 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. A.Mean misex3 Circuit ex1010 apex2 apex4 diffeq tseng ex5p s298 alu4 A.Mean seq misex3 Circuit ex1010 k2 apex2 apex4 diffeq tseng ex5p s298 alu4 seq k2 Max 34.7 Ch. Ch. RF RF 38 41 39 27 36 34 42 25 30 Max 32.1 Ch. Ch. 38 41 33 34 37 24 31 28 36 28 23 22.36 15.63 15.8 23.5 10.4 16.9 12.3 23.5 Avg Ch. Ch. 9.4 6.5 tse_4448_c1 tse_4448_noN 20.7 19.1 12.7 15.6 16.9 12.3 17.6 13.4 Avg Ch. Ch. 9.6 8.9 9.2 5 R. Iter 8.22 R. Iter 12 15 10 7 6 7 6 5 6 6.7 8 7 7 7 7 7 7 6 7 6 5 Delay(ns) Delay(ns 17.85 15.92 15.34 15.46 12.25 20.63 12.76 15.17 14.06 19.35 16.13 15.93 12.73 20.72 13.44 11.65 21.06 17.03 15.4 10.9 24.5 17.8 Phase ) Ch. Ch. Max Ch. Ch. Max 34.2 35.2 41 36 38 37 29 33 31 39 24 27 41 RF RF 39 40 43 26 38 33 41 27 30 Ch. Ch. Avg - 20.25 24.5 21.3 14.4 18.8 19.2 11.7 14.3 10.4 5.72 15.6 Ch. Ch. Avg 2 11 15.78 15.58 22.5 10.7 16.7 12.2 23.5 9.4 6.4 23 tse_4448_noNE SB tse_4448_c2 R. Iter - 7.4 8 8 7 8 7 7 8 8 7 7 6 eLB R. Iter 9.4 10 12 24 8 6 7 7 5 6 Delay(ns) explorations 21.98 28.06 16.56 19.23 15.84 17.73 19.96 14.64 12.92 17.95 17.2 13.3 Delay(ns) 15.63 19.23 15.34 12.01 15.58 15.3 17.2 11.2 21.2 13.1 Ch. Ch. Max 21.86 Ch. Ch. Max RF RF RF RF 25 24 19 24 23 20 18 35.25 RF RF RF RF RF RF RF 39 37 33 32 Ch. Ch. Avg tse_4448_50pAll Ch. Ch. Avg 13.4 16.4 4.54 10.3 14.18 8.5 8.6 12 17.6 18.2 13.6 9 7.3 tse_4448_c3 R. Iter 26.43 R. Iter 55 94 10 7.25 7 7 6 6 8 7 8 6 Delay(ns) Delay(ns) 18.57 22.84 16.98 12.54 14.12 11.88 16.08 15.6 16.74 13.41 15.9 12.8 14.7 52 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Equivalent Soft Model of Classical arch. Classical (VPR) Model of Equivalent Soft Size = CB V. Betz & J. Rose VPR Arch ~ RoseArch VPRV. J. Betz & Mux Fc,in Widely explored arch. in academics ( I K*(N+1)/2 I = Size I+N = LI Mux Thesis Thesis Soft eFPGA, objective: eFPGA Architecture Fundamentals 1997 BLE (Toronto Univ.) (Toronto Size <=N+ still still is CB Mux ) 1 Size Fs = SB Mux NEW what Unified eFPGA eFPGA investigation Model of this work Size <= SB - if - eLB experiments - 4 SB with SB U + N + U Mux BLE eliminated LI eliminated and CB Size Fs + N <= SB - R Mux 53 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. * I.Kuon • • • • • • Power Power ASIC at multiple levelsHeterogeneity arch. Challenges of Routing block Challenges of Logic Island & J.& Rose(Toronto Univ.) vs - style, style, Column vs FPGA Gap* Gap* FPGA Performance in in beyond Performance FPGAs literature (vendors + academics) and patents survey patents and FPGAs + academics) literature(vendors ( 35 - based arch.based X Area, X Key FPGA research areas 3 X - 5 90 XSpeed, nm 14 XPower ) All images from Xilinx, Altera Websites 54 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Phase Mapping Analysis Silicon Silicon Analysis Bigger LUTs have poor haveBigger LUTs mapping efficiency mapping - 1 LUT Analysis LUT Size comparison comparison overall comparison Relative Relative LUT LUT size LUT LUT LUT - - - 6 4 3 LUT ( Conf.+Logic % of Tile - 3 19.95 9.42 7.33 inefficient to LUT compared inefficient ) Normalized to LUT4 LUT4 arch. Area Area 1.7 0.8 1 efficiency considered) Logic Capacity wrt 4 LUT4 LUT4 (mapping 1.54 0.75 1 55 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs.
LD (LUT4/mm²) Tile Area (um²) 10000 12000 14000 16000 250 270 290 310 330 2000 4000 6000 8000 0 SB - R StatisticsSiliconExplorations:(ST Phase - 2 SB SB eLB Conf. Buff. - - eLB 65 R nm LP)nm 56 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. 0 0 0.8 0 1 1 1 1 1 1 20 25 30 35 10 15 ...... 6 7 9 1 2 3 4 5 6 1 0 5 Routing Routing tsr_ tsr_ 4436 4436 Relative Relative Gains in Area, Speed &Power* _F _F Statistics: Statistics: near win tsr_ tsr_ 4436 4436 _noN _noN tsr_ tsr_ 4436 4436 - _noNE _noNE win situation win situation by Theme tsr_ tsr_ 4436 SB 4436 _c - _c 2 R Explorations:Tradeoffs 2 tsr_ tsr_ Phase 4436 4436 _c _c 3 3 2 - Routing Routing Iterations Channel Avg. Max. Channel 2 Power Speed Logic Density 57 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Power Power Effect of threshold voltage Effect threshold of vs Performance 58 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. PCM (Samsung is focused) FRAM (TI is focused) Chief of MRAMsCompetitors Processor (multifunction) M - eFPGA (co virtually virtually possible) - Dynamic Shadowed - - - Multi M Increased computation Increased computation efficiency Change Change highly highly attractive cofor overhead silicon low - - processor) eFPGA like a dream come true for embedded Computing for embedded true like come adream - Context config . on the fly! (inherent . on the fly! (inherent Rad - save power - - Non Volatile Re Full/Partial shut down to Live at power power Live up at **** - programmalbe - vs Hard - processing SRAM/Flash Reconf ** MRAMs * . 2 *** contexts contexts MRAMMulti based - Context (low silicon overhead) silicon Context (low silicon LIRMM - efficient MRAM cell structuresMRAM efficient has filed multiple patentson multiplehas filed 59 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. The History PLD startups of http://www.ocoudert.com/blog/ 2009 / 09 / 15 /why - fpga - startups - keep - failing 60 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. by Kenton Williston ( Williston by Kenton Massively parallel processors: Who's alive? still Silicon Hive(Netherlands) ClearSpeed PACT XPP Technologies Elixent PicoChip Stream Processors Inc. Aspex CPU CPU Technology, Inc. Recore Recore (Netherlands) Coherent Coherent Plurality (Israel) IMEC IMEC (Belgium) IP Flex (Japan) Motorola Motorola Labs COMPANY NEC NEC (Japan) Element CXI Rapport Rapport Inc. BrightScale /Panasonic (U.K.) Intellasys MathStar Semiconductor Ambric Tabula Tilera (U.K.) Designs Designs (U.K.) Technologies Logix 2009 Multicore , Inc. ) Industrial Survey on Status ofSeveral on Status Industrial Survey Dynamically Reconfigurable Logic Engine Scalable Scalable Embedded 24 Arrayprocessors Acalis7 Field Multithread Multithread 96 ADRES: Coarse for VLIW's ArrayGrain Reconfig Kilocore HypercoreProcessor: 16 picoArray Field Field Programmable Object Array DAP/DNA AM2000 AM2000 family Storm Moustique Moustique Block Accelerators Linedancer /Coarse Grain companies ( companies /Coarse Grain hx2100 hx2100 BA Video 1024 Processor Montium XPP 3C Reconfigurable Reconfigurable Array . Vector Streaming Processor KC - 1 1 Family PRODUCT TilePro36 TilePro36 & 64 D Unannounced - Massively Parallel Array - - Programmable Programmable MultiCores 256 with 256 with 256 processors 955 16 955 - HyperX - Fabrix Fabrix Array element element processor array - Tile Tile Processors 64 64 processors 4,096 4,096 Processors - 344 Processors 344 - 80 32 80 - bit bit processors - based DSP based - bit bit ALUs - Why http://www.eetimes.com/design/signal blog/ http://www.eetimes.com/electronics 256 256 cores - 4034360 massively /Massively - parallel Was Was shipping videochips, backing but dried up Was Was - chip In In Stealth - Silicon Silicon killed; now marketing for video IP parallel Surveillance Surveillance Video Development Development appears have to ceased - Showing Showing silicon vendors Connex Licensable Licensable activelymarketing IP, Licensable Licensable IP Licensable Licensable IP Now Now Captive; status unknown - 1st 1st generation now shipping processors Now Now selling subsystemsas Appears to have folded Now shipping for video - - Mode** Mode** ( failed Actively marketing IP Development Development ceased blogs/dsp Still Still development in Shipping Shipping in volume COMMENTS Activelymarketing Activelymarketing - Technology; now Technology; IP now marketing processing Out business of In In Development - Who - - starts designline activelymarketing - - - status unknown status s activelymarketing - - - dsp/ still activelymarketing 2009 - 4017733 alive shipping in shipping 2010 - - /Analysis ) - ) 61 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Reconfigurable Computing continue will inspiring researchers and industry andplay important will role in Despite numerous failures, and being still a small niche have something Copyright Copyright Warner Bros. worth living for worth living why do you live dark challenges ahead 62 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Top Top 25 Semiconductor Giants (Foundries excluded) (Foundries Giants Semiconductor Semiconductor EmpireIndustry iSuppli : 2010 forcast , highest growth year ever in history Altera Xilinx ~ Biggest Biggest Stand alone FAB TSMC 85 % of of FPGA market% : ~ : : ~ : : : ~ 1 10 1 , 900 , , 400 000 Million $ Million $ Million $ Top Semiconductor Spenders OEM Semiconductor Top 63 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. 2010 MainMarkets FPGAs of Revenue Revenue Breakdown http://phx.corporate Source:Xilinx Corporate Backgrounder Semiconductor EmpireIndustry - ir.net/External.File?item=UGFyZW 2009 http://www.xilinx.com/company/about.htm Semiconductor Revenue Distribution RevenueSemiconductor Distribution 50 SUQ 9 NDg 3 MzR 8 Q 2 hpbGRJRD 0 tMXxUeXBlPTM=&t= 1 Forecast.aspx Prompts Chain/News/Pages/Semiconductor http://www.isuppli.com/Semiconductor revenue.html global reuse.com/news/ http://www.design of news/ http://www.eetimes.com/electronics onductor_sales_leaders_by_year http://en.wikipedia.org/wiki/Semic industry news/ http://www.eetimes.com/electronics - chips - 4088113 4088277 semiconductor - - - consolidation iSuppli /Who /Viewpoint - to 24061 - - Pump - is - - - inevitable largest / 2010 - - Up Is - - semiconductor - 2010 - buyer - - - Roid - - - - - Rage Value - - - 64 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. iSuppli : 2009 Semiconductor Semiconductor Industry Empire FPGA/PLD FPGA/PLD Market opinion http://www.eetimes.com/electronics http://www.latticesemi.com/corporate/about/pldmarketbackground.cfm?source=topnav - on - the - programmable - imperative - blogs/programmable - - logic - designline - blog/ 4033356 /A - dissenting - 65 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. Dr. Dr. Steve XILINX Trimberger http://ce.et.tudelft.nl/FPL/trimbergerFPL Makimoto’s Customization cycle: Domain SpecificFPGAs New Trends in FPGAs 2007 will and will In coming yearscome and ASSPs FPGAs specific domain and MoreHeterogeneous Industry movingto is .pdf Makimoto’s Power Customization will further force that force will further Cycle 66 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. ( for Global CIFRE PhDMotivations French international audience, Universities & Industry & Universities audience, http://www.anrt.asso.fr/fr/pdf/diapo_presentation_cifre.pdf http://www.anrt.asso.fr/fr/pdf/plaquette_cifre_complete_avril ) 2009 _GB.pdf 67 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. InvitationFlyer to PhD Defense 68 © SZA (linkedin.com/in/SyedZahidAhmed), 22 June 2011: PhD Dissertation: eFPGAs. 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