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State of the Art in FPGA Technology

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State of the Art in FPGA Technology State of the art in FPGA technology Jecel Assumpção Jr LCR - ICMC - USP São Carlos topics • Xilinx vs Altera • Bit players • Rookies • Alternatives Xilinx vs Altera • First FPGA (1985) • First • Sells US$1.7B/year reprogrammable logic device (1984) • First CPLD (1988) • Sells US$1.2B/year Xilinx vs Altera • High End = Virtex • High End = Stratix • 1998 • 2002 • 1999 E • 2003 GX • 2000 II • 2004 II • 2002 II Pro • 2005 II GX • 2004 4 LX/SX/FX • 2006 III • 2006 5 LX/LXT/SXT • 2008 IV E • 2008 5 FXT/TXT • 2008 IV GX • 2009 6 Xilinx vs Altera • Low End = Spartan • Low End = • 1998 Cyclone • 1999 II • 2003 • 2001 IIE • 2004 II • 2003 3 • 2007 III • 2005 3E • 2009 IV • 2006 3A • 2007 3AN/3A-DSP • 2009 6 Xilinx vs Altera Virtex 6 Stratix IV technology 40nm 40nm Logic cells 75K to 588K 72K to 803K Block RAM 6M to 33M 7M to 33M DSP 288 to 864 384 to 1024 Tranceivers Up to 48+24 Up to 48 I/O 380 to 720 372 to 920 speed 600MHz 600MHz Bit player: Lattice • ECP3 - lowest cost FPGA with SERDES • XP2 - 90nm Flash • Also ECP2, ECP2M and SC Bit player: Actel • Igloo and ProASIC3 - low power • SmartFusion and Fusion - mixed signal • RTAX, RTProASIC3 and RTSX - radiation tolerance • Axcelerator, SX-A, eX and MX - antifuse Bit player: QuickLogic • Customer Specific Standard Products (CSSPs) Bit player: Atmel • Legacy devices - AT6000 • AT40KAL + AVR8 = FPSLIC (Field Programmable System Level Integrated Circuits) Edinburgh • 1985 to 1988 - three generations of CAL up to CAL256 • 1989 - Algotronix formed, CAL1024 • 1993 - bought by Xilinx: XC6200 • Very popular for research, but not commercially Imperial College Rookie: Silicon Blue • Classic architecture • Low power • Low cost • Internal Flash Rookie: Achronix • 1.5GHz • picoPIPE assynchronous internal architecture • SERDES • DDR3 controllers Rookie: Tabula • 1.6GHz with 8 multiplexed designs • 48 SERDES • 5.5MB RAM • 220K to 630K logic cells Rookie: Tier Logic Alternative: eASIC • Standard Cell ASIC-like unit cost, power consumption performance and density • Low up-front development cost • Simple, FPGA-like design flow • Device turnaround in only 4-6 weeks Alternative: Stretch Inc Alternative: Trips Alternative: Xmos Alternative: MathStar Alternative: Tilera Alternative: Stream Processors Inc Thanks! references • http://www.xilinx.com/ • http://www.altera.com/ • http://lms.nthu.edu.tw/sys/read_attach. php?id=17968 • http://ce.et.tudelft.nl/FPL/trimbergerFPL 2007.pdf • http://www.fpga- guide.com/overview_frame.html references • http://www.latticesemi.com/ • http://www.actel.com/ • http://www.quicklogic.com/ • http://www.atmel.com/ • http://www.algotronix.com/people/tom/ album.html • http://www.doc.ic.ac.uk/~ipage/papers/ cam95.pdf references • http://www.siliconbluetech.com/ • http://www.achronix.com/ • http://www.tabula.com/ • http://www.tierlogic.com/ references • http://www.easic.com/ • http://www.stretchinc.com/ • http://userweb.cs.utexas.edu/~trips/ • http://www.xmos.com/ • http://www.mathstar.com/ • http://www.tilera.com/ • http://www.streamprocessors.com/.
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