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Achronix Speedcore Risc-V Workgroup May 8-11, 2017 Achronix Speedcore Risc-V Workgroup May 8-11, 2017 Achronix Semiconductor Corporation Confidential © 2017 Achronix Introduction . Founded in 2004 at Cornell University. Achronix has over . Initially developed high performance self-timed FPGAs. 100 person-years invested in the ACE . Currently in production: design tool suite. – Standalone FPGAs, FPGA Accelerator cards, and Embedded FPGAs. San Jose, CA Bangalore, India 2 Achronix Semiconductor Corporation Confidential © 2017 Speedcore . High-performance FPGA core, available to be added to your device. We work with your technology node, your metal stack. You control the FPGA size, BRAM, LRAM, and DSP Density, IO count, etc. Your Device Speedcore High-performance Embedded FPGA . Deliverables Include . GDSII, LEF files, LIB timing files, SPICE netlist, Power models, DFT Netlist, PI & SI simulation models, manufacturing vectors, characterization vectors, and extensive documentation. Custom version of the Achronix ACE tool suite . Includes synthesis, place-and-route, static timing analysis, debug tools, etc. Supports your specific device. 3 Achronix Semiconductor Corporation Confidential © 2017 Processor & Algorithm Acceleration . Example system architecture is from SiFive Freedom u500 Achronix Speedcore eFPGA Your Logic Here Logic Your Your Logic Here Logic Your High throughput, Low latency, Coherent, Programmable Acceleration . An Achronix Speedcore IP with a 128b interface @ 600 MHz 768 Gbps with a round-trip latency of ~10 ns. Compare to ~100Gbps effective throughput with ~1200ns latency for a PCIe Gen3x16 interface. Connect to the TileLink cache-coherent interconnect, allowing for coherent programmable acceleration. Also supports AXI or other on-chip interfaces. Multiple parallel interfaces for higher throughput. You control how many LUTs & Flops, DSP blocks, BRAM blocks, and LRAM blocks. You can invent new block types to put in columns . Speedcore can get it’s own L1 cache if the application would benefit. 4 Achronix Semiconductor Corporation Confidential © 2017 Processor and Algorithm Acceleration IO Acceleration Achronix . Accelerator fits between I/O & system Speedcore eFPGA interconnect. Support multiple of PCIe-based protocols . CCIX, CAPI, Thunderbolt . Support programmable protocol extensions TCP/IP Offload . Specialized transactions, Cache Coherency, CCIX / Custom Custom DMA Engine Protocol . Programmable TCP/IP acceleration . Free up CPU cycles. Programmable packet inspection . Discard unsupported/suspicious packets before they use up memory & CPU bandwidth. Runtime-selection accelerator selection . Switch between accelerator types as needed. Can bypass interface data and provide algorithm acceleration. Reconfiguration is ~2 ms per 100k LUTs. 5 Achronix Semiconductor Corporation Confidential © 2017 Achronix Speedcore eFPGA Compiler: Fast Development of Customer Specific Speedcore IP Inputs Deliverables IP Deliverables: • GDSII • Simulation files • SI and PI models • Test models • Timing characterization • Documentation Full Support in ACE Design Tools 6 Achronix Semiconductor Corporation Confidential © 2017 ACE Design Tools and Supported Features Synplify-Pro from Synopsys ACE Design Tools – high level feature overview Supplied by Achronix . Full Verilog, SystemVerilog and RTL support . Full-fledged STA supporting CRPR, OCV Synthesis IP Configuration derating, multiple corners . TCL command language Place & Route . GUI and command-line control ACE (Achronix CAD Environment) . Highly efficient integrated data model Timing Analysis . Supports all current simulators Bitstream In System – Synopsys VCS, Mentor QuestaSim, Aldec & Download Debugging Riviera, Cadence Incisive. Linux and Windows support . Protected/encrypted IP support Silicon RTL and Post P&R Simulation: Production Version 6.0.6 VCS from Synopsys, Riviera from Aldec, or Available Now Questa from Mentor Graphics 7 Achronix Semiconductor Corporation Confidential © 2017 ACE Design Suite Project Setup & Compile 8 Achronix Semiconductor Corporation Confidential © 2017 ACE Design Suite Floorplanning & Placement 9 Achronix Semiconductor Corporation Confidential © 2017 ACE Design Suite FPGA Program & Snapshot Debug 10 Achronix Semiconductor Corporation Confidential © 2017 Extensive Speedcore Documentation 11 Achronix Semiconductor Corporation Confidential © 2017 Summary . Achronix – is a profitable 12 year old company. – extensive experience designing, manufacturing, shipping, and supporting IP, devices, and boards. Speedcore Embedded FPGA – High-performance on-die programmability with extreme throughput, latency, and power improvements. – Tailored to each design: Size, RAM & DSP density, IO Count, Technology Node & metal stack, etc. ACE – Mature & full-featured FPGA design suite – Over 100 person-years of investment, used in hundreds of FPGA designs. 12 Achronix Semiconductor Corporation Confidential © 2017 Achronix Speedcore Risc-V Workgroup May 8-11, 2017 Achronix Semiconductor Corporation Confidential © 2017 .
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