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Design Automation of Real-Life Asynchronous Devices and Systems Full Text Available At Full text available at: http://dx.doi.org/10.1561/1000000006 Design Automation of Real-Life Asynchronous Devices and Systems Full text available at: http://dx.doi.org/10.1561/1000000006 Design Automation of Real-Life Asynchronous Devices and Systems Alexander Taubin Boston University, USA Jordi Cortadella Universitat Polit`ecnica de Catalunya, Spain Luciano Lavagno Politecnico di Torino, Italy Alex Kondratyev Cadence Design Systems, USA Ad Peeters Handshake Solutions, The Netherlands Boston – Delft Full text available at: http://dx.doi.org/10.1561/1000000006 Foundations and Trends R in Electronic Design Automation Published, sold and distributed by: now Publishers Inc. PO Box 1024 Hanover, MA 02339 USA Tel. +1-781-985-4510 www.nowpublishers.com [email protected] Outside North America: now Publishers Inc. PO Box 179 2600 AD Delft The Netherlands Tel. +31-6-51115274 The preferred citation for this publication is A. Taubin, J. Cortadella, L. Lavagno, A. Kondratyev and A. Peeters, Design Automation of Real-Life Asynchronous Devices and Systems, Foundations and Trends R in Electronic Design Automation, vol 2, no 1, pp 1–133, 2007 ISBN: 978-1-60198-058-8 c 2007 A. Taubin, J. Cortadella, L. Lavagno, A. Kondratyev and A. Peeters All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, mechanical, photocopying, recording or otherwise, without prior written permission of the publishers. Photocopying. In the USA: This journal is registered at the Copyright Clearance Cen- ter, Inc., 222 Rosewood Drive, Danvers, MA 01923. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by now Publishers Inc for users registered with the Copyright Clearance Center (CCC). The ‘services’ for users can be found on the internet at: www.copyright.com For those organizations that have been granted a photocopy license, a separate system of payment has been arranged. Authorization does not extend to other kinds of copy- ing, such as that for general distribution, for advertising or promotional purposes, for creating new collective works, or for resale. In the rest of the world: Permission to pho- tocopy must be obtained from the copyright owner. Please apply to now Publishers Inc., PO Box 1024, Hanover, MA 02339, USA; Tel. +1-781-871-0245; www.nowpublishers.com; [email protected] now Publishers Inc. has an exclusive license to publish this material worldwide. Permission to use this content must be obtained from the copyright license holder. Please apply to now Publishers, PO Box 179, 2600 AD Delft, The Netherlands, www.nowpublishers.com; e-mail: [email protected] Full text available at: http://dx.doi.org/10.1561/1000000006 Foundations and Trends R in Electronic Design Automation Volume 2 Issue 1, 2007 Editorial Board Editor-in-Chief: Sharad Malik Department of Electrical Engineering Princeton University Princeton, NJ 08544 Editors Robert K. Brayton (UC Berkeley) Raul Camposano (Synopsys) K.T. Tim Cheng (UC Santa Barbara) Jason Cong (UCLA) Masahiro Fujita (University of Tokyo) Georges Gielen (KU Leuven) Tom Henzinger (EPFL) Andrew Kahng (UC San Diego) Andreas Kuehlmann (Cadence Berkeley Labs) Ralph Otten (TU Eindhoven) Joel Phillips (Cadence Berkeley Labs) Jonathan Rose (University of Toronto) Rob Rutenbar (CMU) Alberto Sangiovanni-Vincentelli (UC Berkeley) Leon Stok (IBM Research) Full text available at: http://dx.doi.org/10.1561/1000000006 Editorial Scope Foundations and Trends R in Electronic Design Automation will publish survey and tutorial articles in the following topics: • System Level Design • Physical Design • Behavioral Synthesis • Circuit Level Design • Logic Design • Reconfigurable Systems • Verification • Analog Design • Test Information for Librarians Foundations and Trends R in Electronic Design Automation, 2007, Volume 2, 4 issues. ISSN paper version 1551-3939. ISSN online version 1551-3947. Also available as a combined paper and online subscription. Full text available at: http://dx.doi.org/10.1561/1000000006 Foundations and Trends R in Electronic Design Automation Vol. 2, No. 1 (2007) 1–133 c 2007 A. Taubin, J. Cortadella, L. Lavagno, A. Kondratyev and A. Peeters DOI: 10.1561/1000000006 Design Automation of Real-Life Asynchronous Devices and Systems Alexander Taubin1, Jordi Cortadella2, Luciano Lavagno3, Alex Kondratyev4 and Ad Peeters5 1 Boston University, USA, [email protected] 2 Universitat Polit`ecnica de Catalunya, Spain, [email protected] 3 Politecnico di Torino, Italy, [email protected] 4 Cadence Design Systems, USA, [email protected] 5 Handshake Solutions, The Netherlands, [email protected] Abstract The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives. However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to the synchronous RTL-to-GDSII flow) for asynchronous circuits. Full text available at: http://dx.doi.org/10.1561/1000000006 The purpose of this paper is to counteract this view by presenting design flows that can tackle large designs without significant changes with respect to synchronous design flow. We are limiting ourselves to four design flows that we believe to be closest to this goal. We start from the Tangram flow, because it is the most commercially proven and it is one of the oldest from a methodological point of view. The other three flows (Null Convention Logic, de-synchronization, and gate-level pipelining) could be considered together as asynchronous re-implementations of synchronous (RTL- or gate-level) specifications. The main common idea is substituting the global clocks by local syn- chronizations. Their most important aspect is to open the possibility to implement large legacy synchronous designs in an almost “push but- ton” manner, where all asynchronous machinery is hidden, so that syn- chronous RTL designers do not need to be re-educated. These three flows offer a trade-off from very low overhead, almost synchronous implementations, to very high performance, extremely robust dual-rail pipelines. Full text available at: http://dx.doi.org/10.1561/1000000006 Contents 1 Introduction 1 1.1 Requirements for an Asynchronous Design Flow 1 1.2 Motivation for Asynchronous Approach 4 1.3 Asynchronous Design 7 1.4 An Overview of Asynchronous Design Styles 9 1.5 Asynchronous Design Flows 11 1.6 Paper Organization 16 2 Handshake Technology 19 2.1 Motivation 19 2.2 Functional Design 21 2.3 Design Language Haste 21 2.4 Handshake Circuits 29 2.5 Handshake Implementations 32 2.6 Library Connection 34 2.7 Simulation and Verification 35 2.8 Structural Design Flow 36 2.9 Physical Design 39 3 Synchronous-to-asynchronous RTL Flow Using NCL 43 3.1 Overview 43 ix Full text available at: http://dx.doi.org/10.1561/1000000006 3.2 Null Convention Logic 45 3.3 NCL Design Flow with HDL Tools 49 3.4 DIMS-based NCL Design Flow 51 3.5 NCL Flow with Explicit Completeness 53 3.6 Verification of NCL Circuits 55 4 De-synchronization: Simple Mutation Circuit into Asynchronous 63 4.1 Introduction 63 4.2 Signal Transition Graphs 64 4.3 Revisiting Synchronous Circuits 66 4.4 Relaxing the Synchronous Requirement 68 4.5 Minimum Requirements for Correct Asynchronous Communication 69 4.6 Handshake Protocols for De-synchronization 76 4.7 Implementation of Handshake Controllers 80 4.8 Design Flow 82 4.9 Why De-synchronize? 83 4.10 Conclusions 84 5 Automated Gate Level Pipelining (Weaver) 85 5.1 Automated Pipelining: Motivation 85 5.2 Automated Gate-Level Pipelining: General Approach 88 5.3 Micropipeline Stages: QDI Template 91 5.4 Design Flow Basics 92 5.5 Fine-Grain Pipelining with Registers 93 5.6 Pipeline Petri Net Model of the Flow 95 5.7 Weaving: Simple Examples 100 6 Applications and Success Stories 107 6.1 Low-Power Robust Design Using Haste 107 6.2 Low-Power Robust Design using De-synchronization 109 6.3 Design of Cryptographic Coprocessor 111 Full text available at: http://dx.doi.org/10.1561/1000000006 7 Conclusions 121 Acknowledgments 125 References 127 Full text available at: http://dx.doi.org/10.1561/1000000006 1 Introduction 1.1 Requirements for an Asynchronous Design Flow With the increases in die size and clock frequency, it has become increasingly difficult to drive signals across a die following a globally synchronous approach. Process variations and signal integrity stretch the timing margins in static timing analysis to the point where they become too conservative and result in significant over-design. Asyn- chronous circuits measure, rather than estimate, the delay of the combinational logic, of the wires, and of the memory elements. They operate reliably at very low voltages (even below the transistor thresh- old), when device characteristics exhibit second and third order effects. They do not require cycle-accurate specifications of the design, but can exploit specification concurrency virtually at every level of granular- ity. They can save power because they naturally perform computation on-demand. Asynchronous design also provides unique advantages, such as reduced electromagnetic emission, extremely aggressive pipelining for high performance, and improved security for cryptographic devices. In addition, asynchronous design might become a necessity for 1 Full text available at: http://dx.doi.org/10.1561/1000000006 2 Introduction non-standard future fabrication technologies, such as flexible electron- ics based on low-temperature poly-silicon TFT technology [50] or nano- computing [97].
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