15740\Off the Clock.Pdf

$15740\Off the Clock.Pdf$ Platforms.qxp:Tech Temp 22/10/08 16:31 Page 37 RESEARCH & DEVELOPMENT Advanced platforms Off the clock nvented 25 years ago by Xilinx, the Factor of three speed boost 90nm process. Our customers wanted Ifpga has evolved from being used as 1.5GHz at half the power. We’ve done this glue logic to its current role as the claimed for asynchronous and moved to a 65nm process; in fact, centrepiece of many designs. And there fpga architecture. we’ve been through two nodes in four are good reasons why the fpga is popular; months longer than we thought it would its reprogrammability being one. By Graham Pitcher. take to do one.” But John Lofton Holt, chairman and Rather than taking business away from chief executive of Achronix, doesn’t companies such as Altera and Xilinx, Holt believe the technology has evolved claims Achronix is creating a new market. particularly well. “Over the period, Infiniband. “In addition,” Kalilollahi “There’s a lot of people who are forced to process technology has improved by a continued, “we have to make sure the use structured asics or standard cell factor of 10, but the fpga is still limited at device has high performance memory and devices, but who want to use fpgas. But 500MHz.” this is provided through a DDR2/DDR3 they can’t get the speed from an fpga, so The problem, Holt contends, is clock PHY and controller.” have to fall back on asics and the huge distribution. “Designers have problems Holt expanded: “The serdes is key but NRE associated with them.” meeting timing closure,” he noted, “and there has been nothing fast enough for a He realises that, once an asic goes to an fpga’s power consumption rises with production, it won’t change. “So our clock speed.” targets are those introducing new His solution is an asynchronous design products or upgrading. But people using which, he claims, is the world’s fastest fpgas today may not have a road map they fpga and three times the speed of typical can use, so we will take some of that fpgas. “These devices are faster than business,” he asserted. fpgas available from Altera and “The most important differentiation Xilinx, as well as standard cell between our products and fpgas is that asics.” The technology is based we’re not different,” Holt believed. on an idea developed at “Because we use a silicon Cornell University. architecture, we can leverage Achronix has unveiled its decades of tools expertise.” asynchronous technology in Amongst the eda companies the form of the Speedster supporting Achronix are Synplify family, the first member of which and Mentor Graphics. is the SPD60. The device is Back end tools, called the targeted at communications Achronix CAD environment (ACE), applications and features an have been developed ‘from array of connectivity, scratch’, Holt noted. “But they underpinned by a 10.3Gbit/s have a familiar feel, with place serdes. According to Yousef and route, timing and debug Kalilollahi, vp of marketing, features.” this is a ‘very important’ element. “We don’t know of any Off the clock other fpga company with a 10Gbit Why is an asynchronous design so serdes.” attractive and why has such an The high speed serdes means the approach not been taken before? Holt SPD60 can offer a range of interfaces, said there had been attempts beforehand. including 100G Ethernet, XAUI and “But they were aimed at more aggressive www.newelectronics.co.uk 28 October 2008 37 Platforms.qxp:Tech Temp 22/10/08 16:31 Page 38 RESEARCH & DEVELOPMENT Advanced platforms targets and generally used ‘strange’ architecture uses a Each logic block is architectures.” handshaking surrounded by switch boxes, Achronix’ devices use the company’s protocol to move which route global signals picoPIPE acceleration technology to data through the across the fabric. speed data through the programmable fabric. Each logic block fabric. Denny Scharf, strategic marketing Scharf noted the contains eight four input manager, explained the architecture in process used data look up tables, storage more depth. “The picoPIPE fabric is tokens. “Bits are elements and 128bit of ram. surrounded by a frame. The frame propagated through Block ram and multipliers operates conventionally, with clocks the design. Whilst are included in the fabric. traditional fpgas need The fabric, meanwhile, is a clock to be generated capable of supporting any across the die, propagation in logic function. the picoPIPE architecture is determined In a traditional fpga by the downstream element signifying architecture (see figure 1), the globally that it has valid data and is ready to clocked logic is unbalanced and the receive.” device’s clock rate must account for the In conventional architectures, data is slowest path in the domain. According to only valid when a clock edge is received. Achronix, any combinatorial logic that is Data tokens in the Achronix architecture faster than the slowest path has to wait for can be viewed as a merging of data and the slowest one to finish. clock edge. It is this that allows the fabric In contrast, Achronix says its to run at high speed. architecture allows fine grained Data transfer is controlled by a local pipelining, which supports higher data rates. Pipelining also allows more data values in flight and an overall faster “Xilinx and Altera will have an easier time throughput. buying us than trying to compete.” The SPD60 is the first device in a planned family of four. The remaining John Lofton Holt, Achronix devices will appear over the next nine months, said Holt. For the future, he believes there are opportunities to be distributed around it. And no data gets handshake between two stages. “These more radical. “There are things we can do into the fabric or leaves it without stages are, effectively, 1bit fifos,” Scharf in the circuits themselves. We have been passing through the frame.” According to claimed, “which are either empty or full. conservative with this device to make sure Scharf, the frame consitutes around 13% It’s a ‘return to zero’ architecture to avoid it worked. We can now start to optimise of the die. glitches.” the architecture to squeeze more density.” But once data is in the programmable The picoPIPE fabric is formed from an Holt also claimed the architecture fabric, things are different. Because array of reconfigurable logic blocks could have been targeted at a 40nm there is not a global clock, the connected by a programmable fabric. process ‘two years ago’. “But there was no IP available. So this family will be on Figure 1: Speed through pipelining 65nm and we believe it will be good at this node for a number of years.” 0 0·67ns 1·3ns 2ns 2·7ns 3·3ns 4ns 4·7ns 5·3ns 6ns 6·7ns 7·3ns 8ns 8·7ns 9·3ns 10ns 10·7ns For the short term, Achronix’ target globally clocked logic cl will be asic replacement. “In our first design win, four Achronix fpgas work alongside a network processor and two 375MHz traditional DQ DQ DQ Altera Stratix III devices for logic,” Holt claimed. picoPIPE logic In the long term, Holt has lofty ambitions. “Xilinx and Altera will have an 1·5GHz Achronix easier time buying us than trying to compete,” he concluded. ■ 38 www.newelectronics.co.uk 28 October 2008.

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