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Implementing Balsa Handshake Circuits Implementing Balsa Handshake Circuits A thesis submitted to the University of Manchester for the degree of Doctor of Philosophy in the Faculty of Science & Engineering 2000 Andrew Bardsley Department of Computer Science 1 Contents Chapter 1. Introduction .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 12 1.1. Asynchronous design .. .. .. .. .. .. .. .. .. .. .. .. .. .. 13 1.1.1. The handshake .. .. .. .. .. .. .. .. .. .. .. .. .. 15 1.1.2. Delay models .. .. .. .. .. .. .. .. .. .. .. .. .. 19 1.1.3. Data encoding .. .. .. .. .. .. .. .. .. .. .. .. .. 22 1.1.4. The Muller C-element .. .. .. .. .. .. .. .. .. .. .. 25 1.1.5. The S-element .. .. .. .. .. .. .. .. .. .. .. .. .. 27 1.2. Thesis Structure .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 28 Chapter 2. Asynchronous Synthesis .. .. .. .. .. .. .. .. .. .. .. .. 30 2.1. Design flows for asynchronous synthesis .. .. .. .. .. .. .. .. 30 2.2. Directness and user intervention .. .. .. .. .. .. .. .. .. .. .. 32 2.3. Macromodules and DI interconnect .. .. .. .. .. .. .. .. .. .. 33 2.3.1. Sutherland’s micropipelines .. .. .. .. .. .. .. .. .. 34 2.3.2. Macromodules .. .. .. .. .. .. .. .. .. .. .. .. .. 39 2.3.3. Brunvand’s OCCAM synthesis .. .. .. .. .. .. .. .. 40 2.3.4. Plana’s pulse handshaking modules .. .. .. .. .. .. .. 40 2.4. Other asynchronous synthesis approaches .. .. .. .. .. .. .. .. 41 2.4.1. ‘Classical’asynchronous state machines .. .. .. .. .. .. 42 2.4.2. Petri-net synthesis .. .. .. .. .. .. .. .. .. .. .. .. 43 2.4.3. Burst-mode machines .. .. .. .. .. .. .. .. .. .. .. 46 2.4.4. Communicating Hardware Processes – CHP .. .. .. .. .. 48 2.4.5. NULL Conventional Logic – NCL .. .. .. .. .. .. .. 48 2.5. Chapter summary .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 50 Chapter 3. Handshake Circuits, Tangram and Balsa .. .. .. .. .. .. .. 51 3.1. Handshake circuits .. .. .. .. .. .. .. .. .. .. .. .. .. .. 51 3.2. The Balsa language .. .. .. .. .. .. .. .. .. .. .. .. .. .. 52 3.3. Handshake components, ports and channels .. .. .. .. .. .. .. 53 3.4. Notation .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 54 3.4.1. Term expansion .. .. .. .. .. .. .. .. .. .. .. .. 55 3.4.2. Data operations .. .. .. .. .. .. .. .. .. .. .. .. .. 58 3.5. Types of components .. .. .. .. .. .. .. .. .. .. .. .. .. .. 60 3.5.1. Activation driven control components .. .. .. .. .. .. 61 3.5.2. Control to datapath interface components .. .. .. .. .. 64 3.5.3. Pull datapath components .. .. .. .. .. .. .. .. .. .. 67 2 Contents 3.5.4. Connection components .. .. .. .. .. .. .. .. .. .. 70 3.6. Compiling into handshake circuits .. .. .. .. .. .. .. .. .. .. 76 3.7. Chapter summary .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 77 Chapter 4. The Balsa Back-end .. .. .. .. .. .. .. .. .. .. .. .. .. .. 78 4.1. The Balsa design flow .. .. .. .. .. .. .. .. .. .. .. .. .. 78 4.1.1. The Breeze handshake circuit netlist format .. .. .. .. .. 80 4.2. Handshake component generation – balsa-netlist .. .. .. .. .. .. 84 4.2.1. Handshake component templates – gen .. .. .. .. .. .. 84 4.2.2. Generic component decomposition – map1 .. .. .. .. .. 88 4.2.3. Target technology gate mapping – map2 .. .. .. .. .. .. 88 4.2.4. Netlist generation – net .. .. .. .. .. .. .. .. .. .. 89 4.2.5. Commercial CAD systems .. .. .. .. .. .. .. .. .. 89 4.3. Component implementations .. .. .. .. .. .. .. .. .. .. .. 91 4.4. Problems with this back-end .. .. .. .. .. .. .. .. .. .. .. .. 92 4.4.1. Signal drive strengths .. .. .. .. .. .. .. .. .. .. .. 92 4.4.2. Timing validation .. .. .. .. .. .. .. .. .. .. .. .. 93 4.5. Other new design flow features .. .. .. .. .. .. .. .. .. .. .. 94 4.5.1. LARD simulation – breeze2lard .. .. .. .. .. .. .. .. 94 4.5.2. New balsa-c features .. .. .. .. .. .. .. .. .. .. .. 100 4.5.3. Design management – balsa-md, balsa-mgr .. .. .. .. .. 104 4.6. Chapter summary .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 104 Chapter 5. New Handshake Components .. .. .. .. .. .. .. .. .. .. .. 105 5.1. The trouble with Balsa handshake circuits .. .. .. .. .. .. .. .. 105 5.1.1. Signal drive strength management .. .. .. .. .. .. .. 107 5.1.2. Control optimisation .. .. .. .. .. .. .. .. .. .. .. 108 5.1.3. Channel construction .. .. .. .. .. .. .. .. .. .. .. 108 5.1.4. Operations with individual signals .. .. .. .. .. .. .. 110 5.1.5. Datapath operations .. .. .. .. .. .. .. .. .. .. .. 111 5.2. New handshake components .. .. .. .. .. .. .. .. .. .. .. .. 113 5.2.1. PatchVariable .. .. .. .. .. .. .. .. .. .. .. .. .. 114 5.2.2. ControlTree .. .. .. .. .. .. .. .. .. .. .. .. .. .. 118 5.2.3. PassiveConnect, Connect .. .. .. .. .. .. .. .. .. .. 119 5.2.4. Encode .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 121 5.3. Chapter Summary .. .. .. .. .. .. .. .. .. .. .. .. .. .. 122 Chapter 6. The AMULET3i DMA Controller .. .. .. .. .. .. .. .. .. 124 6.1. Suitability of DMA controllers as Balsa examples .. .. .. .. .. .. 124 6.2. The AMULET microprocessors .. .. .. .. .. .. .. .. .. .. .. 125 Contents 3 Contents 6.3. AMULET3i and DRACO .. .. .. .. .. .. .. .. .. .. .. .. 126 6.4. The AMULET3i DMA controller .. .. .. .. .. .. .. .. .. .. 130 6.5. DMA controller requirements .. .. .. .. .. .. .. .. .. .. .. 131 6.6. The anatomy of a transfer .. .. .. .. .. .. .. .. .. .. .. .. 132 6.7. Handling DMA requests – the SPI .. .. .. .. .. .. .. .. .. .. 133 6.8. Accessing the registers .. .. .. .. .. .. .. .. .. .. .. .. .. 134 6.8.1. Single register bank access with locking .. .. .. .. .. .. 134 6.8.2. Two sequential register bank accesses .. .. .. .. .. .. 135 6.8.3. Two accesses with parallel write-back .. .. .. .. .. .. 136 6.8.4. The Initiator Interface .. .. .. .. .. .. .. .. .. .. .. 136 6.9. Structure and implementation .. .. .. .. .. .. .. .. .. .. .. 136 6.9.1. Controller structure .. .. .. .. .. .. .. .. .. .. .. 137 6.9.2. MARBLE bus interfaces .. .. .. .. .. .. .. .. .. .. 138 6.9.3. The regular SPI block .. .. .. .. .. .. .. .. .. .. .. 138 6.9.4. Standard cell datapath and control .. .. .. .. .. .. .. 139 6.9.5. Register blocks .. .. .. .. .. .. .. .. .. .. .. .. .. 139 6.10. Balsa control description .. .. .. .. .. .. .. .. .. .. .. .. 139 6.11. Controller performance .. .. .. .. .. .. .. .. .. .. .. .. .. 141 6.12. Chapter summary .. .. .. .. .. .. .. .. .. .. .. .. .. .. 141 Chapter 7. A Simplified DMA Controller .. .. .. .. .. .. .. .. .. .. .. 143 7.1. The simplified DMA controller .. .. .. .. .. .. .. .. .. .. .. 143 7.1.1. Global registers .. .. .. .. .. .. .. .. .. .. .. .. .. 144 7.1.2. Channel registers .. .. .. .. .. .. .. .. .. .. .. .. 145 7.1.3. DMA controller structure .. .. .. .. .. .. .. .. .. .. 146 7.2. The Balsa description .. .. .. .. .. .. .. .. .. .. .. .. .. 150 7.2.1. Arbiter tree .. .. .. .. .. .. .. .. .. .. .. .. .. .. 150 7.2.2. Transfer engine .. .. .. .. .. .. .. .. .. .. .. .. .. 151 7.2.3. Control unit .. .. .. .. .. .. .. .. .. .. .. .. .. .. 152 7.3. An implementation .. .. .. .. .. .. .. .. .. .. .. .. .. .. 157 7.3.1. Optimisation opportunities .. .. .. .. .. .. .. .. .. 159 7.3.2. The optimised implementation .. .. .. .. .. .. .. .. 160 7.4. Chapter Summary .. .. .. .. .. .. .. .. .. .. .. .. .. .. 161 Chapter 8. Conclusions .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 163 8.1. Future work .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 163 8.1.1. Improved datapath synthesis .. .. .. .. .. .. .. .. .. 164 8.1.2. Simulation and design management .. .. .. .. .. .. .. 164 8.1.3. Other work .. .. .. .. .. .. .. .. .. .. .. .. .. .. 165 Contents 4 Contents Appendix 1. Balsa Language Reference .. .. .. .. .. .. .. .. .. .. .. 166 1.1. Top level and declarations .. .. .. .. .. .. .. .. .. .. .. .. 166 1.2. Expressions, types, ranges and lvalues .. .. .. .. .. .. .. .. .. 168 1.3. Commands .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 170 1.4. Terminals and comments .. .. .. .. .. .. .. .. .. .. .. .. .. 173 Appendix 2. Simplified DMA Controller Source Code .. .. .. .. .. .. .. 174 2.1. ctrl.balsa .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 174 2.2. arb.balsa .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 177 2.3. dma.balsa .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 179 2.4. types.balsa .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 179 2.5. marble.balsa .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 181 2.6. te.balsa .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 181 References .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 183 Contents 5 List of Figures 1.1. 2-phase handshaking .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 16 1.2. 4-phase push handshaking .. .. .. .. .. .. .. .. .. .. .. .. .. .. 17 1.3. 2/4-phase pull handshaking .. .. .. .. .. .. .. .. .. .. .. .. .. .. 18 1.4. A latch using reduced broad push and pull protocols .. .. .. .. .. .. .. 19 1.5. The Muller C-element .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 26 1.6. The S-element .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 27 2.1. Typical synthesis design flow .. .. .. .. .. .. .. .. .. .. .. .. .. 31 2.2. Micropipeline elements .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 36 2.3. Decision-wait element and implementations .. .. .. .. .. .. .. .. .. 37 2.4. FIFOs with capture-pass and transparent latches .. .. .. .. .. .. .. .. 38 2.5. 2-way decision-wait petri-net .. .. .. .. .. .. .. .. .. .. .. .. .. 45 2.6. 2-input decision-wait burst-mode machine .. .. .. .. .. .. .. .. .. .. 47 2.7. NCL threshold gates .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 49 2.8. NCL hysteresis threshold gate adder .. .. .. .. .. .. .. .. .. .. .. .. 50 3.1.
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