Placing an FPGA on a Board Guidelines for Efficient Design
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Customer PPT Rev 30
LATTICE SEMICONDUCTOR The Leader in Low Power, Small Form Factor, Secure FPGAs First Quarter, 2019 Lattice Semiconductor (NASDAQ: LSCC) [1] Safe Harbor This presentation contains forward-looking statements that involve estimates, assumptions, risks and uncertainties, including all information under the heading 1Q 19 Business Outlook. Lattice believes the factors identified below could cause our actual results to differ materially from the forward-looking statements. Factors that may cause our actual results to differ materially from the forward-looking statements in this presentation include global economic uncertainty, overall semiconductor market conditions, market acceptance and demand for our new and existing products, the Company's dependencies on its silicon wafer suppliers, the impact of competitive products and pricing, and technological and product development risks. In addition, actual results are subject to other risks and uncertainties that relate more broadly to our overall business, including those risks more fully described in Lattice’s filings with the SEC including its annual report on Form 10-K for the fiscal year ended December 30, 2017 and its quarterly filings on Form 10-Q. Certain information in this presentation is identified as having been prepared on a non-GAAP basis. Management uses non- GAAP measures to better assess operating performance and to establish operational goals. Non-GAAP information should not be viewed by investors as a substitute for data prepared in accordance with GAAP. You should not unduly rely on forward-looking statements because actual results could differ materially from those expressed in any forward- looking statements. In addition, any forward-looking statement applies only as of the date on which it is made. -
FPGA Design Security Issues: Using the Ispxpga® Family of Fpgas to Achieve High Design Security
White Paper FPGA Design Security Issues: Using the ispXPGA® Family of FPGAs to Achieve High Design Security December 2003 5555 Northeast Moore Court Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 FAX: (503) 268-8556 www.latticesemi.com WP1010 Using the ispXPGA Family of FPGAs to Lattice Semiconductor Achieve High Design Security Introduction In today’s complex systems, FPGAs are increasingly being used to replace functions traditionally performed by ASICs and even microprocessors. Ten years ago, the FPGA was at the fringe of most designs; today it is often at the heart. With FPGA technology taking gate counts into the millions, a trend accelerated by embedded ASIC-like functionality, the functions performed by the FPGA make an increasingly attractive target for piracy. Many tech- niques have been developed over the years to steal designs from all types of silicon chips. Special considerations must now be made when thinking about protecting valuable Intellectual Property (IP) implemented within the FPGA. The most common FPGA technology in use today is SRAM-based, which is fast and re-configurable, but must be re-configured every time the FPGA is powered up. Typically, an external PROM is used to hold the configuration data for the FPGA. The link between the PROM and FPGA represents a significant security risk. The configuration data is exposed and vulnerable to piracy while the device powers up. Using a non-volatile-based FPGA eliminates this security risk. Traditionally, non-volatile FPGAs were based on Antifuse technology that is secure, but very expensive to use due to its one-time programmability and higher manufacturing costs. -
Software-Defined Hardware Provides the Key to High-Performance Data
Software-Defined Hardware Provides the Key to High-Performance Data Acceleration (WP019) Software-Defined Hardware Provides the Key to High- Performance Data Acceleration (WP019) November 13, 2019 White Paper Executive Summary Across a wide range of industries, data acceleration is the key to building efficient, smart systems. Traditional general-purpose processors are falling short in their ability to support the performance and latency constraints that users have. A number of accelerator technologies have appeared to fill the gap that are based on custom silicon, graphics processors or dynamically reconfigurable hardware, but the key to their success is their ability to integrate into an environment where high throughput, low latency and ease of development are paramount requirements. A board-level platform developed jointly by Achronix and BittWare has been optimized for these applications, providing developers with a rapid path to deployment for high-throughput data acceleration. A Growing Demand for Distributed Acceleration There is a massive thirst for performance to power a diverse range of applications in both cloud and edge computing. To satisfy this demand, operators of data centers, network hubs and edge-computing sites are turning to the technology of customized accelerators. Accelerators are a practical response to the challenges faced by users with a need for high-performance computing platforms who can no longer count on traditional general-purpose CPUs, such as those in the Intel Xeon family, to support the growth in demand for data throughput. The core of the problem with the general- purpose CPU is that Moore's Law continues to double the number of available transistors per square millimeter approximately every two years but no longer allows for growth in clock speeds. -
Handoutshandouts
HandoutsHandouts FPGA-related documents 1. Introduction to Verilog, P. M. Nyasulu and J. Knight, Carleton University, 2003 (Ottawa, Canada). 2. Quick Reference for Verilog HDL, R. Madhavan, AMBIT Design Systems, Inc, Automata Publishing Company, 1995 (San Jose, CA). Project-related documents 3. Project Guidelines and Project Specifications. (I’ll hand these out in lab) IntroductionIntroduction toto FPGAsFPGAs Outline: 1. What’s an FPGA ? Æ logic element “fabric”, i.e. logic gates + memory + clock trigger handling. 2. What’s so good about FPGAs ? Æ FPGA applications and capabilities Æ FPGAs for physicists 3. How do you program an FPGA ? Æ Intro to Quartus II Æ Schematic design Æ Verilog HDL design WhatWhat’’ss anan FPGAFPGA An FPGA is: - a Field Programmable Gate Array. - a programmable breadboard for digital circuits on chip. The FPGA consists of: - programmable Logic Elements (LEs). - programmable interconnects. - custom circuitry (i.e. multipliers, phase- lock loops (PLL), memory, etc …). Programmable Programmable Interconnects Logic [Figure adapted from Low Energy FPGAs – Architecture and Design, by V. George and J. M. Rabaey, Kluwer Academic Publishers, Boston (2001).] LogicLogic ElementElement (LE)(LE) An FPGA consists of a giant array of interconnected logic elements (LEs). The LEs are identical and consist of inputs, a Look-Up Table (LUT), a little bit of memory, some clock trigger handling circuitry, and output wires. global LUTLUT inputs inputs outputs local outputs MemoryMemory local clock (a few bits) CLOCK triggers signals feedback Figure: Architecture of a single Logic Element InterconnectInterconnect ArchitecturesArchitectures Row-Column Architecture Island Style Architecture Sea-of-Gates Architecture Hierarchical Architecture FPGAFPGA devicesdevices (I)(I) 2 primary manufacturers: 1. -
FPGA Design Guide
FPGA Design Guide Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 (503) 268-8000 September 16, 2008 Copyright Copyright © 2008 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine- readable form without prior written consent from Lattice Semiconductor Corporation. Trademarks Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), LSC, E2CMOS, Extreme Performance, FlashBAK, flexiFlash, flexiMAC, flexiPCS, FreedomChip, GAL, GDX, Generic Array Logic, HDL Explorer, IPexpress, ISP, ispATE, ispClock, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2, ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH, ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP, ispXPGA, ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2, LatticeECP2M, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, MACH, MachXO, MACO, ORCA, PAC, PAC-Designer, PAL, Performance Analyst, PURESPEED, Reveal, Silicon Forest, Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The Simple Machine for Complex Design, TransFR, UltraMOS, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. ISP, Bringing the Best Together, and More -
FPGA Configuration Flash Memory AT17F32
Features • Programmable 33,554,432 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) • 3.3V Output Capability • 5V Tolerant I/O Pins • Program Support using the Atmel ATDH2200E System or Industry Third Party Programmers • In-System Programmable (ISP) via 2-wire Bus • Simple Interface to SRAM FPGAs • Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, APEX™ Devices, FPGA Stratix™, Lattice Semiconductor® (ORCA®) FPGAs, Spartan®, Virtex™ FPGAs • Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Configuration • Low-power CMOS FLASH Process • Available in 44-lead PLCC Package Flash Memory • Emulation of Atmel’s AT24CXXX Serial EEPROMs • Low-power Standby Mode • Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System AT17F32 Reconfiguration • Fast Serial Download Speeds up to 33 MHz • Endurance: 10,000 Write Cycles Typical • LHF Package Available (Lead and Halide Free) 1. Description The AT17F Series of In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17F Series device is packaged in the 44-lead PLCC, see Table 1- 1. The AT17F Series Configurator uses a simple serial-access procedure to configure one or more FPGA devices. The AT17F Series Configurators can be programmed with industry-standard program- mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. Table 1-1. AT17F Series Packages Package AT17F32 44-lead PLCC Yes 3393C–CNFG–6/05 2. Pin Configuration 44-lead PLCC NC CLK NC NC DATA PAGE_EN VCC NC NC SER_EN NC 6 5 4 3 2 1 NC 7 44 43 42 41 3940 NC NC 8 38 NC NC 9 37 NC NC 10 36 NC NC 11 35 NC NC 12 34 NC NC 13 33 NC NC 14 32 NC NC 15 31 NC NC 16 30 NC NC 17 29 READY 18 19 20 21 22 23 24 25 26 27 28 CE NC NC NC NC NC GND CEO/A2 RESET/OE PAGESEL0 PAGESEL1 2 AT17F32 3393C–CNFG–6/05 AT17F32 3. -
In Re: Lattice Semiconductor Corporation Securities Litigation 04
LERACH COUGHLIN STOIA GELLER RUDMAN & ROBBINS LLP WILLIAM S. LERACH [email protected] DARREN J. ROBBINS [email protected] 401 B Street, Suite 1600 San Diego, CA 92101 Telephone: 619/231-1058 619/231-7423 (fax) DENNIS J. HERMAN [email protected] 100 Pine Street, Suite 2600 San Francisco, CA 94111 Telephone: 415/288-4545 415/288-4534 (fax) TAMARA J. DRISCOLL [email protected] 700 Fifth Avenue, Suite 5600 Seattle, WA 98104 Telephone: 206/749-5544 206/749-9978 (fax) Lead Counsel for Plaintiffs [Additional counsel appear on signature page.] UNITED STATES DISTRICT COURT DISTRICT OF OREGON In re LATTICE SEMICONDUCTOR CORP. CV-04-01255-HU (Consolidated Cases) SECURITIES LITIGATION CLASS ACTION This Document Relates To: CONSOLIDATED CLASS ACTION ALL ACTIONS. COMPLAINT FOR VIOLATION OF THE FEDERAL SECURITIES LAWS [Caption continued on following page.] DEMAND FOR JURY TRIAL CONSOLIDATED CLASS ACTION COMPLAINT FOR VIOLATION OF THE FEDERAL SECURITIES LAWS AUTUMN PARTNERS, LLC, Individually Case No. CV-04-01255-HU and On Behalf of Itself and All Others Similarly Situated, CLASS ACTION Plaintiff, vs. LATTICE SEMICONDUCTOR CORP., CYRUS Y. TSUI, STEPHEN A. SKAGGS, STEVEN A. LAUB and RONALD HOYT, Defendants. CONSOLIDATED CLASS ACTION COMPLAINT FOR VIOLATION OF THE FEDERAL SECURITIES LAWS TABLE OF CONTENTS Page I. INTRODUCTION............................................................................................................... 1 II. JURISDICTION AND VENUE..........................................................................................6 -
Opencapi, Gen-Z, CCIX: Technology Overview, Trends, and Alignments
OpenCAPI, Gen-Z, CCIX: Technology Overview, Trends, and Alignments BRAD BENTON| AUGUST 8, 2017 Agenda 2 | OpenSHMEM Workshop | August 8, 2017 AGENDA Overview and motivation for new system interconnects Technical overview of the new, proposed technologies Emerging trends Paths to convergence? 3 | OpenSHMEM Workshop | August 8, 2017 Overview and Motivation 4 | OpenSHMEM Workshop | August 8, 2017 NEWLY EMERGING BUS/INTERCONNECT STANDARDS Three new bus/interconnect standards announced in 2016 CCIX: Cache Coherent Interconnect for Accelerators ‒ Formed May, 2016 ‒ Founding members include: AMD, ARM, Huawei, IBM, Mellanox, Xilinx ‒ ccixconsortium.com Gen-Z ‒ Formed August, 2016 ‒ Founding members include: AMD, ARM, Cray, Dell EMC, HPE, IBM, Mellanox, Micron, Xilinx ‒ genzconsortium.org OpenCAPI: Open Coherent Accelerator Processor Interface ‒ Formed September, 2016 ‒ Founding members include: AMD, Google, IBM, Mellanox, Micron ‒ opencapi.org 5 5 | OpenSHMEM Workshop | August 8, 2017 NEWLY EMERGING BUS/INTERCONNECT STANDARDS Motivations for these new standards Tighter coupling between processors and accelerators (GPUs, FPGAs, etc.) ‒ unified, virtual memory address space ‒ reduce data movement and avoid data copies to/from accelerators ‒ enables sharing of pointer-based data structures w/o the need for deep copies Open, non-proprietary standards-based solutions Higher bandwidth solutions ‒ 25Gbs and above vs. 16Gbs forPCIe-Gen4 Better exploitation of new and emerging memory/storage technologies ‒ NVMe ‒ Storage class memory (SCM), -
Program & Exhibits Guide
FROM CHIPS TO SYSTEMS – LEARN TODAY, CREATE TOMORROW CONFERENCE PROGRAM & EXHIBITS GUIDE JUNE 24-28, 2018 | SAN FRANCISCO, CA | MOSCONE CENTER WEST Mark You Calendar! DAC IS IN LAS VEGAS IN 2019! MACHINE IP LEARNING ESS & AUTO DESIGN SECURITY EDA IoT FROM CHIPS TO SYSTEMS – LEARN TODAY, CREATE TOMORROW JUNE 2-6, 2019 LAS VEGAS CONVENTION CENTER LAS VEGAS, NV DAC.COM DAC.COM #55DAC GET THE DAC APP! Fusion Technology Transforms DOWNLOAD FOR FREE! the RTL-to-GDSII Flow GET THE LATEST INFORMATION • Fusion of Best-in-Class Optimization and Industry-golden Signoff Tools RIGHT WHEN YOU NEED IT. • Unique Fusion Data Model for Both Logical and Physical Representation DAC.COM • Best Full-flow Quality-of-Results and Fastest Time-to-Results MONDAY SPECIAL EVENT: RTL-to-GDSII Fusion Technology • Search the Lunch at the Marriott Technical Program • Find Exhibitors www.synopsys.com/fusion • Create Your Personalized Schedule Visit DAC.com for more details and to download the FREE app! GENERAL CHAIR’S WELCOME Dear Colleagues, be able to visit over 175 exhibitors and our popular DAC Welcome to the 55th Design Automation Pavilion. #55DAC’s exhibition halls bring attendees several Conference! new areas/activities: It is great to have you join us in San • Design Infrastructure Alley is for professionals Francisco, one of the most beautiful who manage the HW and SW products and services cities in the world and now an information required by design teams. It houses a dedicated technology capital (it’s also the city that Design-on-Cloud Pavilion featuring presentations my son is named after). -
International Standard
This preview is downloaded from www.sis.se. Buy the entire standard via https://www.sis.se/std-8023417 IEC 62680-1-2 ® Edition 1.0 2016-11 INTERNATIONAL STANDARD colour inside Universal serial bus interfaces for data and power – Part 1-2: Common components – USB Power Delivery specification ) en ( 11 - 6 :201 2 - 1 - 62680 IEC Copyright © IEC, 2016, Geneva, Switzerland. All rights reserved. Sold by SIS under license from IEC and SEK. No part of this document may be copied, reproduced or distributed in any form without the prior written consent of the IEC. This preview is downloaded from www.sis.se. Buy the entire standard via https://www.sis.se/std-8023417 THIS PUBLICATION IS COPYRIGHT PROTECTED Copyright © 2016 IEC, Geneva, Switzerland All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from either IEC or IEC's member National Committee in the country of the requester. If you have any questions about IEC copyright or have an enquiry about obtaining additional rights to this publication, please contact the address below or your local IEC member National Committee for further information. IEC Central Office Tel.: +41 22 919 02 11 3, rue de Varembé Fax: +41 22 919 03 00 CH-1211 Geneva 20 [email protected] Switzerland www.iec.ch About the IEC The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes International Standards for all electrical, electronic and related technologies. -
Migrating to Achronix FPGA Technology (AN023) Migrating to Achronix FPGA Technology (AN023)
Migrating to Achronix FPGA Technology (AN023) Migrating to Achronix FPGA Technology (AN023) November 19, 2020 Application Note Introduction Many users transitioning to Achronix FPGA technology will be familiar with existing FPGA solutions from other vendors. Although Achronix technology and tools are very similar to existing FPGA technology and tools, there are some differences. Understanding these differences are needed to achieve the very best performance and quality of results (QoR). This application note discusses any differences in the Achronix tool flow, highlighting key files and methodologies that users may not be familiar with. Further this application note details the primitive components present in the Achronix fabric, and how they may differ from, or in many cases are similar to, other vendors. Finally this application note reviews the unique features, particularly focused on AI and ML workloads that are present in the Achronix FPGA devices. Related Documents This application note is intended to give an overview of any changes that a user may encounter when migrating to Achronix technology. For full details of any of the items described below, the user is directed to the appropriate user guide or application note. Instead of duplicating information, this application note highlights the changes, and refers the user to the appropriate user guide where they can obtain the full information. A number of user guides are commonly referred to throughout this document Speedster7t IP Component Library User Guide (UG086) .This user guide describes all the silicon elements on the Speedster7t family. It includes descriptions, and instantiation templates, of the memories, DSP, MLP, NAP and logic primitives. -
Transistor-Level Programmable Fabric
TRANSISTOR-LEVEL PROGRAMMABLE FABRIC by Jingxiang Tian APPROVED BY SUPERVISORY COMMITTEE: ___________________________________________ Carl Sechen, Chair ___________________________________________ Yiorgos Makris, Co-Chair ___________________________________________ Benjamin Carrion Schaefer ___________________________________________ William Swartz Copyright 2019 Jingxiang Tian All Rights Reserve TRANSISTOR-LEVEL PROGRAMMABLE FABRIC by JINGXIANG TIAN, BS DISSERTATION Presented to the Faculty of The University of Texas at Dallas in Partial Fulfillment of the Requirements for the Degree of DOCTOR OF PHILOSOPHY IN ELECTRICAL ENGINEERING THE UNIVERSITY OF TEXAS AT DALLAS December 2019 ACKNOWLEDGMENTS I would like to express my deep sense of gratitude to the consistent and dedicated support of my advisor, Dr. Carl Sechen, throughout my entire PhD study. You have been a great mentor, and your help in my research and career is beyond measure. I sincerely thank my co-advisor, Dr. Yiorgos Makris, who brings ideas and funds for this project. I am grateful that they made it possible for me to work on this amazing research topic that is of great interest to me. I would also like to thank my committee members, Dr. Benjamin Schaefer and Dr. William Swartz for serving as my committee members and giving lots of advice on my research. I would like to give my special thanks to the tech support staff, Steve Martindell, who patiently helped me a thousand times if not more. With the help of so many people, I have become who I am. My parents and my parents-in-law give me tremendous support. My husband, Tianshi Xie, always stands by my side when I am facing challenges. Ada, my precious little gift, is the motivation and faith for me to keep moving on.