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FPGA Design Guide FPGA Design Guide Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 (503) 268-8000 September 16, 2008 Copyright Copyright © 2008 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine- readable form without prior written consent from Lattice Semiconductor Corporation. Trademarks Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), LSC, E2CMOS, Extreme Performance, FlashBAK, flexiFlash, flexiMAC, flexiPCS, FreedomChip, GAL, GDX, Generic Array Logic, HDL Explorer, IPexpress, ISP, ispATE, ispClock, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2, ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH, ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP, ispXPGA, ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2, LatticeECP2M, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, MACH, MachXO, MACO, ORCA, PAC, PAC-Designer, PAL, Performance Analyst, PURESPEED, Reveal, Silicon Forest, Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The Simple Machine for Complex Design, TransFR, UltraMOS, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. ISP, Bringing the Best Together, and More of the Best are service marks of Lattice Semiconductor Corporation. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium in the U.S. and other jurisdictions. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Disclaimers NO WARRANTIES: THE INFORMATION PROVIDED IN THIS DOCUMENT IS “AS IS” WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND INCLUDING WARRANTIES OF ACCURACY, COMPLETENESS, MERCHANTABILITY, NONINFRINGEMENT OF INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL LATTICE SEMICONDUCTOR CORPORATION (LSC) OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER (WHETHER DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL, INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY TO USE THE INFORMATION PROVIDED IN THIS DOCUMENT, EVEN IF LSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION OR LIMITATION OF CERTAIN LIABILITY, SOME OF THE ABOVE LIMITATIONS MAY NOT APPLY TO YOU. LSC may make changes to these materials, specifications, or information, or to the products described herein, at any time without notice. LSC makes no commitment to update this documentation. LSC reserves the right to discontinue any product or service without notice and assumes no obligation FPGA Design Guide ii to correct any errors contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current. Type Conventions Used in This Document Convention Meaning or Use Bold Items in the user interface that you select or click. Text that you type into the user interface. <Italic> Variables in commands, code syntax, and path names. Ctrl+L Press the two keys at the same time. Courier Code examples. Messages, reports, and prompts from the software. ... Omitted material in a line of code. Omitted lines in code and report examples. [ ] Optional items in syntax descriptions. In bus specifications, the brackets are required. ( ) Grouped items in syntax descriptions. { } Repeatable items in syntax descriptions. | A choice between items in syntax descriptions. FPGA Design Guide iii FPGA Design Guide iv Contents Chapter 1 Introduction 1 Chapter 2 Moving Designs from Altera 3 Conversion Guidelines 3 Converting Design Constraints 4 Converting Memory Blocks 7 Converting PLL Blocks 9 Converting DDR Interfaces 11 Chapter 3 Moving Designs from Xilinx 13 Migrating Xilinx Spartan Designs to LatticeECP/EC 14 Replacing Commonly Used Xilinx Primitives 14 Replacing DCM/DLL Elements 17 Comparing Xilinx and Lattice Semiconductor Block Memory 18 Xilinx Multiplier Versus the Lattice Semiconductor DSP Block 22 Converting DDR Interfaces 23 Replacing Constraints 24 Converting Xilinx Virtex II to LatticeECP/EC Devices 27 Converting Xilinx DLL to Lattice Semiconductor PLL 27 Creating MUXCY and MUXCY_L Verilog HDL Modules 28 Wide Multiplexing 28 Optimal Carry-Chain Handling 28 Converting Xilinx RAMB16_S36_S36 to Verilog HDL 29 Converting DDR Interfaces 31 Chapter 4 Incremental and Modular Design Methods 33 Necessity and Benefits 33 Typical Work Flow and Data Flow 34 Major Advantages 35 Incremental Changes 36 Identify Design Candidates 36 FPGA Design Guide v Contents Block Modular Design Flow 37 Logic Partitioning 38 Partitioning Guidelines 38 Directory Structure 39 Device Floorplanning 39 Top-Level Floorplanning Procedures 39 Taking Architectures into Account 40 Block-Level Implementation 40 Top-Level Assembly 41 Simulation Scenarios 41 Incremental Design Methods 42 Design Example 43 Logic Partitions and Data Flow 43 Floorplan Sketch 44 Flat Implementation 45 Submodule Floorplan 46 I/O Connectivity 46 Critical Paths 48 Sample Design Implementation 49 Conclusion 49 Related Documentation 50 Chapter 5 Logic Synthesis Guidelines 51 Synthesis Design Flow and Guidelines 51 Reports Produced by Synthesis 54 Related Documentation 55 Chapter 6 HDL Synthesis Coding Guidelines 57 General HDL Practices 58 Hierarchical Coding 58 Design Partitioning 59 Design Registering 61 Comparing If-Then-Else and Case Statements 62 Avoiding Unintentional Latches 63 Register Control Signals 64 Clock Enable 65 Local Asynchronous and Synchronous Sets and Resets 67 Multiplexers 68 Finite State Machine Guidelines 69 State Encoding Methods for State Machines 69 Coding Styles for State Machines 71 HDL Coding for Distributed and Block Memory 75 Synthesis Control of High-Fan-Out Nets 76 Bidirectional Buffers 77 Coding to Avoid Simulation/Synthesis Mismatches 79 Sensitivity Lists 80 Blocking/Nonblocking Assignments in Verilog 80 Synthesis Pragmas: full_case/parallel_case 82 Signal Fanout 83 FPGA Design Guide vi Contents References 83 Chapter 7 Attributes and Preferences for FPGA Designs 85 About Attributes 86 ispLEVER Attributes 86 Vendor Attributes 86 About Compiler Directives 87 Using Attributes and Compiler Directives in HDL 87 sysIO Buffer Constraints 87 I/O Buffer Insertion 87 I/O Buffer Configuration 89 Overriding Default I/O Buffer Type 90 Locking I/O Pins 91 Optimization Constraints 92 Black-Box Module Instances 92 Preserving Signals 96 Floorplanning Constraints 97 Locating a Block to a Device Site 98 Grouping Logic 99 Group Bounding Boxes and Anchors 105 Regional Groups 106 Register-Oriented Groups (Synplify Only) 107 Related Documentation 109 Chapter 8 Synthesis Tips for Higher Performance 111 Register Balancing and Pipelining 112 Retiming 112 Pipelining 112 Using Dedicated Resource GSR for fMAX Improvement 116 Instantiating Dedicated Resource GSR in RTL Code 116 Improving Timing Through the I/O Register 116 Example Coded in Precision RTL Synthesis 117 Examples Coded in Synplify 119 Adding Delays to Input Registers 121 Examples Coded in Precision RTL Synthesis 121 Examples Coded in Synplify 123 Maximum Fan-Out Control for fMAX Improvement 124 Examples Coded in Synplify 125 Examples Coded in Precision RTL Synthesis 125 Clock-Enable Control for fMAX Improvement 126 Examples Coded in Synplify 126 Examples Coded in Precision RTL Synthesis 127 General Constraint Considerations 127 Block-Level Synthesis Methods in Synplify 128 Block-Level Synthesis Methods in Precision RTL Synthesis 128 Turning Off Mapping DSP Multipliers in RTL 129 Examples Coded with Synplify 129 Examples Coded with Precision RTL Synthesis 131 Achieving Improved Synthesis Results by Assigning Black-Box Timing to Large Embedded Blocks 132 FPGA Design Guide vii Contents Chapter 9 Strategies for Timing Closure 135 Seven Steps to Timing Closure 135 Constraining Designs 136 Logical Preference File (.lpf) 136 How ispLEVER Uses the Logical Preference File 138 Creating and Editing Preferences 140 Preference Editing Tools 142 Preference Flow 144 General Strategy Guidelines 145 Adding and Modifying Timing Preferences 145 Typical Design Preferences 146 Proper Preferences 147 Translating Board Requirements into FPGA Preferences 148 Using the Place and Route Software (PAR) 151 Placement 151 Routing 151 Timing-Driven PAR Process 152 Performing Static Timing Analysis 152 Why Perform Static Timing Analysis? 153 Analyzing Timing Reports Produced by TRACE 154 Timing Exceptions 155 Controlling Placement and Routing 165 Running Multiple Routing Passes 165 Using Multiple Placement Iterations (Cost Tables) 167 Re-Entrant Routing 169 Clock Boosting 169 Map Register Retiming 172 Map Register Retiming vs. Clock Boosting 172 Floorplanning the Design 173 Floorplanning Definition 173 Complex FPGA Design Management 173 Floorplanning Design Flow 173 When to Floorplan 174 Floorplanning Preferences 176 Implementation of Floorplan Preferences 179 Setting Group Preferences in the Design Planner 187 Using the Design Planner Interface 192 Design Performance Enhancement Strategies 193
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