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Latticemico8 Soft Core 8-Bit Microcontroller Optimized for Lattice Programmable Devices

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Latticemico8 Soft Core 8-Bit Microcontroller Optimized for Lattice Programmable Devices O P E N S O U R C E S O F T C O R E M I C R O C ont R O LL E R LatticeMico8 Soft Core 8-Bit Microcontroller Optimized for Lattice Programmable Devices The LatticeMico8™ is an 8-bit “soft” microcontroller core for the LatticeECP™, LatticeEC™ and LatticeXP™ families of Field Programmable Gate Arrays (FPGAs), as well as the MachXO™ family of Crossover Programmable Logic Devices. Combining a full 18-bit wide instruction set with 32 general purpose registers, the LatticeMico8 is a flexible reference design suitable for a wide variety of markets, including com- munications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configu- ration, while maintaining a broad feature set. In order to encourage user experimentation, development and contributions, Lattice is providing a new open intellec- tual property (IP) core license, the first such license offered Key Features and Benefits by any FPGA supplier. The license applies many of the concepts of the successful open source movement to IP cores Optimized for LatticeECP, LatticeEC, LatticeXP, and MachXO Families targeted for programmable logic applications. Efficient Architecture – Utilizes <200 LUTs Broad Feature Set LatticeMico8 Block Diagram • 8-bit data path • 18-bit wide instructions • 32 general purpose registers 16 Deep Call Stack • 32 bytes of internal scratch pad memory Program Interrupt Ack • Input/Output is performed using ports (up to 256 port Address Program Flow Control & PC Flags numbers) CY, Z • Optional 256 bytes of external scratch pad RAM Interrupt • Two cycles per instruction Easily Modified to Meet Specific Application Needs rd Lattice UART Reference Design Peripheral rb Register File 32 (8 Bit) Parameterized for Easy Implementation of Four Stan- Registers dard Configurations Microcontroller and Development Tools Released in Arithmetic Open Source Format Logic Unit (ALU) • LatticeMico8 source code in Verilog or VHDL • LatticeMico8 assembler Program Instr • LatticeMico8 instruction set simulator Memory 17:0 Internal (EBR) 32 Byte Innovative Open IP Core License Scratch Pad • Allows users to modify the core and share Memory modifications • Freely distribute hardware (FPGAs) without license ALU Op • Migrate designs to another FPGA or ASIC Excellent Solution for a Wide Variety of Applications Optional • Consumer • Computation External To Scratch Pad I/O Port • Communications (Up to 256 Bytes) • Medical From • Industrial www.latticesemi.com/mico8 I/O Port • Automotive Download the LatticeMico8 reference design today! L A tt IC E : B R I N GI N G T H E best to G et H E R Open IP Core Licensing LatticeMico8 Instruction Set The main benefits of using open source IP are greater flexibility, Bitwise Logic Operations AND, ANDI, OR, ORI, XOR, XORI improved portability, and no cost. Specifically, open source IP ADD, ADDI, ADDC, ADDCI, SUB, SUBI, is available and open for everyone, meaning that designers can Arithmetic Operations SUBC, SUBCI review it and make enhancements and improvements to the IP. Since the entire user community helps to identify problem Compare Operations CMP, CMPI, TEST, TESTI areas and to develop solutions, the open source IP core tends to Flag Changing Operations SETI, CLRI, SETC, CLRC, SETZ, CLRZ be more reliable. Another benefit is that a user has architecture Rotate Instructions ROR, RORC, ROL, ROLC independence, meaning that an open source IP core can be used in any FPGA or even migrated to an ASIC for higher volume, Move Operations MOV, MOVI mature designs. Finally, and the most commonly associated Branch Operations B, BZ, BNZ, BC, BNC benefit of open source IP, is the fact that it is free of charge. Call Operations CALL, CALLZ, CALLNZ, CALLC, CALLNC Standard open source IP licensing do have some restrictions that Memory Operations LSP, LSPI, SSP, SSPI can be a stumbling block. Many licenses require the publication of the entire FPGA design as open source if a license block is I/O Operations IMPORT, IMPORTI, EXPORT, EXPORTI used. Other licenses typically require providing a copy of the li- cense with the derived work. Not only can this be inconvenient, Assembler but it is also impractical. As a result, standard open source The LatticeMico8 Assembler was developed in C and is provided licensing has restrictions that are unsuitable and may limit the as an easy-to-use compiler. The Assembler compiles a text as- ability to keep a design proprietary. sembler input file and generates an Embedded Block RAM (EBR) initialization file. Assembler output options include: Lattice solves these problems with a unique open IP core • Hexadecimal output file (for use with Lattice IPexpress™) licensing agreement. The agreement provides all the benefits • Binary output file (for use with Lattice IPexpress) of standard open source and allows users to mix proprietary • Verilog initialization file (included in design prior to designs with the open source core. Additionally, it allows for synthesis) the distribution of designs in bitstream or FPGA format without In addition to these outputs, the Assembler can also generate an accompanying it with a copy of the license. assembler listing file. Flexible Configurations Instruction Set Simulator The LatticeMico8 microcontroller offers superior design flex- Lattice offers an Instruction Set Simulator for the LatticeMico8 ibility. LatticeMico8 is parameterized to allow the easy imple- microcontroller. As with the Assembler, the Simulator was de- mentation of four standard configurations, each optimized for veloped using C. The Instruction Set Simulator allows programs different user needs. With available external scratch pad RAM, developed for the LatticeMico8 to be run and debugged on a more memory, and up to 32 registers, the LatticeMico8 delivers a host platform. The Simulator can also be used to generate a dis- flexible solution with plenty of resources. assembly listing of a program. The Simulator takes as input the Four Standard Configurations memory output file of the Assembler and emulates the instruc- tion execution of the LatticeMico8 in software. Configuration ispLEVER Development Tools Resource 1 2 3 4 LatticeMico8 soft core microcontrollers Registers 16 32 32 32 are supported by Lattice’s ispLEVER® Internal RAM Scratch Pad 16 16 32 32 development tools. ispLEVER tools offer a comprehensive design environment for External RAM Scratch Pad No No No Yes the Lattice FPGA, CPLD, FPSC and SPLD Resource Utilization families. ispLEVER tools include everything you need for design entry, synthesis, map, Configuration FPGA fMAX (MHz) LUTs Registers place & route, floorplanning, simulation, LFXP3C-4 71.4 project management, device programming 1 198 71 LFEC3E-4 77.1 and more. Synthesis and simulation tools LFXP3C-4 62.4 from industry leaders Mentor Graphics and 2 247 71 LFEC3E-4 68.8 Synplicity are included with ispLEVER. LFXP3C-4 63.4 3 243 71 LFEC3E-4 70.0 LFXP3C-4 62.3 4 275 73 Applications Support LFEC3E-4 65.6 1-800-LATTICE (528-8423) (503) 268-8001 [email protected] www.latticesemi.com Copyright © 2005 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), IPexpress, LatticeEC, September 2005 LatticeECP, LatticeMico8, LatticeXP, and MachXO are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/ Order #: I0177 or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies..
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