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4.12.2014 Computer System Structures cz:Struktury počítačových systémů Version: 1.0 Lecturer: Richard Šusta ČVUT-FEL in Prague, CR – subject A0B35SPS Microprocessors 2 1 4.12.2014 Definition: Microprocessor A Microprocessor is a Single VLSI Chip that has a CPU and may also have some Other Units (for example, caches, floating point processing arithmetic unit, pipelining, and super-scaling units) Source Microprocessor Family Motorola 68HCxxx Intel 80x86 & i860 Sun SPARC IBM PowerPC Source: Raj Kamal, Embedded Systems: Architecture, Programming and Design 3 Existovalo a dodnes existuje mnoho typů od různých výrobců http://research.microsoft.com/en-us/um/people/gbell/CyberMuseum_contents/Microprocessor_Evolution_Poster.jpg 2 4.12.2014 From 8 bit to 32 bit CISC processors 8 bit µ-processor 8008 8080 8085 Z80 Year 1972 1974 1976 1976 Instructions 66 111 113 158 MIPS 0.06 0.29 0.37 0.58 Minimum system (IO circuits) 20-40 7 3 3 16 and 32 bit 64bit example: Intel 8086/88 80286 80386 80486 Pentium I5-2500K Quad core µ-processor Year 1978/79 1982 1985-91 1989-94 1993-98 2011 Instructions processor 133 ~175 ~195 ~200 ~225 ~500 + numeric cooprocessor MIPS 0.33-0.75 0.9-2.6 2.5-11 16-70 100-300 ~80000 Memory Physical / Virtual 1 MB 16 MB/1 GB 4 GB / 64TB 32 GB / 256 TB Definition: Microcontroller A microcontroller is a single-chip VLSI unit which, though having limited computational capabilities possesses enhanced input- output capabilities and a number of on- chip functional units Source Microcontroller Family Motorola 68HC11xx, HC12xx, HC16xx Intel 80x86, 8051, 80251 Microchip PIC 16F84, 16F876, PIC18 ARM ARM9, ARM7 Source: Raj Kamal, Embedded Systems: Architecture, Programming and Design 6 3 4.12.2014 Microcontroller Output interfaces Output Input intefaces Input In device1 Out device1 In device2 Microcontroller (uC) Out device2 In device3 Auxiliary units 7 Example: “Original” 8051 Microcontroller Oscillator 4096 Bytes 128 Bytes Two 16 Bit and timing Program Data Timer/Event Memory Memory Counters 8051 Internal data bus CPU 64 K Byte Bus Programmable Programmable Expansion I/O Serial Port Full Control Duplex UART Synchronous Shifter subsystem interrupts External interrupts Control Parallel ports Serial Output Address Data Bus Serial Input I/O pins Source: Raj Kamal, Embedded Systems: Architecture, Programming and Design 8 4 4.12.2014 Hardcore/Softcore Processors Hard-core Processors A Fabricated Integrated Circuit that may or may not be Embedded into Additional Logic Soft-core Processors A Processor Described in a HDL that is implemented in Reconfigurable Logic (ie, in an FPGA), e.g NIOS, MicroBlaze, OpenRISC SPS 9 Soft-core Processors Logic Elements Ultra SPARC S1 Core/f 60000 S1 Core 37000 OpenRISC 1200 6000 LEON2 5000 Sun Microsystems Sun LEON3 3500 ARM Cortex-M1 2600 aeMB 2536 source LatticeMico32 1984 OpenFire 1928 Open Nios II/f 1800 Xilinx MicroBlaze 1324 Nios II/s 1170 DSPuva16 510 Nios II/e 390 PacoBlaze 204 LatticeMico8 200 Xilinx PicoBlaze 192 100 1000 10000 100000 SPS 10 5 4.12.2014 Nios II: RISC soft-core processor Copyright © 2005 Altera Corporation Nios II Versions Nios II Processor Comes In Three ISA (Instruction Set Architecture) Compatible Versions FAST: Optimized for Speed STANDARD: Balanced for Speed and Size ECONOMY: Optimized for Size Software Code is Binary Compatible No Changes Required When CPU is Changed Copyright © 2005 Altera Corporation 12 6 4.12.2014 Nios II: Hard Numbers Nios II/ f Nios II /s Nios II /e Stratix II 200 DMIPS @ 90 DMIPS @ 28 DMIPS @ 175MHz 175MHz 190MHz 1180 LEs 800 LEs 400 LEs Cyclone 100 DMIPS @ 62 DMIPS @ 20 DMIPS @ 125MHz 125MHz 140MHz 1800 LEs 1200 LEs 550 LEs DMIPS = Dhrystone benchmark MIPS (million instructions per second) Dhrystone is without float point operations (Note: Whetstone [cz brousek] has float points) Comparing with Pentium (1996) 224 DMIPS @ 200MHz cca 196 DMIPS@175MHz - cca 140 DMIPS@125 MHz Copyright © 2005 Altera Corporation 13 Processor Core Variations Nios II /f Nios II /s Nios II /e Fast Standard Economy Pipeline 6 Stage 5 Stage None H/W Multiplier & Emulated 1 Cycle 3 Cycle Barrel Shifter In Software Branch Prediction Dynamic Static None Instruction Cache Configurable Configurable None Data Cache Configurable None None Logic Requirements 1800 w/o MMU 1200 600 (Typical LEs) 3200 w/ MMU Custom Up to 256 Instructions © 2010 Altera Corporation—Public (MMU - Memory Management Unit) ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. 14 7 4.12.2014 Mutlicycle CPU Start State 0 1 Instr. Instr. fetch/ decode/reg. fetch/branch adv. PC addr. load Reg Jump Branch 3 2 Read Compute ALU Write PC Write memory memory operation on branch jump addr. data addr. condition to PC 6 9 4 store 8 5 7 Write Write memory Write register data register 15 SPS 15 Different Execution Time of Instructions instruction data registers ALU registers memory memory Fastest P Not Not Not Not Jump C used used used used Not Not P Not Branch C used used used P Not Compute C used P Load C Not P used Store C Not SlowestSPS 16 8 4.12.2014 Single-cycle versus multicycle instruction execution. Clock Time needed Time allotted Instr 1 Instr 2 Instr 3 Instr 4 Clock Time Time needed saved 3 cycles 5 cycles 3 cycles 4 cycles Time allotted Instr 1 Instr 2 Instr 3 Instr 4 SPS 17 Internal Registers in CPUs Processor Memory Input/Output PC IR AC Address Bus MAR Data Bus ALU MDR PC Program counter Control Unit AC Accumulator Internal registers IR Instruction register MAR Memory address register MDR Memory data register SPS 18 9 4.12.2014 Cycles of Instructions Store Fetch IR MAR MDR Result Operands Fetch Decode Execute Instruction Opcode Operation SPS 19 Pipelining Řízení procesoru s pipelining (zřetězeným) zpracováním instrukcí není jednoduché. Autoři procesoru MIPS, podobného NIOSu, uvádějí ve své knize (Paterson, D., Henessy, J.: Computer Organization and Design, Elsevier), že jimi navržená jednotka pro pipelining úspěšně otestována nejméně 100 lidmi na 18 různých pracovištích obsahovala chybu ztracenou v několika tisících řádkách HDL kódu, na kterou se přišlo až delším používání. Více bude v předmětu A0B36APO Architektura počítačů SPS 20 10 4.12.2014 Minimum Nios II Processor Nios II Processor Core reset Instruction General clock Program Master Purpose Port Controller Registers & Address Generation Status & Control Registers Data Master Arithmetic Port Logic Unit = Configurable = Fixed © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. 21 Outside NIOS Image source: Tron 11 4.12.2014 Simple NIOS System on DE2 Nios Processor Address (32) Switch PIO Read 32-Bit Bus Avalon Nios Write LED PIO Processor Data In (32) Data Out (32) 7-Segment LED PIO PIO-32 UART Timer User-Defined Interface 23 Nios II/e on Basic Computer for DE2 Copyright © 2005 Altera Corporation 24 12 4.12.2014 NIOS DE2 Basic Computer Start-address End-address Element Size 0x00000000 0x007FFFFF SDRAM 8 MB Ram 128 MB --- 120 MB MB 0x08000000 0x0807FFFF ROM (SRAM) 512 kB read-only 16 MB 256 15,5 MB 0x09000000 0x09001FFF On-chip-RAM 8 kB 112 MB 111,92 MB 0x10000000 0x10000003 LEDR 4 bytes-write-only 0x10000010 0x10000013 LEDG 4 bytes-write-only 0x10000020 0x10000023 HEX3_HEX0 4 bytes-write-only 0x10000030 0x10000033 HEX7_HEX4 4 bytes-write-only 0x10000040 0x10000043 SW 4 bytes-read-only 4 bytes data 0x10000050 0x1000005F KEY_BASE +12 bytes control .. other I/O 25 Memory Map of Basic Computer SDRAM - synchronous dynamic RAM, i.e. synchronized with the system bus, on the DE2 board - 1M x 16 bits x 4 banks - addresses 0x00000000 to 0x007FFFFF. SRAM - static RAM (SRAM) chip, on the DE2 board - 256K x 16 bits - addresses space 0x08000000 to 0x0807FFFF. On-Chip Memory 8-Kbyte memory inside the Cyclone II FPGA chip - 2K x 32 bits - addresses 0x09000000 to 0x09001FFF. 26 Copyright © 2005 Altera Corporation 13 4.12.2014 Nios II/s: DE2 Media Computer Copyright © 2005 Altera Corporation 27 NIOS DE2 Media Computer Start-address End-address Element Size 0x00000000 0x007FFFFF SDRAM 8 MB synchron. DRAM 128 MB --- 120 MB MB 0x08000000 0x0807FFFF SRAM 512 kB VGA pixel buffer 16 MB 256 15,5 MB 0x09000000 0x09001FFF On-chip-RAM 8 kB VGA char. buffer 112 MB 111,92 MB 0x10000000 0x10000003 LEDR 4 bytes-write-only 0x10000010 0x10000013 LEDG 4 bytes-write-only 0x10000020 0x10000023 HEX3_HEX0 4 bytes-write-only 0x10000030 0x10000033 HEX7_HEX4 4 bytes-write-only 0x10000040 0x10000043 SW 4 bytes-read-only 4 bytes data 0x10000050 0x1000005F KEY_BASE +12 bytes control 28 .. other I/O 28 14 4.12.2014 I/O DE2 Basic & Media Computer 0x10000000 LEDR_BASE 0x10000010 LEDG_BASE, 0x10000020 HEX3_HEX0_BASE 0x10000030 HEX7_HEX4_BASE 0x10000040 SW_BASE 0x10000050 KEY_BASE ...others I/O... Literatura on DVD: DE2_Media_Computer.pdf 29 Switch and Push Button SW_BASE KEY_BASE 30 15 4.12.2014 LED LEDR_BASE LEDG_BASE 31 HEX HEX3_HEX0_BASE HEX7_HEX4_BASE 32 16 4.12.2014 Wiki: Memory Mapped IO Memory-mapped I/O (MMIO) and port I/O (also called isolated I/O or port-mapped I/O abbreviated PMIO) are two complementary methods of performing input/output between the CPU and peripheral devices in a computer. An alternative approach, not discussed here, is using dedicated I/O processors — commonly known as channels on mainframe computers — that execute their own instructions. Memory-mapped I/O (not to be confused with memory-mapped file I/O) uses the same address bus to address both memory and I/O devices ‒ the memory and registers of the I/O devices are mapped to (associated with) address values.
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  • CDA 4253 FPGA System Design the Picoblaze Microcontroller

    CDA 4253 FPGA System Design the Picoblaze Microcontroller

    CDA 4253 FPGA System Design The PicoBlaze Microcontroller Hao Zheng Comp Sci & Eng U of South Florida Overview of PicoBlaze • So:-core microcontroller in VHDL: portable to other plaorms. • Small: occupies ~20 CLBs. • Respectable performance: 50 MIPS • Predictable performance: every instrucOon takes 2 cycles. • Suitable for simple data processing and control. 2 Required Reading • P. Chu, FPGA Prototyping by VHDL Examples Chapter 14, PicoBlaze Overview Recommended Reading • PicoBlaxe 8-bit Embedded Microcontroller User Guide (UG129) • K. Chapman, PicoBlaze for Spartan-6, Virtex-6, and 7-Series (KCPSM6) 3 Block diagram of a General-Purpose Processor ctrl 4 Block diagram of a General-Purpose Processor (Microcontroller) 5 PicoBlaze Overview 8-bit data Width, 18-bit instrucOon Width, 10-bit program address 6 Size of PicoBlaze-6 in Spartan 6 1. Resource UOlizaon in CLB Slices • 26 CLB Slices • 1.1% of Spartan-6 used in Nexys3 2. Number of PicoBlaze-6 cores fing inside of the Spartan-6 FPGA (XC6SLX16) used in the Nexys3 FPGA board • 87 PicoBlaze cores Speed of PicoBlaze on Basys-3 1. Maximum Clock Frequency • 100 MHz 2. Maximum number of instrucOons per second • 50 millions of instrucOons per second (MIPS) Fixed Oming: ideal for real-Ome control applicaons, i.e. flight control, manufacturing process control, ... Register File of PicoBlaze-3 8-bit Address 0 7 s0 0 1 7 s1 0 2 7 s2 0 3 7 s3 0 4 7 s4 0 5 7 s5 0 6 7 s6 0 16 Registers 7 7 s7 0 F 7 sF 0 9 DefiniNon of Flags Flags are set or reset after ALU operations Zero flag - Z zero condition Z = 1 if result = 0 0 otherwise Carry flag - C overflow, underflow, or various conditions Example* C = 1 if result > 28-1 (for addition) or result < 0 (for subtraction) 0 otherwise *Applies only to addition or subtraction related instructions, refer to the following slides otherwise 10 Interface of PicoBlaze Inputs Outputs KCPSM = constant (K) coded programmable state machine 11 Interface of PicoBlaze in_port[7:0] – input data port that carries the data for the INPUT instrucOon.