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Nios® II Processor Reference Guide

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Nios® II Processor Reference Guide Nios® II Processor Reference Guide Subscribe NII-PRG | 2020.10.22 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction................................................................................................................... 8 1.1. Nios II Processor System Basics.............................................................................. 8 1.2. Getting Started with the Nios II Processor.................................................................9 1.3. Customizing Nios II Processor Designs....................................................................10 1.4. Configurable Soft Processor Core Concepts..............................................................11 1.4.1. Configurable Soft Processor Core............................................................... 11 1.4.2. Flexible Peripheral Set and Address Map......................................................11 1.4.3. Automated System Generation.................................................................. 12 1.5. Intel FPGA IP Evaluation Mode...............................................................................13 1.6. Introduction Revision History.................................................................................13 2. Processor Architecture..................................................................................................14 2.1. Processor Implementation.....................................................................................15 2.2. Register File........................................................................................................16 2.3. Arithmetic Logic Unit............................................................................................ 17 2.3.1. Unimplemented Instructions......................................................................17 2.3.2. Custom Instructions................................................................................. 17 2.4. Reset and Debug Signals...................................................................................... 18 2.5. Exception and Interrupt Controllers........................................................................ 18 2.5.1. Exception Controller................................................................................. 19 2.5.2. EIC Interface...........................................................................................19 2.5.3. Internal Interrupt Controller...................................................................... 20 2.6. Memory and I/O Organization................................................................................20 2.6.1. Instruction and Data Buses....................................................................... 21 2.6.2. Cache Memory.........................................................................................23 2.6.3. Tightly-Coupled Memory........................................................................... 25 2.6.4. Address Map........................................................................................... 26 2.6.5. Memory Management Unit.........................................................................26 2.6.6. Memory Protection Unit............................................................................ 27 2.7. JTAG Debug Module............................................................................................. 27 2.7.1. JTAG Target Connection............................................................................ 28 2.7.2. Download and Execute Software................................................................ 28 2.7.3. Software Breakpoints............................................................................... 29 2.7.4. Hardware Breakpoints.............................................................................. 29 2.7.5. Hardware Triggers....................................................................................29 2.7.6. Trace Capture..........................................................................................30 2.8. Processor Architecture Revision History...................................................................31 3. Programming Model......................................................................................................33 3.1. Operating Modes..................................................................................................33 3.1.1. Supervisor Mode......................................................................................33 3.1.2. User Mode.............................................................................................. 34 3.2. Memory Management Unit.................................................................................... 34 3.2.1. Recommended Usage............................................................................... 34 3.2.2. Memory Management............................................................................... 35 3.2.3. Address Space and Memory Partitions.........................................................36 3.2.4. TLB Organization..................................................................................... 38 3.2.5. TLB Lookups............................................................................................39 ® Nios II Processor Reference Guide Send Feedback 2 Contents 3.3. Memory Protection Unit........................................................................................ 39 3.3.1. Memory Regions...................................................................................... 40 3.3.2. Overlapping Regions.................................................................................41 3.3.3. Enabling the MPU.....................................................................................42 3.4. Registers............................................................................................................ 42 3.4.1. General-Purpose Registers........................................................................ 42 3.4.2. Control Registers..................................................................................... 43 3.4.3. Shadow Register Sets...............................................................................62 3.5. Working with the MPU.......................................................................................... 65 3.5.1. MPU Region Read and Write Operations.......................................................65 3.5.2. MPU Initialization..................................................................................... 66 3.5.3. Debugger Access..................................................................................... 67 3.6. Working with ECC................................................................................................ 67 3.6.1. Enabling ECC...........................................................................................67 3.6.2. Handling ECC Errors................................................................................. 67 3.6.3. Injecting ECC Errors.................................................................................68 3.7. Exception Processing............................................................................................71 3.7.1. Terminology............................................................................................ 71 3.7.2. Exception Overview..................................................................................72 3.7.3. Exception Latency.................................................................................... 74 3.7.4. Reset Exceptions......................................................................................74 3.7.5. Break Exceptions..................................................................................... 75 3.7.6. Interrupt Exceptions.................................................................................76 3.7.7. Instruction-Related Exceptions...................................................................80 3.7.8. Other Exceptions..................................................................................... 85 3.7.9. Exception Processing Flow.........................................................................85 3.7.10. Determining the Cause of Interrupt and Instruction-Related Exceptions......... 90 3.7.11. Handling Nested Exceptions.....................................................................91 3.7.12. Handling Nonmaskable Interrupts.............................................................93 3.7.13. Masking and Disabling Exceptions.............................................................93 3.8. Memory and Peripheral Access...............................................................................95 3.8.1. Cache Memory.........................................................................................96 3.9. Instruction Set Categories.....................................................................................97 3.9.1. Data Transfer Instructions......................................................................... 97 3.9.2. Arithmetic and Logical Instructions.............................................................98 3.9.3. Move Instructions.................................................................................... 98 3.9.4. Comparison Instructions........................................................................... 99 3.9.5. Shift and Rotate Instructions....................................................................
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