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Nios II Processor Reference Handbook Nios II Processor Reference Handbook 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com NII5V1-6.1 Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des- ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap- plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in- formation and before placing orders for products or services. Printed on recycled paper ii Altera Corporation Contents Chapter Revision Dates ........................................................................... ix About This Handbook .............................................................................. xi Introduction ............................................................................................................................................... xi Assumptions about the Reader ..................................................................................................... 1–xi How to Find Further Information ........................................................................................................ xii How to Contact Altera ........................................................................................................................... xii Typographical Conventions ................................................................................................................. xiii Section I. Nios II Processor Chapter 1. Introduction Introduction ............................................................................................................................................ 1–1 Nios II Processor System Basics ..................................................................................................... 1–1 Getting Started with the Nios II Processor ................................................................................... 1–2 Customizing Nios II Processor Designs ........................................................................................ 1–3 Configurable Soft-Core Processor Concepts ...................................................................................... 1–3 Configurable Soft-Core Processor .................................................................................................. 1–4 Flexible Peripheral Set & Address Map ........................................................................................ 1–4 Custom Instructions ......................................................................................................................... 1–5 Automated System Generation ...................................................................................................... 1–5 Document Revision History ................................................................................................................. 1–6 Chapter 2. Processor Architecture Introduction ............................................................................................................................................ 2–1 Processor Implementation .................................................................................................................... 2–2 Register File ............................................................................................................................................ 2–3 Arithmetic Logic Unit ........................................................................................................................... 2–3 Unimplemented Instructions .......................................................................................................... 2–4 Custom Instructions ......................................................................................................................... 2–4 Floating Point Instructions .............................................................................................................. 2–4 Reset Signals ........................................................................................................................................... 2–5 Exception & Interrupt Controller ........................................................................................................ 2–6 Exception Controller ........................................................................................................................ 2–6 Integral Interrupt Controller ........................................................................................................... 2–6 Interrupt Vector Custom Instruction ............................................................................................. 2–6 Memory & I/O Organization .............................................................................................................. 2–8 Instruction & Data Buses ................................................................................................................. 2–9 Altera Corporation iii Contents Cache Memory ................................................................................................................................ 2–11 Tightly Coupled Memory ............................................................................................................. 2–13 Address Map ................................................................................................................................... 2–14 JTAG Debug Module .......................................................................................................................... 2–14 JTAG Target Connection ............................................................................................................... 2–15 Download & Execute Software .................................................................................................... 2–15 Software Breakpoints ..................................................................................................................... 2–15 Hardware Breakpoints .................................................................................................................. 2–16 Hardware Triggers ......................................................................................................................... 2–16 Trace Capture .................................................................................................................................. 2–17 Document Revision History ............................................................................................................... 2–19 Chapter 3. Programming Model Introduction ............................................................................................................................................ 3–1 General-Purpose Registers ................................................................................................................... 3–1 Control Registers ................................................................................................................................... 3–2 Operating Modes ................................................................................................................................... 3–4 Normal Mode .................................................................................................................................... 3–5 Debug Mode ...................................................................................................................................... 3–5 Changing Modes .............................................................................................................................. 3–5 Exception Processing ............................................................................................................................. 3–5 Exception Types ................................................................................................................................ 3–6 Determining the Cause of Exceptions ........................................................................................... 3–9 Nested Exceptions .......................................................................................................................... 3–10 Returning from an Exception ...................................................................................................... 3–10 Break Processing .................................................................................................................................. 3–11 Processing a Break .......................................................................................................................... 3–11 Returning from a Break ................................................................................................................
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