DOCSLIB.ORG

Nios II Processor Reference Handbook

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Nios II Processor Reference Handbook Nios II Processor Reference Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com NII5V1-7.2 Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des- ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap- plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in- formation and before placing orders for products or services. Printed on recycled paper ii Altera Corporation Contents Chapter Revision Dates ........................................................................... ix About This Handbook .............................................................................. xi Introduction ............................................................................................................................................... xi Prerequisites ..................................................................................................................................... 1–xi How to Find Further Information ........................................................................................................ xii How to Contact Altera ........................................................................................................................... xii Typographical Conventions ................................................................................................................. xiii Section I. Nios II Processor Chapter 1. Introduction Introduction ............................................................................................................................................ 1–1 Nios II Processor System Basics .......................................................................................................... 1–1 Getting Started with the Nios II Processor ........................................................................................ 1–2 Customizing Nios II Processor Designs ............................................................................................. 1–3 Configurable Soft-Core Processor Concepts ...................................................................................... 1–4 Configurable Soft-Core Processor .................................................................................................. 1–4 Flexible Peripheral Set and Address Map .................................................................................... 1–5 Custom Instructions ......................................................................................................................... 1–5 Automated System Generation ...................................................................................................... 1–6 OpenCore Plus Evaluation ................................................................................................................... 1–6 Referenced Documents ......................................................................................................................... 1–7 Document Revision History ................................................................................................................. 1–7 Chapter 2. Processor Architecture Introduction ............................................................................................................................................ 2–1 Processor Implementation .................................................................................................................... 2–2 Register File ............................................................................................................................................ 2–3 Arithmetic Logic Unit ........................................................................................................................... 2–4 Unimplemented Instructions .......................................................................................................... 2–4 Custom Instructions ......................................................................................................................... 2–4 Floating Point Instructions .............................................................................................................. 2–5 Reset Signals ........................................................................................................................................... 2–6 Exception and Interrupt Controller .................................................................................................... 2–6 Exception Controller ........................................................................................................................ 2–6 Integral Interrupt Controller ........................................................................................................... 2–6 Interrupt Vector Custom Instruction ............................................................................................. 2–7 Altera Corporation iii Contents Memory and I/O Organization ........................................................................................................... 2–8 Instruction and Data Buses ............................................................................................................. 2–9 Cache Memory ................................................................................................................................ 2–11 Tightly-Coupled Memory ............................................................................................................. 2–13 Address Map ................................................................................................................................... 2–14 JTAG Debug Module .......................................................................................................................... 2–15 JTAG Target Connection ............................................................................................................... 2–15 Download and Execute Software ................................................................................................. 2–16 Software Breakpoints ..................................................................................................................... 2–16 Hardware Breakpoints .................................................................................................................. 2–16 Hardware Triggers ......................................................................................................................... 2–16 Trace Capture .................................................................................................................................. 2–18 Referenced Documents ....................................................................................................................... 2–19 Document Revision History ............................................................................................................... 2–20 Chapter 3. Programming Model Introduction ............................................................................................................................................ 3–1 General-Purpose Registers ................................................................................................................... 3–1 Control Registers ................................................................................................................................... 3–2 Operating Modes ................................................................................................................................... 3–4 Normal Mode .................................................................................................................................... 3–5 Debug Mode ...................................................................................................................................... 3–5 Changing Modes .............................................................................................................................. 3–5 Exception Processing ............................................................................................................................. 3–5 Reset Exceptions ............................................................................................................................... 3–6 Break Exceptions .............................................................................................................................. 3–7 Interrupt Exceptions ........................................................................................................................ 3–8 Instruction-Related Exceptions ...................................................................................................
Load more

Recommended publications
  • A Superscalar Out-Of-Order X86 Soft Processor for FPGA
    A Superscalar Out-of-Order x86 Soft Processor for FPGA Henry Wong University of Toronto, Intel [email protected] June 5, 2019 Stanford University EE380 1 Hi! ● CPU architect, Intel Hillsboro ● Ph.D., University of Toronto ● Today: x86 OoO processor for FPGA (Ph.D. work) – Motivation – High-level design and results – Microarchitecture details and some circuits 2 FPGA: Field-Programmable Gate Array ● Is a digital circuit (logic gates and wires) ● Is field-programmable (at power-on, not in the fab) ● Pre-fab everything you’ll ever need – 20x area, 20x delay cost – Circuit building blocks are somewhat bigger than logic gates 6-LUT6-LUT 6-LUT6-LUT 3 6-LUT 6-LUT FPGA: Field-Programmable Gate Array ● Is a digital circuit (logic gates and wires) ● Is field-programmable (at power-on, not in the fab) ● Pre-fab everything you’ll ever need – 20x area, 20x delay cost – Circuit building blocks are somewhat bigger than logic gates 6-LUT 6-LUT 6-LUT 6-LUT 4 6-LUT 6-LUT FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel code and hardware accelerators need effort – Less effort if soft processors got faster 5 FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel code and hardware accelerators need effort – Less effort if soft processors got faster 6 FPGA Soft Processors ● FPGA systems often have software components – Often running on a soft processor ● Need more performance? – Parallel
    [Show full text]
  • Implementation, Verification and Validation of an Openrisc-1200
    (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 10, No. 1, 2019 Implementation, Verification and Validation of an OpenRISC-1200 Soft-core Processor on FPGA Abdul Rafay Khatri Department of Electronic Engineering, QUEST, NawabShah, Pakistan Abstract—An embedded system is a dedicated computer system in which hardware and software are combined to per- form some specific tasks. Recent advancements in the Field Programmable Gate Array (FPGA) technology make it possible to implement the complete embedded system on a single FPGA chip. The fundamental component of an embedded system is a microprocessor. Soft-core processors are written in hardware description languages and functionally equivalent to an ordinary microprocessor. These soft-core processors are synthesized and implemented on the FPGA devices. In this paper, the OpenRISC 1200 processor is used, which is a 32-bit soft-core processor and Fig. 1. General block diagram of embedded systems. written in the Verilog HDL. Xilinx ISE tools perform synthesis, design implementation and configure/program the FPGA. For verification and debugging purpose, a software toolchain from (RISC) processor. This processor consists of all necessary GNU is configured and installed. The software is written in C components which are available in any other microproces- and Assembly languages. The communication between the host computer and FPGA board is carried out through the serial RS- sor. These components are connected through a bus called 232 port. Wishbone bus. In this work, the OR1200 processor is used to implement the system on a chip technology on a Virtex-5 Keywords—FPGA Design; HDLs; Hw-Sw Co-design; Open- FPGA board from Xilinx.
    [Show full text]
  • Application-Specific Customization of Soft Processor Microarchitecture
    Application-Specific Customization of Soft Processor Microarchitecture Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose The Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto {yiannac,steffan,jayar}@eecg.utoronto.ca ABSTRACT processors on their FPGA die, there has been significant up- A key advantage of soft processors (processors built on an take [15,16] of soft processors [3,4] which are constructed in FPGA programmable fabric) over hard processors is that the programmable fabric itself. While soft processors can- they can be customized to suit an application program’s not match the performance, area, or power consumption of specific software. This notion has been exploited in the past a hard processor, their key advantage is the flexibility they principally through the use of application-specific instruc- present in allowing different numbers of processors and spe- tions. While commercial soft processors are now widely de- cialization to the application through special instructions. ployed, they are available in only a few microarchitectural Specialization can also occur by selecting a different micro- variations. In this work we explore the advantage of tuning architecture for a specific application, and that is the focus the processor’s microarchitecture to specific software appli- of this paper. We suggest that this kind of specialization cations, and show that there are significant advantages in can be applied in two different contexts: doing so. 1. When an embedded processor is principally
    [Show full text]
  • Five Ways to Build Flexibility Into Industrial Applications with Fpgas by Jason Chiang and Stefano Zammattio, Altera Corporation
    Five Ways to Build Flexibility into Industrial Applications with FPGAs by Jason Chiang and Stefano Zammattio, Altera Corporation WP-01154-2.0 White Paper This document describes using an Altera® industrial-grade FPGA as a coprocessor or system on a chip (SoC) to bring flexibility to industrial applications. Providing a single, highly integrated platform for multiple industrial products, Altera FPGAs can substantially reduce development time and risk. Introduction Programmable logic devices (PLDs) are a critical component in embedded industrial designs. PLDs have evolved in industrial designs from providing simple glue logic, to the use of an FPGAs as a coprocessor. This technique allows for I/O expansion and off loads the primary microcontroller (MCU) or digital signal processor (DSP) device in applications such as communications, motor control, I/O modules, and image processing. As system complexity increases, FPGAs also offer the ability to integrate an entire SoC, at a lower cost compared to discrete MCU, DSP, ASSP, or ASIC solutions. Whether used as a coprocessor or SoC, Altera FPGAs offer the following advantages for your industrial applications: 1. Design Integration—Simplify and reduce cost by using an FPGA as a coprocessor or SoC that integrates the IP and software stacks on a single device platform. 2. Reprogrammability—Adapt industrial designs to evolving protocols, IP improvements, and new hardware features within one FPGA on a common development platform. 3. Performance Scaling—Enhance performance via embedded processors, custom instructions, and IP blocks within the FPGA to meet your system requirements. 4. Obsolescence Protection—Increase industrial product life cycles and provide protection against hardware obsolescence through long FPGA life cycles and device migration to new FPGA families.
    [Show full text]
  • Development of Softcore Processor
    IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 DEVELOPMENT OF SOFTCORE PROCESSOR Mohammed Zaheer1, A.M Khan2 1Research Student Department of Electronics Mangalore University, Karnataka, India 2proffesor chairman, Department of Electronics Mangalore University, Karnataka, India Abstract Designing of softcore processor on FPGA is based on software hardware co design. A soft-core processor is a hardware description language (HDL) model of a specific processor (CPU) that can be customized for a given application and synthesized for an ASIC or FPGA target. Embedded Systems which performs specific application using components having hardware and software together is known as embedded system. With hardware design getting complicated day by day, using of software tools for designing the system and testing has made the necessity of today’s technology. Due to the reduced size and greater complexity of hardware models, it requires a higher technological tool for simulation to satisfy the needs of the designers. The more efficient the simulator, complexity in the hardware model can be easily executed in small intervals of time, resulting in design product in a stipulated time intervals. The design of soft core processor system involves strict performance involving area, time, power, cost constraints. Advantages of Softcore processor design improves in design quality reduce integration and test time, supporting growing complexity of embedded system, processor cores, high level hardware synthesizing capabilities, ASIC/FPGA development and platform independence. Xilinx microblaze softcore processor support package allows to create mixed Hardware Software application using micro blaze processor. These processors are called as soft-core processor.
    [Show full text]
  • Nios® II Processor Reference Guide
    Nios® II Processor Reference Guide Subscribe NII-PRG | 2020.10.22 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction................................................................................................................... 8 1.1. Nios II Processor System Basics.............................................................................. 8 1.2. Getting Started with the Nios II Processor.................................................................9 1.3. Customizing Nios II Processor Designs....................................................................10 1.4. Configurable Soft Processor Core Concepts..............................................................11 1.4.1. Configurable Soft Processor Core............................................................... 11 1.4.2. Flexible Peripheral Set and Address Map......................................................11 1.4.3. Automated System Generation.................................................................. 12 1.5. Intel FPGA IP Evaluation Mode...............................................................................13 1.6. Introduction Revision History.................................................................................13 2. Processor Architecture..................................................................................................14 2.1. Processor Implementation.....................................................................................15 2.2. Register File........................................................................................................16
    [Show full text]
  • Accelerated V2X Provisioning with Extensible Processor Platform
    Accelerated V2X provisioning with Extensible Processor Platform Henrique S. Ogawa1, Thomas E. Luther1, Jefferson E. Ricardini1, Helmiton Cunha1, Marcos Simplicio Jr.2, Diego F. Aranha3, Ruud Derwig4 and Harsh Kupwade-Patil1 1 America R&D Center (ARC), LG Electronics US Inc. {henrique1.ogawa,thomas.luther,jefferson1.ricardini,helmiton1.cunha}@lge.com [email protected] 2 University of Sao Paulo, Brazil [email protected] 3 Aarhus University, Denmark [email protected] 4 Synopsys Inc., Netherlands [email protected] Abstract. With the burgeoning Vehicle-to-Everything (V2X) communication, security and privacy concerns are paramount. Such concerns are usually mitigated by combining cryptographic mechanisms with a suitable key management architecture. However, cryptographic operations may be quite resource-intensive, placing a considerable burden on the vehicle’s V2X computing unit. To assuage this issue, it is reasonable to use hardware acceleration for common cryptographic primitives, such as block ciphers, digital signature schemes, and key exchange protocols. In this scenario, custom extension instructions can be a plausible option, since they achieve fine-tuned hardware acceleration with a low to moderate logic overhead, while also reducing code size. In this article, we apply this method along with dual-data memory banks for the hardware acceleration of the PRESENT block cipher, as well as for the F2255−19 finite field arithmetic employed in cryptographic primitives based on Curve25519 (e.g., EdDSA and X25519). As a result, when compared with a state-of-the-art software-optimized implementation, the performance of PRESENT is improved by a factor of 17 to 34 and code size is reduced by 70%, with only a 4.37% increase in FPGA logic overhead.
    [Show full text]
  • Embedded Design Handbook
    Embedded Design Handbook Subscribe EDH | 2020.07.22 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Introduction................................................................................................................... 6 1.1. Document Revision History for Embedded Design Handbook........................................ 6 2. First Time Designer's Guide............................................................................................ 8 2.1. FPGAs and Soft-Core Processors.............................................................................. 8 2.2. Embedded System Design...................................................................................... 9 2.3. Embedded Design Resources................................................................................. 11 2.3.1. Intel Embedded Support........................................................................... 11 2.3.2. Intel Embedded Training........................................................................... 11 2.3.3. Intel Embedded Documentation................................................................. 12 2.3.4. Third Party Intellectual Property.................................................................12 2.4. Intel Embedded Glossary...................................................................................... 13 2.5. First Time Designer's Guide Revision History............................................................14 3. Hardware System Design with Intel Quartus Prime and Platform Designer.................
    [Show full text]
  • My First Nios II Software Tutorial
    My First Nios II Software Tutorial My First Nios II Software Tutorial 101 Innovation Drive San Jose, CA 95134 www.altera.com TU-01003-2.1 Document last updated for Altera Complete Design Suite version: 12.1 Document publication date: December 2012 Subscribe © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its ISO semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008 services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. December 2012 Altera Corporation My First Nios II Software Tutorial Contents Chapter 1. My First Nios II Software Design Software and Hardware Requirements . 1–1 Download Hardware Design to Target FPGA . 1–2 Nios II SBT for Eclipse Build Flow . 1–4 Create the Hello World Example Project . 1–4 Build and Run the Program . 1–7 Edit and Rerun the Program .
    [Show full text]
  • PS2 Controller IP Core for on Chip Embedded System Applications
    International Journal of Computational Engineering Research||Vol, 03||Issue, 6|| PS2 Controller IP Core For On Chip Embedded System Applications 1,V.Navya Sree , 2,B.R.K Singh 1,2,M.Tech Student, Assistant Professor Dept. Of ECE, DVR&DHS MIC College Of Technology, Kanchikacherla,A.P India. ABSTRACT In many case on chip systems are used to reduce the development cycles. Mostly IP (Intellectual property) cores are used for system development. In this paper, the IP core is designed with ALTERA NIOSII soft-core processors as the core and Cyclone III FPGA series as the digital platform, the SOPC technology is used to make the I/O interface controller soft-core such as microprocessors and PS2 keyboard on a chip of FPGA. NIOSII IDE is used to accomplish the software testing of system and the hardware test is completed by ALTERA Cyclone III EP3C16F484C6 FPGA chip experimental platform. The result shows that the functions of this IP core are correct, furthermore it can be reused conveniently in the SOPC system. KEYWORDS: Intellectual property, I. INTRODUCTION An intellectual property or an IP core is a predesigned module that can be used in other designs IP cores are to hardware design what libraries are to computer programming. An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array ( FPGA ) or application-specific integrated circuit ( ASIC ) for a product. As essential elements of design reuse , IP cores are part of the growing electronic design automation ( EDA ) industry trend towards repeated use of previously designed components.
    [Show full text]
  • Embedded Systems & the Nios II Soft Core Processor
    Embedded systems & the Nios II soft core processor A Nios II processor system I equivalent to a microcontroller or System on a chip (SoC) The Nios II processor family consits of two configurable 32-bit Harvard architecture cores Fast (/f core): Six-stage pipeline optimized for highest performance, optional memory management unit, or memory protection unit Economy (/e core): Optimized for smallest size, and available at no cost (no license required) • One-stage pipeline à one instruction per six clock cycles Choosing the core in Platform Designer NIOS–II Core block diagram • A general-purpose RISC processor core • 32-bit instruction set, data path, and address space • 32 general-purpose registers • Optional shadow register sets – useful for context switching on multitasking systems (e.g. Interrupts, RTOS) • 32 interrupt sources • External interrupt controller interface for more interrupt sources • Supports single-precision floating-point operations Nios II Processor Reference Guide, Intel, Available online: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf Nios II performance https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/ds_nios2_perf.pdf https://en.wikipedia.org/wiki/List_of_ARM_microarchitectures Nios II performance Compared to: ARM Cortex – M1 ARM Cortex - A9 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/ds_nios2_perf.pdf https://en.wikipedia.org/wiki/List_of_ARM_microarchitectures Nios II performance Example minimum implementation MAX 10 in chip planner NIOS II • A widely used soft processors in the FPGA industry – Soft core IP • Supports Intel’s (former Altera) FPGAs and is even available for standard-cell ASICs (Synopsys).
    [Show full text]
  • PVMC: Programmable Vector Memory Controller
    PVMC: Programmable Vector Memory Controller Tassadaq Hussain1;2, Oscar Palomar1;2, Osman Unsal1, Adrian Cristal1;2;3, Eduard Ayguade´1;2, Mateo Valero1;2 1 Computer Sciences, Barcelona Supercomputing Center, Barcelona, Spain 2 Departament d’Arquitectura de Computadors, Universitat Politecnica` de Catalunya, Barcelona, Spain 3 Artificial Intelligence Research Institute (IIIA), Centro Superior de Investigaciones Cient´ıficas (CSIC), Barcelona, Spain Email: ffi[email protected] Abstract—In this work, we propose a Programmable Vector patterns using a variety of memory access instructions. The Memory Controller (PVMC), which boosts noncontiguous vector PVMC manages memory access patterns in hardware thus data accesses by integrating descriptors of memory patterns, a improves the system performance by prefetching complex specialized local memory, a memory manager in hardware, and access patterns in parallel with computation and by transferring multiple DRAM controllers. We implemented and validated the them to the vector processor without using a complex crossbar proposed system on an Altera DE4 FPGA board. We compare the performance of our proposal with a vector system without network. This allows a PVMC-based vector system to operate PVMC as well as a scalar only system. When compared with a at higher clock frequencies. The PVMC includes a special- baseline vector system, the results show that the PVMC system ized memory unit that holds complex patterns and efficiently transfers data sets up to 2.2x to 14.9x faster, achieves between accesses, reuses, aligns and feeds data to a vector processor. 2.16x to 3.18x of speedup for 5 applications and consumes 2.56 PVMC supports multiple data buses that increase the local to 4.04 times less energy.
    [Show full text]