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CDA 4253 FPGA System Design the Picoblaze Microcontroller

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CDA 4253 FPGA System Design the Picoblaze Microcontroller CDA 4253 FPGA System Design The PicoBlaze Microcontroller Hao Zheng Comp Sci & Eng U of South Florida Overview of PicoBlaze • So:-core microcontroller in VHDL: portable to other plaorms. • Small: occupies ~20 CLBs. • Respectable performance: 50 MIPS • Predictable performance: every instrucOon takes 2 cycles. • Suitable for simple data processing and control. 2 Required Reading • P. Chu, FPGA Prototyping by VHDL Examples Chapter 14, PicoBlaze Overview Recommended Reading • PicoBlaxe 8-bit Embedded Microcontroller User Guide (UG129) • K. Chapman, PicoBlaze for Spartan-6, Virtex-6, and 7-Series (KCPSM6) 3 Block diagram of a General-Purpose Processor ctrl 4 Block diagram of a General-Purpose Processor (Microcontroller) 5 PicoBlaze Overview 8-bit data Width, 18-bit instrucOon Width, 10-bit program address 6 Size of PicoBlaze-6 in Spartan 6 1. Resource UOlizaon in CLB Slices • 26 CLB Slices • 1.1% of Spartan-6 used in Nexys3 2. Number of PicoBlaze-6 cores fing inside of the Spartan-6 FPGA (XC6SLX16) used in the Nexys3 FPGA board • 87 PicoBlaze cores Speed of PicoBlaze on Basys-3 1. Maximum Clock Frequency • 100 MHz 2. Maximum number of instrucOons per second • 50 millions of instrucOons per second (MIPS) Fixed Oming: ideal for real-Ome control applicaons, i.e. flight control, manufacturing process control, ... Register File of PicoBlaze-3 8-bit Address 0 7 s0 0 1 7 s1 0 2 7 s2 0 3 7 s3 0 4 7 s4 0 5 7 s5 0 6 7 s6 0 16 Registers 7 7 s7 0 F 7 sF 0 9 DefiniNon of Flags Flags are set or reset after ALU operations Zero flag - Z zero condition Z = 1 if result = 0 0 otherwise Carry flag - C overflow, underflow, or various conditions Example* C = 1 if result > 28-1 (for addition) or result < 0 (for subtraction) 0 otherwise *Applies only to addition or subtraction related instructions, refer to the following slides otherwise 10 Interface of PicoBlaze Inputs Outputs KCPSM = constant (K) coded programmable state machine 11 Interface of PicoBlaze in_port[7:0] – input data port that carries the data for the INPUT instrucOon. 12 Interface of PicoBlaze out_port[7:0] – carries the output data for an OUTPUT instrucOon. 13 Interface of PicoBlaze port_id[7:0] – addresses of components connected to PicoBlaze. Holds for two cycles during an INPUT/OUTPUT instrucOon. 14 Interface of PicoBlaze write_strobe – being asserted ‘1’ validates the data on the output_port[7:0]. 15 Interface of PicoBlaze read_strobe – being asserted ‘1’ indicates the capture of the data on the input_port[7:0] during an INPUT instrucOon. 16 Interface of PicoBlaze reset – needs to be asserted for at least one cycle. 17 Interface of PicoBlaze interrupt – assert it for at least two cycles to trigger an interrupt event in PicoBlaze. 18 Interface of PicoBlaze interrupt_ack – acknoWledges the current interrupt has been recognized by PicoBlaze. Used to clear the current interrupt. 19 Interface of PicoBlaze – Summary Name Direction Size Function clk input 1 System clock signal. reset input 1 Reset signal. address output 10 Address of the instruction memory. Specifies address of the instruction to be retrieved. instruction input 18 Fetched instruction. port_id output 8 Address of the input or output port. in_port input 8 Input data from I/O peripherals. read_strobe output 1 Strobe associated with the input operation. out_port output 8 Output data to I/O peripherals. write_strobe output 1 Strobe associated with the output operation. interrupt input 1 Interrupt request from I/O peripherals. interrupt_ack output 1 Interrupt acknowledgment to I/O peripherals 20 Chapter 9 Using the PicoBlaze Microcontroller in an FPGA Design The PicoBlaze™ microcontroller is primarily designed for use in a VHDL design flow. However, both Verilog and black box instantiation are also supported, as described below. VHDL Design Flow The PicoBlaze microcontroller is supplied as a VHDL source file, called KCPSM3.vhd, which is optimized for efficient and predictable implementation in a Spartan-3, Spartan-6, and Virtex-6 FPGA. The code is suitable for both synthesis and simulation and was developed and tested using the Xilinx Synthesis Tool (XST) for logic synthesis and ModelSim for simulation. Designers have also successfully used other logic synthesis and simulation tools. The VHDL source code must not be modified in any way. KCPSM3 Module The KCPSM3 module contains the PicoBlaze ALU, register file, scratchpad, RAM, etc. The only function not included is the instruction store. The component declaration for the KCPSM3 module appears in Figure 9-1. Figure 9-2 lists the KCPSM3 component instantiation.Use of PicoBlaze in VHDL Design component KCPSM3 port ( address : out std_logic_vector( 9 downto 0); instruction : in std_logic_vector(17 downto 0); port_id : out std_logic_vector( 7 downto 0); write_strobe : out std_logic; out_port : out std_logic_vector( 7 downto 0); read_strobe : out std_logic; in_port : in std_logic_vector( 7 downto 0); interrupt : in std_logic; interrupt_ack : out std_logic; reset : in std_logic; clk : in std_logic ); end component; FigurePicoBlaze Component Declaraon 9-1: VHDL Component Declaration of KCPSM3 21 PicoBlaze 8-bit Embedded Microcontroller www.xilinx.com 61 UG129 (v2.0) June 22, 2011 Chapter 9: Using the PicoBlaze Microcontroller in an FPGA Design Use of PicoBlaze in VHDL Design processor: kcpsm3 port map( address => address_signal, instruction => instruction_signal, port_id => port_id_signal, write_strobe => write_strobe_signal, out_port => out_port_signal, read_strobe => read_strobe_signal, in_port => in_port_signal, interrupt => interrupt_signal, interrupt_ack => interrupt_ack_signal, reset => reset_signal, clk => clk_signal ); FigurePicoBlaze Component InstanOaon 9-2: VHDL Component Instantiation of the KCPSM3 22 Connecting the Program ROM The PicoBlaze program ROM is used within a VHDL design flow. The PicoBlaze assembler generates a VHDL file in which a block RAM and its initial contents are defined. This VHDL file can be used for both logic synthesis and simulation of the processor. Figure 9-3 shows the component declaration for the program ROM, and Figure 9-4 shows the component instantiation. The name of the program ROM, shown as "prog_rom" in the following figures, is derived from the name of the PicoBlaze assembler source file. For example, if the assembler source file is named phone.psm, then the assembler generates a program ROM definition file called phone.vhd. component prog_rom port ( address : in std_logic_vector( 9 downto 0); instruction : out std_logic_vector(17 downto 0); clk : in std_logic ); end component; Figure 9-3: VHDL Component Declaration of Program ROM program: prog_rom port map( address => address_signal, instruction => instruction_signal, clk => clk_signal ); Figure 9-4: VHDL Component Instantiation of Program ROM To speed development, a VHDL file called embedded_KCPSM3.vhd is provided. In this file, the PicoBlaze macro is connected to its associated block RAM program ROM. This entire module can be embedded in the design application, or simply used to cut and paste the component declaration and instantiation information into the user’s design files. 62 www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller UG129 (v2.0) June 22, 2011 Chapter 9: Using the PicoBlaze Microcontroller in an FPGA Design Chapter 9: Using the PicoBlaze Microcontroller in an FPGA Design processor: kcpsm3 port map( processor: kcpsm3 address => address_signal, port map ( instruction => instruction_signal, addressport_id => port_id_signal,address_signal, write_strobeinstruction => write_strobe_signal,instruction_signal, out_portport_id => out_port_signal,port_id_signal, write_strobe read_strobe => read_strobe_signal,write_strobe_signal, out_port in_port => in_port_signal,out_port_signal, read_strobe interrupt => interrupt_signal,read_strobe_signal, interrupt_ack in_port => interrupt_ack_signal,in_port_signal, interrupt reset => reset_signal,interrupt_signal, interrupt_ack clk => clk_signalinterrupt_ack_signal, ); reset => reset_signal, clk => clk_signal Figure ); 9-2: VHDL Component Instantiation of the KCPSM3 Connecting the ProgramFigure 9-2: ROMVHDL Component Instantiation of the KCPSM3 ConnectingThe the PicoBlaze Program program ROM ROM is used within a VHDL design flow. The PicoBlaze assembler generates a VHDL file in which a block RAM and its initial contents are defined. This TheVHDL PicoBlaze file can program be used forROM both is usedlogic withinsynthesis a VHDL and simulation design flow. of theThe processor. PicoBlaze assembler generatesFigure 9-3 a shows VHDL the file component in which a declaration block RAM for and the its program initial contents ROM, and are Figuredefined. 9-4 This shows VHDLthe component file can be instantiation. used for both The logic name sy nthesisof the program and simulation ROM, shown of the as processor. "prog_rom" in the Figurefollowing 9-3 figures,shows the is derived component from declaration the name of for the the PicoBlaze program assembler ROM, and source Figure file. 9-4 For shows theexample, component if the assemblerinstantiation. source The file name is named of the phone.psmprogram ROM,, then shown the assembler as "prog_rom" generates in the a followingprogram ROM figures, definition is derived file from called the phone.vhd name of the. PicoBlaze assembler source file. For example, if the assembler source file is named phone.psm, then the assembler generates a programUse of PicoBlaze in VHDL Design component ROM definition prog_rom file called phone.vhd. port ( address : in std_logic_vector( 9 downto 0); component prog_rom instruction
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