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Emulate 8051 Microprocessor in Picoblaze IP Core EmulateEmulate 80518051 MicroprocessorMicroprocessor inin PicoBlazePicoBlaze IPIP CoreCore Put the functions of a legacy microprocessor into a Xilinx FPGA.FPGA. by Lance Roman President Roman-Jones, Inc. [email protected] Brad Fayette Senior Software Engineer Roman-Jones, Inc. [email protected] 00 Xcell Journal Winter 2004 How do you put a one-dollar Intel™ 8051 • Smaller Size – Traditional 8051 type core. Hook up block RAM or microprocessor into an FPGA without implementations range from 1,100 off-chip program ROM, and you’re using 10 dollars’ worth of FPGA fabric? to 1,600 slices of FPGA logic. The ready to go. The answer is emulation. Using soft- PicoBlaze 8051 processor requires • Low Cost – The PB8051 is $495 ware emulation, Roman-Jones Inc. has just 76 slices. Emulation hardware with an easy Xilinx SignOnce IP developed a new type of 8051 processor requires 77 slices. Add another 158 license. core built on a Xilinx 8-bit, soft-core slices for two timers and a four-mode PicoBlaze™ (PB) processor. This “new” serial port, and you have a total of a Architecture of Emulated 8051 PB8051 is more than 70% smaller than 311 slices. This is a reduction of As shown in Figure 1, the architecture of an competing soft-core implementations – more than two-thirds of the FPGA emulated processor has several elements. without sacrificing any of the performance fabric of competing products. Each element is designed independently, of this legacy part. The PB8051 is a Xilinx • Faster – At 1.3 million instructions but together, they act as a whole. AllianceCORE™ microprocessor built per second (MIPS), the PB8051 is through emulation. faster than a legacy 8051 (1 MIPS) PicoBlaze Platform running at 12 MHz. Compare this to The PicoBlaze host processor is the heart The Legacy of the 8051 5 MIPS with a 40 MHz Dallas version of the emulated system and defines the The Intel 8051 family of microprocessors or 8 MIPS with a traditional FPGA architecture of the PB8051 emulated – probably one of the most popular archi- processor core. It comprises: tectures around – is still the core of many embedded applications. This processor This “new” PB8051 • PicoBlaze Code ROM – Block ROM just refuses to retire. Many designers are contains the software code to emulate using legacy code from previous projects, is more than 70% 8051 instructions. while others are actually writing new code. • Internal Address/Bus – The PicoBlaze The 8051 architecture was designed for smaller than peripheral bus is a 256-byte address ASIC fabric. It is not efficient in an space accessed by PicoBlaze I/O FPGA, resulting in excess logic usage with instructions. It allows the PicoBlaze marginal performance. competing soft-core processor to interface with RAM, FPGA microprocessor integration is a emulation peripherals, timers, and the solution for older 8051 products undergo- implementations – serial port. This bus is internal to the ing redesign to eliminate obsolesce, lower core and thus hidden from the user. costs, decrease component count, and without sacrificing increase overall performance. • Emulation Peripherals – Not all emu- The new FPGA-embedded PB8051 any of the performance lation tasks can be done in software designs allow you to take advantage of and still meet the performance existing in-house software tools and your requirements for your particular own architecture familiarity to quickly of this legacy part. application. Specialized hardware implement a finished design. The inte- assists the PicoBlaze code to perform grated PB8051 can be customized on the tasks that are time-consuming, on a critical execution path, or both. FPGA to exact requirements. implementation – which takes up more than three times as much FPGA A good example is the parity bit in the Processor Emulation fabric as the PB8051. The PicoBlaze PSW (program status word) register that Programmers have used microprocessor processor itself runs at a remarkable 40 reflects 8051 accumulator parity. This emulation for many years as a software MIPS using an 80 MHz clock. function must be performed for every development vehicle. It allows program- 8051 instruction executed, and would mers to write and test code on a develop- • Software Friendly – You can write C take several PicoBlaze instruction cycles ment platform before testing on target code or assembler code with your to perform. It is, therefore, done in hardware. present software development tools to hardware. This same concept can be practical generate programs. You can also run when the target microprocessor architec- legacy objects out of a 27C512 • Instruction Decode ROM – This is a ture does not lend itself to efficient imple- EPROM. key emulation peripheral that is used mentation and use of FPGA resources. • Easy Hardware – You can use VHDL to decode 8051 instructions to set The features of our PB8051 emulated or Verilog™ hardware description PicoBlaze routine locations and emu- processor include: languages to instantiate the 8051- lation parameters. Winterl 2004 Xcell Journal 00 1K x 16 256 x 8 Block ROM Instruction Emulation Decode ROM Program Code Interrupt RST_8051 PicoBlaze 8051 WR Data Emulation Peripherals RD 256 x 8 PSEN Block RAM INSTR_FETCH EXT_BUS_START Address Decode, Data, Signals EXT_BUS_HOLD SERIAL0_PRE12 Address P1_IN[7:0] Serial Port Address SERIAL2_PRE32 Decode P1_OUT[7:0] Address Decode, Data, Signals P3_IN[7:0] P3_OUT[7:0] TIME_PRE Timer EXT_DATA_IN[7:0] EXT_DATA_OUT[7:0] CLK EXT_ADDRESS[15:0] Internal RST Address/Data ROM_ADDRESS[15:0] Bus ROM_DATA[7:0] Figure 1 – PB8051 block diagram • Address Decode – A significant in very tight PicoBlaze assembler code, opti- • Scan Interrupts – This function deter- amount of the emulation peripheral mized for speed and efficiency. mines if an interrupt is pending, and if hardware is dedicated to simple The emulation program is divided into so, services it. An interrupt window is address decode of the PicoBlaze several segments: generated at the end of every emulated peripheral bus. This address space is instruction when required. for the PicoBlaze processor only and is • Instruction Fetch – An 8051 bus cycle insulated from the 8051 application. is simulated to fetch the next instruc- In addition to PicoBlaze code, Java™ tion from 8051 program memory (64 software utilities process symbols taken • Block RAM – 256 bytes are available Kb size), which may be on-chip block from PicoBlaze listings (.LOG files) into a to 8051 internal RAM and some 8051 RAM or off-chip EPROM (such as the ROM table. These .LOG files are used to registers. You can access this block 27C256). decode 8051 opcodes. RAM via 8051 instructions. This program also produces the .COE • Instruction Decode – Fetched instruc- • Serial Port and Timer – The actual files used by the Xilinx CORE tions are decoded to determine the 8051 timer and multi-mode serial port Generator™ system to create PicoBlaze addressing mode and operation. were best done in hardware instead of code ROM. All of this is transparent to trying to implement these functions in • Fetch Operands – Depending upon designers integrating with the PB8051. software. Clock prescaling inputs are the addressing mode, additional provided so that these functions can operands are fetched for the instruc- User Back-End Interface run at a clock rate independent of the tion from program memory, internal What gives the PB8051 its “hardware emulated system. RAM, or external RAM. flavor” is the user back-end interface, where you interface your logic design PicoBlaze Emulation Software • Instruction Execution – An instruction with the emulated 8051 processor. The A 1K x 16 block ROM holds the PicoBlaze performs the desired operation and back-end interface is part of the emula- code that performs the actual emulation. The updates emulated register contents, tion peripherals, controlled by the emulation program is carefully constructed including affected 8051 PSW flags. PicoBlaze platform. 00 Xcell Journal Winter 2004 What gives the PB8051 its “hardware flavor” is the user back-end interface, where you interface your logic design with the emulated 8051 processor. Just as the 8051 processor family has tional multiplexer circuitry is not needed. Test and Debug Considerations many derivatives to define port, function- If your entire design, including the 8051 We recommend you use design tools to ality, features, and pinout, the back-end program, resides on the FPGA, simply set quickly and easily test and debug your design. interface serves the same function. The the EXT_BUS_HOLD to “low” to take full The most useful tool will be an HDL simula- PB8051 has a back-end interface that advantage of running at clock speed. If you tor, such as Modeltech or Aldec programs. resembles the generic 8031, the ROM-less elect to use an off-chip EPROM or have Most problems and bugs can be solved at the version of the 8051. slow peripherals, wait states can be inserted behavioral level. For interactive debugging, Roman-Jones Inc. customizes back-end by asserting EXT_BUS_HOLD at “high.” the Xilinx ChipScope™ integrated logic ana- interfaces to meet your exact 8051 needs, One of our reference designs illustrates wait lyzer has proved to be the tool of choice. At such as removing an unused serial port or state generation. the current time, no source code debugger adding an I2C port to emulate the 80C652 tools are available for the PB8051. derivative. Xilinx Implementation Considerations There are few implementation considera- Designer’s Learning Curve Designing with the PB8051 tions other than the need to place the Designers should have some experience in Incorporating the PB8051 into the rest of PB8051 design netlist into your project 8051 hardware/software and FPGA design your design is easy, because it comes with ref- directory and instantiate it as a compo- before attempting to consolidate the two. erence designs and examples of Xilinx inte- nent in your VHDL or Verilog design; The PB8051 core is designed for ease of grated software design (ISE) projects.
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