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Towards an Embedded Board-Level Tester Study of a Configurable Test Processor

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Towards an Embedded Board-Level Tester Study of a Configurable Test Processor Towards an Embedded Board-Level Tester Study of a Configurable Test Processor Dissertation Zur Erlangung des akademischen Grades Doktor-Ingenieur (Dr.-Ing) vorgelegt in der Fakultät für Informatik und Automatisierung der Technischen Universität Ilmenau von Herrn Ing. Jorge Hernán Meza Escobar, geboren am 18.01.1984 in Cali, Kolumbien Datum der Einrichtung: 15.06.2016 (vorliegende Revision vom 29.11.2016) Datum der Verteidigung: 21.11.2016 Gutachter: 1. Prof. Dr.-Ing. habil. Andreas Mitschele-Thiel, Technische Universität Ilmenau 2. Prof. Dr.-Ing. Sebastian Michael Sattler, Friedrich-Alexander Universität Erlangen-Nürnberg 3. Prof. Dr. Raimund-Johannes Ubar, Tallinn University of Technology urn:nbn:de:gbv:ilm1-2016000605 Acknowledgments First, I would like to express my deepest and sincere gratitude to my advisors Dr.-Ing. Heinz-Dietrich Wuttke and Prof. Dr.-Ing. habil. Andreas Mitschele-Thiel. Thank you for letting me be part of the ICS group, for the excellent scientific guidance of my thesis, and for your constructive reviews, suggestions, and discussions, which significantly improved this work. I would also like to express my gratitude and appreciation to my whole family, especially to my parents Jorge and Leonor, my brother Kike, and my sister Leonor. Thank you for your support and for encouraging me to pursue my dreams. Special thanks go to Pamela for all her love, support, and encouragement. I would also like to thank my cousin Grace Lewis for her grammar and text corrections. I would like to thank the HW/SW systems group, especially Steffen Ostendorff and Jörg Sachße. The embedded board-level tester and the test processor would surely not be able to work without your contributions! My special thanks go to Dr.-Ing. Karsten Henke and all ICS group members. Thanks for having an open ear for discussing various aspects of my theoretical and practical work. I would like to thank the organizational and technical staff, Nicole Sauer, Nadine Wolf, and specially Jürgen Schmidt. I would also like to thank the reviewers for investing their time in reading and evaluating this work. Finally, I would like to express my gratitude and recognize that this research would not have been possible without the financial assistance of the Thüringer Aufbaubank (TAB), the Zentrales Innovationsprogram Mittelstand (ZIM), and the TU Ilmenau. I am also very thankful to Göpel Electronic and Thomas Wenzel for the opportunity to develop this research with the collaboration of an industry partner. III Abstract The demand for electronic systems with more features, higher performance, and less power consumption increases continuously. This is a real challenge for design and test engineers because they have to deal with electronic systems with ever-increasing complexity maintaining production and test costs low and meeting critical time to market deadlines. For a test engineer working at the board-level, this means that manufacturing defects must be detected as soon as possible and at a low cost. However, the use of classical test techniques for testing modern printed circuit boards is not sufficient, and in the worst case these techniques cannot be used at all. This is mainly due to modern packaging technologies, a high device density, and high operation frequencies of modern printed circuit boards. This leads to very long test times, low fault coverage, and high test costs. This dissertation addresses these issues and proposes an FPGA-based test approach for printed circuit boards. The concept is based on a configurable test processor that is temporarily implemented in the on-board FPGA and provides the corresponding mechanisms to communicate to external test equipment and co-processors implemented in the FPGA. This embedded test approach provides the flexibility to implement test functions either in the external test equipment or in the FPGA. In this manner, tests are executed at-speed increasing the fault coverage, test times are reduced, and the test system can be adapted automatically to the properties of the FPGA and devices located on the board. An essential part of the FPGA-based test approach deals with the development of a test processor. In this dissertation the required properties of the processor are discussed, and it is shown that the adaptation to the specific test scenario plays a very important role for the optimization. For this purpose, the test processor is equipped with configuration parameters at the instruction set architecture and microarchitecture level. Additionally, an automatic generation process for the test system and for the computation of some of the processor’s configuration parameters is proposed. The automatic generation process uses as input a model known as the device under test model (DUT-M). In order to evaluate the entire FPGA-based test approach and the viability of a processor for testing printed circuit boards, the developed test system is used to test interconnections to two different devices: a static random memory (SRAM) and a liquid crystal display (LCD). Experiments were conducted in order to determine the resource utilization of the processor and FPGA-based test system and to measure test time when different test functions are implemented in the external test equipment or the FPGA. It has been shown V VI Abstract that the introduced approach is suitable to test printed circuit boards and that the test processor represents a realistic alternative for testing at board-level. Zusammenfassung Der Bedarf an elektronischen Systemen mit zusätzlichen Merkmalen, höherer Leistung und geringerem Energieverbrauch nimmt ständig zu. Dies stellt eine erhebliche Herausforderung für Entwicklungs- und Testingenieure dar, weil sie sich mit elektronischen Systemen mit einer steigenden Komplexität zu befassen haben. Außerdem müssen die Herstellungs- und Testkosten gering bleiben und die Produkteinführungsfristen so kurz wie möglich gehalten werden. Daraus folgt, dass ein Testingenieur, der auf Leiterplatten-Ebene arbeitet, die Herstellungsfehler so früh wie möglich entdecken und dabei möglichst niedrige Kosten verursachen soll. Allerdings sind die klassischen Testmethoden nicht in der Lage, die Anforderungen von modernen Leiterplatten zu erfüllen und im schlimmsten Fall können diese Testmethoden überhaupt nicht verwendet werden. Dies liegt vor allem an modernen Gehäuse-Technologien, der hohen Bauteildichte und den hohen Arbeitsfrequenzen von modernen Leiterplatten. Das führt zu sehr langen Testzeiten, geringer Testabdeckung und hohen Testkosten. Die Dissertation greift diese Problematik auf und liefert einen FPGA-basierten Testansatz für Leiterplatten. Das Konzept beruht auf einem konfigurierbaren Testprozessor, welcher im On-Board-FPGA temporär implementiert wird und die entsprechenden Mechanismen für die Kommunikation mit der externen Testeinrichtung und Co-Prozessoren im FPGA bereitstellt. Dadurch ist es möglich Testfunktionen flexibel entweder auf der externen Testeinrichtung oder auf dem FPGA zu implementieren. Auf diese Weise werden Tests at- speed ausgeführt, um die Testabdeckung zu erhöhen. Außerdem wird die Testzeit verkürzt und das Testsystem automatisch an die Eigenschaften des FPGAs und anderer Bauteile auf der Leiterplatte angepasst. Ein wesentlicher Teil des FPGA-basierten Testansatzes umfasst die Entwicklung eines Testprozessors. In dieser Dissertation wird über die benötigten Eigenschaften des Prozessors diskutiert und es wird gezeigt, dass die Anpassung des Prozessors an den spezifischen Testfall von großer Bedeutung für die Optimierung ist. Zu diesem Zweck wird der Prozessor mit Konfigurationsparametern auf der Befehlssatzarchitektur-Ebene und Mikroarchitektur-Ebene ausgerüstet. Außerdem wird ein automatischer Generierungsprozess für die Realisierung des Testsystems und für die Berechnung einer Untergruppe von Konfigurationsparametern des Prozessors vorgestellt. Der automatische Generierungsprozess benutzt als Eingangsinformation ein Modell des Prüflings (device under test model, DUT-M). VII VIII Zusammenfassung Das entwickelte Testsystem wurde zum Testen von Leiterplatten für Verbindungen zwischen dem FPGA und zwei Bauteilen verwendet, um den FPGA-basierten Testansatz und die Durchführbarkeit des Testprozessors für das Testen auf Leiterplatte-Ebene zu evaluieren. Die zwei Bauteile sind ein Speicher mit direktem Zugriff (static random-access memory, SRAM) und eine Flüssigkristallanzeige (liquid crystal display, LCD). Die Experimente wurden durchgeführt, um den Ressourcenverbrauch des Prozessors und Testsystems festzustellen und um die Testzeit zu messen. Dies geschah durch die Implementierung von unterschiedlichen Testfunktionen auf der externen Testeinrichtung und dem FPGA. Dadurch konnte gezeigt werden, dass der FPGA-basierte Ansatz für das Testen von Leiterplatten geeignet ist und dass der Testprozessor eine realistische Alternative für das Testen auf Leiterplatten-Ebene ist. Table of Contents List of Tables ................................................................................ XIII List of Figures ............................................................................... XV Acronyms..................................................................................... XVII 1 Introduction ................................................................................ 1 1.1 Motivation ........................................................................................................... 1 1.2 Problem statement and research questions ....................................................
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