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Customer PPT Rev 30
LATTICE SEMICONDUCTOR The Leader in Low Power, Small Form Factor, Secure FPGAs First Quarter, 2019 Lattice Semiconductor (NASDAQ: LSCC) [1] Safe Harbor This presentation contains forward-looking statements that involve estimates, assumptions, risks and uncertainties, including all information under the heading 1Q 19 Business Outlook. Lattice believes the factors identified below could cause our actual results to differ materially from the forward-looking statements. Factors that may cause our actual results to differ materially from the forward-looking statements in this presentation include global economic uncertainty, overall semiconductor market conditions, market acceptance and demand for our new and existing products, the Company's dependencies on its silicon wafer suppliers, the impact of competitive products and pricing, and technological and product development risks. In addition, actual results are subject to other risks and uncertainties that relate more broadly to our overall business, including those risks more fully described in Lattice’s filings with the SEC including its annual report on Form 10-K for the fiscal year ended December 30, 2017 and its quarterly filings on Form 10-Q. Certain information in this presentation is identified as having been prepared on a non-GAAP basis. Management uses non- GAAP measures to better assess operating performance and to establish operational goals. Non-GAAP information should not be viewed by investors as a substitute for data prepared in accordance with GAAP. You should not unduly rely on forward-looking statements because actual results could differ materially from those expressed in any forward- looking statements. In addition, any forward-looking statement applies only as of the date on which it is made. -
FPGA Design Security Issues: Using the Ispxpga® Family of Fpgas to Achieve High Design Security
White Paper FPGA Design Security Issues: Using the ispXPGA® Family of FPGAs to Achieve High Design Security December 2003 5555 Northeast Moore Court Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 FAX: (503) 268-8556 www.latticesemi.com WP1010 Using the ispXPGA Family of FPGAs to Lattice Semiconductor Achieve High Design Security Introduction In today’s complex systems, FPGAs are increasingly being used to replace functions traditionally performed by ASICs and even microprocessors. Ten years ago, the FPGA was at the fringe of most designs; today it is often at the heart. With FPGA technology taking gate counts into the millions, a trend accelerated by embedded ASIC-like functionality, the functions performed by the FPGA make an increasingly attractive target for piracy. Many tech- niques have been developed over the years to steal designs from all types of silicon chips. Special considerations must now be made when thinking about protecting valuable Intellectual Property (IP) implemented within the FPGA. The most common FPGA technology in use today is SRAM-based, which is fast and re-configurable, but must be re-configured every time the FPGA is powered up. Typically, an external PROM is used to hold the configuration data for the FPGA. The link between the PROM and FPGA represents a significant security risk. The configuration data is exposed and vulnerable to piracy while the device powers up. Using a non-volatile-based FPGA eliminates this security risk. Traditionally, non-volatile FPGAs were based on Antifuse technology that is secure, but very expensive to use due to its one-time programmability and higher manufacturing costs. -
Sstic-2021-Actes.Pdf
Préface Mercredi 2 juin 2021, 8 heures du matin. Sous perfusion de café, les yeux à peine entrouverts, je suis avec le reste du comité d’organisation (CO), qui est sur les rangs et veille aux derniers détails, vérifiant que la guicheteuse et les lecteurs de badge fonctionnent. Pendant ce temps, certains irréductibles sont déjà dehors, malgré le crachin breton, prêts à se ruer pour pouvoir découvrir en premier les goodies et s’installer confortablement dans l’amphi, à leur place favorite, pour feuilleter les actes et lire la préface. On ouvre les portes, c’est parti pour le 19e SSTIC ! Fondu. Huit cents personnes dans l’amphi face à nous, je vérifie avec l’orateur invité qui fait l’ouverture que tout est prêt. Avec le trac, les spots qui m’éblouissent, je m’avance pour prononcer quelques mots et lancer la conférence... Et dire qu’il y a environ un tiers de nouveaux ! Fondu. Petit tour en régie, pour discuter avec les techniciens du Couvent et s’assurer que le streaming se passe bien. Oups, on me dit sèchement de m’éloigner de la caméra ; apparemment, les talkies-walkies qui assurent la liaison avec le reste du CO, éparpillé entre le premier rang et l’accueil, font trembler les aimants du stabilisateur... Fondu. Après la présentation des résultats du challenge, une session de rumps réussie où il a fallu courir dans l’amphi pour apporter le micro, nous voilà dans le magnifique cloître du Couvent, sous un soleil bienvenu. Les petits fours sont excellents et je vois, à l’attroupement qui se forme rapidement, que le stand foie gras vient d’ouvrir. -
USB 3.0 Promoter Group Defines Authentication Protocol for USB Type-C™
PRESS RELEASE CONTACTS: Brad Saunders Liz Nardozza USB 3.0 Promoter Group USB-IF PR +1 503-264-0817 +1 503-619-5224 [email protected] [email protected] USB 3.0 Promoter Group Defines Authentication Protocol for USB Type-C™ Specification defines policy for product OEMs to mitigate risks from non-compliant devices Shenzhen, China and Beaverton, OR, USA – April 13, 2016 – The USB 3.0 Promoter Group today announced the USB Type-C™ Authentication specification, defining cryptographic-based authentication for USB Type-C™ chargers and devices. Using this protocol, host systems can confirm the authenticity of a USB device or USB charger, including such product aspects as the descriptors/capabilities and certification status. All of this happens right at the moment a wired connection is made – before inappropriate power or data can be transferred. USB Type-C™ Authentication empowers host systems to protect against non-compliant USB Chargers and to mitigate risks from maliciously embedded hardware or software in USB devices attempting to exploit a USB connection. For a traveler concerned about charging their phone at a public terminal, their phone can implement a policy only allowing charge from certified USB chargers. A company, tasked with protecting corporate assets, can set a policy in its PCs granting access only to verified USB storage devices. “USB is well-established as the favored choice for connecting and charging devices,” said Brad Saunders, USB 3.0 Promoter Group Chairman. “In support of the growing USB Type-C ecosystem, we anticipated the need for a solution extending the integrity of the USB interface. -
Universal Serial Bus Type-C Cable and Connector Specification
Release 1.3 - 1 - USB Type-C Cable and July 14, 2017 Connector Specification Universal Serial Bus Type-C Cable and Connector Specification Release 1.3 July 14, 2017 Copyright © 2017 USB 3.0 Promoter Group. All rights reserved. Release 1.3 - 2 - USB Type-C Cable and July 14, 2017 Connector Specification Copyright © 2014-2017, USB 3.0 Promoter Group: Apple Inc., Hewlett-Packard Inc., Intel Corporation, Microsoft Corporation, Renesas, STMicroelectronics, and Texas Instruments All rights reserved. NOTE: Adopters may only use the USB Type-C™ cable and connector to implement USB or third party functionality as expressly described in this Specification; all other uses are prohibited. LIMITED COPYRIGHT LICENSE: The USB 3.0 Promoters grant a conditional copyright license under the copyrights embodied in the USB Type-C Cable and Connector Specification to use and reproduce the Specification for the sole purpose of, and solely to the extent necessary for, evaluating whether to implement the Specification in products that would comply with the specification. Without limiting the foregoing, use of the Specification for the purpose of filing or modifying any patent application to target the Specification or USB compliant products is not authorized. Except for this express copyright license, no other rights or licenses are granted, including without limitation any patent licenses. In order to obtain any additional intellectual property licenses or licensing commitments associated with the Specification a party must execute the USB 3.0 Adopters Agreement. NOTE: By using the Specification, you accept these license terms on your own behalf and, in the case where you are doing this as an employee, on behalf of your employer. -
Handoutshandouts
HandoutsHandouts FPGA-related documents 1. Introduction to Verilog, P. M. Nyasulu and J. Knight, Carleton University, 2003 (Ottawa, Canada). 2. Quick Reference for Verilog HDL, R. Madhavan, AMBIT Design Systems, Inc, Automata Publishing Company, 1995 (San Jose, CA). Project-related documents 3. Project Guidelines and Project Specifications. (I’ll hand these out in lab) IntroductionIntroduction toto FPGAsFPGAs Outline: 1. What’s an FPGA ? Æ logic element “fabric”, i.e. logic gates + memory + clock trigger handling. 2. What’s so good about FPGAs ? Æ FPGA applications and capabilities Æ FPGAs for physicists 3. How do you program an FPGA ? Æ Intro to Quartus II Æ Schematic design Æ Verilog HDL design WhatWhat’’ss anan FPGAFPGA An FPGA is: - a Field Programmable Gate Array. - a programmable breadboard for digital circuits on chip. The FPGA consists of: - programmable Logic Elements (LEs). - programmable interconnects. - custom circuitry (i.e. multipliers, phase- lock loops (PLL), memory, etc …). Programmable Programmable Interconnects Logic [Figure adapted from Low Energy FPGAs – Architecture and Design, by V. George and J. M. Rabaey, Kluwer Academic Publishers, Boston (2001).] LogicLogic ElementElement (LE)(LE) An FPGA consists of a giant array of interconnected logic elements (LEs). The LEs are identical and consist of inputs, a Look-Up Table (LUT), a little bit of memory, some clock trigger handling circuitry, and output wires. global LUTLUT inputs inputs outputs local outputs MemoryMemory local clock (a few bits) CLOCK triggers signals feedback Figure: Architecture of a single Logic Element InterconnectInterconnect ArchitecturesArchitectures Row-Column Architecture Island Style Architecture Sea-of-Gates Architecture Hierarchical Architecture FPGAFPGA devicesdevices (I)(I) 2 primary manufacturers: 1. -
FPGA Design Guide
FPGA Design Guide Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 (503) 268-8000 September 16, 2008 Copyright Copyright © 2008 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine- readable form without prior written consent from Lattice Semiconductor Corporation. Trademarks Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), LSC, E2CMOS, Extreme Performance, FlashBAK, flexiFlash, flexiMAC, flexiPCS, FreedomChip, GAL, GDX, Generic Array Logic, HDL Explorer, IPexpress, ISP, ispATE, ispClock, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2, ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH, ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP, ispXPGA, ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2, LatticeECP2M, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, MACH, MachXO, MACO, ORCA, PAC, PAC-Designer, PAL, Performance Analyst, PURESPEED, Reveal, Silicon Forest, Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The Simple Machine for Complex Design, TransFR, UltraMOS, and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. ISP, Bringing the Best Together, and More -
USB Technical Overview Brad Saunders – USB-IF/USB PG Chair (Sponsored by Intel Corporation)
USB Technical Overview Brad Saunders – USB-IF/USB PG Chair (Sponsored by Intel Corporation) USB Developer Days 2017 Taipei, Taiwan October 24 – 25, 2017 USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 1 • System Level Overview • USB 3.2 Topic Agenda • USB Type-C™ • The Rest of the Story USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 2 Some Words of Caution … • Only design to official released versions of USB specifications • Developer presentations are intended to help familiarize you with the general characteristics of these specifications and provide design guidance • These presentations are not technically complete and should not be used as the sole basis for product designs • USB technology has evolved into highly complex and challenging designs • Always make use of certified product suppliers – silicon, connectors, etc. • Proper materials and manufacturing processes are increasingly more critical to making successful products • Submit your products for USB certification USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 3 Performance Power Delivers up to 10 Gbps x 2 – Delivers up to 100W – supporting all of your SuperSpeed USB Power power and charging for data transfer needs all your devices USB Delivery USB Type-C™ Cable & Connector Convenience Robust, slim connector with reversible plug orientation and cable direction USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 4 Major Components of USB Devices USB 2.0 USB 2.0 USB 2.0 xHCI USB -
FPGA Configuration Flash Memory AT17F32
Features • Programmable 33,554,432 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) • 3.3V Output Capability • 5V Tolerant I/O Pins • Program Support using the Atmel ATDH2200E System or Industry Third Party Programmers • In-System Programmable (ISP) via 2-wire Bus • Simple Interface to SRAM FPGAs • Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, APEX™ Devices, FPGA Stratix™, Lattice Semiconductor® (ORCA®) FPGAs, Spartan®, Virtex™ FPGAs • Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Configuration • Low-power CMOS FLASH Process • Available in 44-lead PLCC Package Flash Memory • Emulation of Atmel’s AT24CXXX Serial EEPROMs • Low-power Standby Mode • Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System AT17F32 Reconfiguration • Fast Serial Download Speeds up to 33 MHz • Endurance: 10,000 Write Cycles Typical • LHF Package Available (Lead and Halide Free) 1. Description The AT17F Series of In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17F Series device is packaged in the 44-lead PLCC, see Table 1- 1. The AT17F Series Configurator uses a simple serial-access procedure to configure one or more FPGA devices. The AT17F Series Configurators can be programmed with industry-standard program- mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. Table 1-1. AT17F Series Packages Package AT17F32 44-lead PLCC Yes 3393C–CNFG–6/05 2. Pin Configuration 44-lead PLCC NC CLK NC NC DATA PAGE_EN VCC NC NC SER_EN NC 6 5 4 3 2 1 NC 7 44 43 42 41 3940 NC NC 8 38 NC NC 9 37 NC NC 10 36 NC NC 11 35 NC NC 12 34 NC NC 13 33 NC NC 14 32 NC NC 15 31 NC NC 16 30 NC NC 17 29 READY 18 19 20 21 22 23 24 25 26 27 28 CE NC NC NC NC NC GND CEO/A2 RESET/OE PAGESEL0 PAGESEL1 2 AT17F32 3393C–CNFG–6/05 AT17F32 3. -
In Re: Lattice Semiconductor Corporation Securities Litigation 04
LERACH COUGHLIN STOIA GELLER RUDMAN & ROBBINS LLP WILLIAM S. LERACH [email protected] DARREN J. ROBBINS [email protected] 401 B Street, Suite 1600 San Diego, CA 92101 Telephone: 619/231-1058 619/231-7423 (fax) DENNIS J. HERMAN [email protected] 100 Pine Street, Suite 2600 San Francisco, CA 94111 Telephone: 415/288-4545 415/288-4534 (fax) TAMARA J. DRISCOLL [email protected] 700 Fifth Avenue, Suite 5600 Seattle, WA 98104 Telephone: 206/749-5544 206/749-9978 (fax) Lead Counsel for Plaintiffs [Additional counsel appear on signature page.] UNITED STATES DISTRICT COURT DISTRICT OF OREGON In re LATTICE SEMICONDUCTOR CORP. CV-04-01255-HU (Consolidated Cases) SECURITIES LITIGATION CLASS ACTION This Document Relates To: CONSOLIDATED CLASS ACTION ALL ACTIONS. COMPLAINT FOR VIOLATION OF THE FEDERAL SECURITIES LAWS [Caption continued on following page.] DEMAND FOR JURY TRIAL CONSOLIDATED CLASS ACTION COMPLAINT FOR VIOLATION OF THE FEDERAL SECURITIES LAWS AUTUMN PARTNERS, LLC, Individually Case No. CV-04-01255-HU and On Behalf of Itself and All Others Similarly Situated, CLASS ACTION Plaintiff, vs. LATTICE SEMICONDUCTOR CORP., CYRUS Y. TSUI, STEPHEN A. SKAGGS, STEVEN A. LAUB and RONALD HOYT, Defendants. CONSOLIDATED CLASS ACTION COMPLAINT FOR VIOLATION OF THE FEDERAL SECURITIES LAWS TABLE OF CONTENTS Page I. INTRODUCTION............................................................................................................... 1 II. JURISDICTION AND VENUE..........................................................................................6 -
USB-IF Announces Publication of USB4™ Specification Specification Now Available for Download on USB-IF Website; Doubles Bandwidth to Extend USB Type-C® Performance
DEVELOPER UPDATE CONTACT: Joe Balich USB-IF PR +1 503-619-4113 [email protected] USB-IF Announces Publication of USB4™ Specification Specification now available for download on USB-IF website; doubles bandwidth to extend USB Type-C® performance Beaverton, OR, USA – September 3, 2019 – USB Implementers Forum (USB-IF), the support organization for the advancement and adoption of USB technology, today announced the publication of the USB4™ specification, a major update to deliver the next-generation USB architecture that complements and builds upon the existing USB 3.2 and USB 2.0 architectures. The USB4 architecture is based on the Thunderbolt™ protocol specification recently contributed by Intel Corporation to the USB Promoter Group. It doubles the maximum aggregate bandwidth of USB and enables multiple simultaneous data and display protocols. The development of the USB4 specification was first announced in March 2019 by the USB Promoter Group. It is now officially published by USB-IF and available for download at www.usb.org. Key characteristics of the USB4 solution include: • Two-lane operation using existing USB Type-C® cables and up to 40Gbps operation over 40Gbps certified cables • Multiple data and display protocols that efficiently share the maximum aggregate bandwidth • Backward compatibility with USB 3.2, USB 2.0 and Thunderbolt 3 As the USB Type-C connector has evolved into the role as the external display port of many host products, the USB4 specification provides the host the ability to optimally scale allocations for display data flow. Even as the USB4 specification introduces a new underlying protocol, compatibility with existing USB 3.2, USB 2.0 and Thunderbolt 3 hosts and devices is supported; the resulting connection scales to the best mutual capability of the devices being connected. -
USB Logo Usage Guidelines
EXHIBIT P USB Logo Usage Guidelines 12806942.2 USB Logo Usage Guidelines USB Performance-only Packaging, Cable and Port Logos USB Type-CTM Charging Trident Logos Certified USB Charger Logos USB-IF Word Marks USB Type-CTM USB-CTM © 2000-2018 USB Implementers Forum, Inc. (USB-IF). All rights reserved. USB Logo Usage Guidelines Introduction 2 The Universal Serial Bus (USB) has gone beyond its original intent to connect peripherals to PCs and is now a dominate standard in the interconnect market. USB can be found everywhere from PCs to consumer electronics to mobile devices. Because of its ease of use, speed and expandability, USB is the preferred connection for many consumers. This presents a continued market opportunity for the future. In order to realize this opportunity, USB products must continue to enhance the consumers' experience through high quality and ease of use. That's why USB Implementers Forum, Inc. (USB-IF) developed trademark-protected USB Logo(s), SuperSpeed USB Logo(s), SuperSpeed USB 10 Gbps Logo(s), USB Type-CTM Charging Trident Logo(s), the Certified USB Charger Logo(s), and the Certified USB Fast Charger Logo(s) for use by qualified parties. To qualify for the right to display these logos, products must pass the specified USB-IF compliance testing for product quality. © 2000-2018 USB Implementers Forum, Inc. (USB-IF). All rights reserved. USB Logo Usage Guidelines Table of Contents 3 Logos and Word Marks 5 Logo Usage 19 Basic-Speed USB Versions Hi-Speed USB Versions SuperSpeed USB Version SuperSpeed USB 10 Gbps Version SuperSpeed USB Trident SuperSpeed USB 10 Gbps Trident USB Type-CTM Charging Trident Logos Certified USB Charger Logo Certified USB Fast Charger Logo Logo Color 28 Logo Don’ts 38 Layout 41 Packaging Collateral Advertisements Manuals Art Files 44 © 2000-2018 USB Implementers Forum, Inc.