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USB Technical Overview Brad Saunders – USB-IF/USB PG Chair (Sponsored by Intel Corporation)

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USB Technical Overview Brad Saunders – USB-IF/USB PG Chair (Sponsored by Intel Corporation) USB Technical Overview Brad Saunders – USB-IF/USB PG Chair (Sponsored by Intel Corporation) USB Developer Days 2017 Taipei, Taiwan October 24 – 25, 2017 USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 1 • System Level Overview • USB 3.2 Topic Agenda • USB Type-C™ • The Rest of the Story USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 2 Some Words of Caution … • Only design to official released versions of USB specifications • Developer presentations are intended to help familiarize you with the general characteristics of these specifications and provide design guidance • These presentations are not technically complete and should not be used as the sole basis for product designs • USB technology has evolved into highly complex and challenging designs • Always make use of certified product suppliers – silicon, connectors, etc. • Proper materials and manufacturing processes are increasingly more critical to making successful products • Submit your products for USB certification USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 3 Performance Power Delivers up to 10 Gbps x 2 – Delivers up to 100W – supporting all of your SuperSpeed USB Power power and charging for data transfer needs all your devices USB Delivery USB Type-C™ Cable & Connector Convenience Robust, slim connector with reversible plug orientation and cable direction USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 4 Major Components of USB Devices USB 2.0 USB 2.0 USB 2.0 xHCI USB 2.0 USB 2.0 C USB PD - USB 3.2 USB 3.2 USB 3.2 USB PD USB Device USB PD USB PD Type-C Device USB Class USB PD Type-C Drivers USB USB USB Type USB USB PD Type-C Type-C USB Type-C Device HUB HOST HUB USB Type-C Charger USB 2.0 xHCI USB 2.0 Device USB 3.1 USB 2.0 USB 2.0 USB 2.0 Device USB 3.1 USB 2.0 Class USB 3.1 Device HUB Drivers HUB BC 1.2 Charger Legacy Connectors Legacy HOST SuperSpeed USB USB 2.0 only USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 5 Base Specifications Enabling Specifications Applications Note: this illustration is not comprehensive of all USB specs. USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 6 USB Device Class Specifications Major Application Classes Others • Audio renewed focus • Billboard • • Content Security Communications • Debug • MBIM (Mobile Broadband) • Device Firmware Upgrade • Display renewed focus • IrDA • HID (Human Interface Device) • Media Transport Protocol • PID (Physical Interface Device) • Monitor Control • Image • Personal Health Care • Mass Storage • Power • Printer • Smart Card • Test & Measurement • Video • USB Type-C Bridge USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 7 • System Level Overview • USB 3.2 Topic Agenda • USB Type-C™ • The Rest of the Story USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 8 USB 3.1 – Significant Updates since last year • U1 Minimum Residency Time • 3 µs specified to allow a port sufficient time to complete entry into U1 and get ready for U1 exit • 60 µs LFPS EI Timer not required in certain exit conditions for a SuperSpeedPlus port when switching to SS operation • Allows SSP ports to be more tolerant of some popular but non-compliant legacy devices • Appendix E (Re-timer) Update • Added Warm Reset, defined Cascaded and Sequential Bit-Level Re-timing, added jitter transfer function requirements, other general clean-up • Receiver AC Coupling Capacitor Option • Useful for ESD/EOS protection and removing undesired bias level on Rx side USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 9 Introducing USB 3.2 • Enables SuperSpeed USB to fully utilize USB Type-C cable plug/wires • Doubles performance with dual-lane operation • Same signaling rates (5 Gbps / 10 Gbps) and View into the plug encoding allows use of existing cables • USB 3.2 supersedes USB 3.1 • USB 3.2 single-lane operation equates to USB 3.1 Lane 1 Lane 0 • USB 3.1 Legacy Cable and Connector Dual-lane operation specifications extracted and published separately Note: Related branding, certification logos and icons will be announced when available USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 10 USB 3.2 – Targeted Applications 10 Gbps performance at Over 2 GB/sec 5 Gbps cable lengths transfer rates Longer Storage Reach Hubs & Display 10 Gbps x 2 enabling 8K60/4K120 with DSC, Docks multiple 5 and 10 Gbps 4K60 w/o DSC downstream ports USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 11 USB 3.2 – Approach • USB 3.2 updates focus on link layer definition of USB as needed to establish the x2 operation • PHY design reuse was a high priority – both 5 Gbps and 10 Gbps rates supported • Minimal impact to the other layers – Protocol, Framework, Hub, etc. • Significant buffer size impact to Hub implementations • x2 operation only applies to USB Type-C cables and connectors • Just works with existing software (OS/drivers) • Beyond doubling bandwidth through lane bonding, the solution targeted maintaining parity with regard to USB 3.1 error performance, channel and power efficiency USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 12 USB 3.2 – Dual-lane Requirements Summary (1 of 2) • Configuration Lane (Lane 0) • Established by USB Type-C CC decoding • All LFPS/LBPM signaling/messaging only transits over this lane • Ux Exit functionality only required in the Configuration Lane’s receiver • Data Striping • Applies to data blocks but control blocks are duplicated • Transmission of packets and link commands may be initiated on either lane • Data Scrambling • Operates on a per lane basis with different required seed values by lane USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 13 USB 3.2 – Dual-lane Requirements Summary (2 of 2) • Ordered Sets • Transmitted simultaneously on each lane within skew constraints • TS1 and TS2 transmit/receive sequences proceed in sync across both lanes • Clock offset compensation using SKP performed on a per lane basis • Lane-to-Lane Skew • Maximum Skew of 6400 ps allowed at Receiver input • Compliance Patterns • Transmitted independently on each negotiated lane • Pattern advances in sync on both lanes when Ping.LFPS received • Receiver Detect • Required only on the Configuration Lane • Receiver Loopback • Done on a per lane basis USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 14 USB 3.2 – Gen and Multi-lane Interoperability • USB SuperSpeed Data Rates – Gen 1 (5 Gbps) and Gen 2 (10 Gbps) • Lane count – Single lane (x1) and Dual lane (x2) USB 3.13.2 DFP Gen 1x1Gen Gen1 1x2 Gen 2x1Gen Gen2 2x2 Gen 1x1 Gen 1x1 Gen 1x1 Gen 1x1 Gen 1x1 Gen 1 Gen 1 Gen 1 Gen 1x2 Gen 1x1 Gen 1x2 Gen 1x1 Gen 1x2 USB 3.13.2 UFP Gen 2x1 Gen 1x1 Gen 1x1 Gen 2x1 Gen 2x1 Gen 2 Gen 1 Gen 2 Gen 2x2 Gen 1x1 Gen 1x2 Gen 2x1 Gen 2x2 Fallback Order USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 15 USB 3.2 – Physical Layer Updates (Chapter 6) • Lane Polarity inversion is done on a per lane basis • Multi-lane Requirements • Lane Numbering, Data Striping, etc. • Updated SuperSpeed USB Electrical Test Points definitions • Improved consistency with similar high-speed specifications • New or updated figures and tables USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 16 USB 3.2 – Link Layer Updates (Chapter 7) • Most significant areas of change in LTSSM: • Polling (PortMatch, PortConfig, Active, Configuration) • Recovery (Active, Configuration) • Error Types and Recovery updated to comprehend lane count • Gen 2x2 Block Header Errors • Single-bit error correction option available if PHY associates block headers • PHY LBPM Definition • Adjusted to comprehend lane count • Rx Header Buffer Credits • Increased to seven for Gen 2x2 to sustain burst performance USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 17 USB 3.2 – Protocol Layer Updates (Chapter 8) • LDM (Link Delay Measurement) Link Delay • LDM transmission time varies by speed and lane count • Enhanced SuperSpeed Isochronous Transactions • Host ability to accept and send DPs per service vary by speed and lane count • Host Flexibility in Performing SuperSpeed Isochronous Transactions • Now aligned with SuperSpeedPlus – any size burst within the Max Burst Size of endpoints • Deprecated features and fields (now Reserved) • Bus Interval Adjustment Message • Bus Interval Adjustment Control field deprecated in Isochronous Transaction Packet • Smart Isochronous Scheduling Protocol • SSI, WPA, DBI, NBI fields deprecated in ACK Transaction Packet USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 18 USB 3.2 – Device Framework Updates (Chapter 9) • Bit 7 now reserved for all new USB base spec Descriptor Type definitions • SuperSpeedPlus Isochronous Endpoint Companion Descriptor • Bytes per Interval value varies by speed and lane count USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 19 USB 3.2 – Hub and Port Specifications (Chapter 10) • Downstream Flow Buffering • Buffering size varies by speed and lane count • Self-powered Hubs can now be powered via USB PD or USB Type-C Current • Port power rules updated • Added port labeling and positioning recommendations for hubs USB Developer Days – October 24 – 25, 2017 USB Implementers Forum © 2017 20 USB 3.2 – Bus Power Requirement (Chapter 11) • Now differentiated by single-lane or dual-lane operation Minimum Maximum Parameter
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