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ORCA® Synplicity® Interface Manual

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ORCA® Synplicity® Interface Manual Last Link Previous Next ORCA® Synplicity® Interface Manual For Use With Synplicity® Synplify® Version 6.2.4 or higher and ORCA 2002, and ispLEVER 2.0 and higher Technical Support Line: 1-800-LATTICE or 408-826-6002 (international) Version 2002 1 Last Link Previous Next Synplicity Interface Manual Synplicity, Synplify, Simply Better Synthesis, and the ’S’, ’Y’, ’N’ blocks logo are registered trademarks of Syn- plicity, Inc. EPIC and Timing Wizard are trademarks of Xilinx, Inc. Exemplar is a trademark of Exemplar Logic, Inc. ORCA and Scuba are registered trademarks of Lattice Semiconductor Corporation. Synopsys is a trademark of Synopsys, Inc. Verilog and Verilog-XL are registered trademarks of the Cadence Design Systems, Inc. Viewlogic and ViewSim are registered trademarks of Viewlogic Systems,Inc. All other brands or product names are the trademarks or registered trademarks of their respective owners. Lattice Semiconductor Corporation Field Programmable Gate Arrays 5555 NE Moore Court Hillsboro, OR 97124 Copyright © 2004, Lattice Semiconductor Corporation, All rights reserved. 2 ORCA Foundry/Syplicity Interface Last Link Previous Next GO TO ¾ ORCA Foundry/Synplicity Interface Table of CONTENTS Contents OVERVIEW .................................................................................................................1 Cover Page SOFTWARE REQUIREMENTS ..............................................................................1 SETTING THE DESIGN ENVIRONMENT ..........................................................2 ORCA Web Site Environment Variables ..................................................................................2 ORCA/SYNPLIFY LIBRARY FILES .....................................................................3 ORCA FAQs DESIGN FLOW ...........................................................................................................5 Series 4 Synthesis Flow ................................................................................7 Tech Support DESIGN ENTRY .......................................................................................................10 SETTING TIMING CONSTRAINTS ....................................................................14 Index When to Set Timing Constraints ...............................................................14 Synplify Timing Attributes ........................................................................14 Synplify Timing Report ..............................................................................16 I/O BUFFER INSERTION .......................................................................................17 I/O Macrocell Instantiation ........................................................................17 Overriding the Default Padtype for Automatic I/O Insertion ...............22 Locking I/O Pins ..........................................................................................23 Locking I/O in the HDL File ..............................................................23 Locking I/O in the ORCA Preference File .......................................25 Placing Registers Near I/Os .......................................................................26 Bidirectional Buffer Insertion ....................................................................27 DESIGN EXAMPLES ..............................................................................................29 Designing with ORCA ................................................................................29 MACROCELL INSTANTIATION .........................................................................31 ORCA 2CA/2TA/2TB Macro Library Elements ....................................31 ORCA Series 3 Macro Library Elements ................................................32 ORCA Series 4 Macro Library Elements ................................................34 ORCA/Synplicity Interface i Contents Last Link Previous Next GO TO ¾ ORCA Foundry/Synplicity Interface Table of CONTENTS Contents Hard Macro Instantiation ............................................................................38 Cover Page SIMULATION OF NETLISTS GENERATED BY SYNPLIFY .......................40 DESIGN IMPLEMENTATION ...............................................................................41 ORCA Web Site DESIGN VERIFICATION .......................................................................................43 ORCA THE ORCA ENVIRONMENT in ispLEVER ......................................................44 FAQs Mapping the Design ....................................................................................44 Tech APPENDIX .................................................................................................................46 Support Memory Initialization .................................................................................46 Setting Initial Values in the in the HDL File ....................................46 Index Setting Initial RAM Values .................................................................47 Using GSR in ORCA Designs With Synplify .........................................51 Illegal Names/Characters in ORCA Design Flows ................................51 Programmable GSR Support (Series 3) ...................................................51 Passing Frequency Preferences (Series 3 and 4) .....................................53 ORCA/Synplicity Interface ii Contents Last Link Previous Next GO TO ¾ ORCA/Synplicity Interface Table of Contents Cover Page OVERVIEW ORCA This manual describes the Optimized Reconfigurable Cell Array (ORCA)® Library and Web Site the interface between the Synplicity® design tools and the ORCA place and route tools. Together, the tools provide a powerful and integrated high-level design environment for ORCA ORCA Field-Programmable Gate Arrays (FPGA). FAQs Note Tech Support Note that version numbers for the interface software are continually being updated with each release. Check with the vendor on version number and how it Index affects the file names or syntax that make it possible to perform tasks as they relate to creating designs with ORCA. Check with technical support with compatibility and support issues. SOFTWARE REQUIREMENTS The ORCA/Synplicity Interface is compatible with the following software: • Latest version of ispLEVER software with ORCA devices installed • Synplify version 7.3 or later ORCA/Synplicity Interface 1 Last Link Previous Next GO TO ¾ SETTING THE DESIGN ENVIRONMENT Table of Contents This section helps you customize your Synplicity environment for designing an ORCA FPGA. Cover Page Environment Variables ORCA Make sure you have installed the latest version of ispLEVER with ORCA devices Web Site installed and that the FOUNDRY environment variable is set. The FOUNDRY variable points to the ispFPGA (PC) or ispfpga (UNIX) directory. ORCA FAQs The variable should be set as follows: Tech $ setenv FOUNDRY <ispfpga_directory> Support Note Index Note that these variables are automatically set by the software and you should not have to manually set them. If for some reason, they are changed, this provides instruction for resetting them. ORCA/Synplicity Interface 2 Last Link Previous Next GO TO ¾ ORCA/SYNPLIFY LIBRARY FILES Table of Contents The following libraries are provided for the ORCA 2A FPGAs. These files are available in your synplcty/lib/lucent directory. Cover Page orca.vhd This VHDL file defines the ORCA components. In order to be able to directly instantiate ORCA library primitives in your VHDL design files, you will need to add the ORCA Web Site following statements in your VHDL design to access these components: ORCA library orca; FAQs use orca.orcacomp.all; Tech Support orca.v This Verilog® file defines the ORCA components for use with Verilog designs. Include this file at the top of the source file list when you want to directly instantiate Index ORCA library primitives in your verilog source. If you have version 7.3 or later of Synplify with ORCA Series 3 and Series 4 support, the library files have been renamed as below: orca2.vhd The VHDL library file for ORCA 2 components. For Synplify version 7.3 and later, if targeting the ORCA 2 architecture, add the following: library orca2; use orca2.orcacomp.all; orca3.vhd The VHDL library file for ORCA Series 3 components. For Synplify version 7.3 and later, if targeting the Series 3 architecture, add the following: library orca3; use orca3.orcacomp.all; orca4.vhd The VHDL library file for ORCA Series 4 components. For Synplify version 7.3 and later, if targeting the Series 4 architecture, add the following: ORCA/Synplicity Interface 3 Last Link Previous Next GO TO ¾ library orca4; use orca4.orcacomp.all; Table of Contents Cover The Verilog library files are now named orca2.v, orca3.v, and orca4.v for the respective Page architectures. Please contact Synplicity support in case of discrepancies. For updated library files for Verilog and VHDL in the ispLEVER environment, you can ORCA Web Site retrieve the files in the userware directory after ispLEVER installation. Refer to the complete paths below for PC and UNIX. ORCA Verilog header files: FAQs $FOUNDRY\userware\NT\4E_VERILOG_HEADERS\orca4_synplify.v Tech $FOUNDRY/userware/unix/4E_Verilog_Headers/orca4_synplify.v Support VHDL header files (also in same path): Index $FOUNDRY\userware\NT\4E_VERILOG_HEADERS\orca4_synplify.vhd $FOUNDRY/userware/unix/4E_Verilog_Headers/orca4_synplify.vhd Note There are many HDL source files available in the userware directory to ensure the successful instantiation
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