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ORCA® Synplicity® Interface Manual
For Use With Synplicity® Synplify® Version 6.2.4 or higher and ORCA 2002, and ispLEVER 2.0 and higher
Technical Support Line: 1-800-LATTICE or 408-826-6002 (international)
Version 2002 1 Last Link Previous Next
Synplicity Interface Manual
Synplicity, Synplify, Simply Better Synthesis, and the ’S’, ’Y’, ’N’ blocks logo are registered trademarks of Syn- plicity, Inc. EPIC and Timing Wizard are trademarks of Xilinx, Inc. Exemplar is a trademark of Exemplar Logic, Inc. ORCA and Scuba are registered trademarks of Lattice Semiconductor Corporation. Synopsys is a trademark of Synopsys, Inc. Verilog and Verilog-XL are registered trademarks of the Cadence Design Systems, Inc. Viewlogic and ViewSim are registered trademarks of Viewlogic Systems,Inc. All other brands or product names are the trademarks or registered trademarks of their respective owners.
Lattice Semiconductor Corporation Field Programmable Gate Arrays 5555 NE Moore Court Hillsboro, OR 97124 Copyright © 2004, Lattice Semiconductor Corporation, All rights reserved.
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GO TO ¾ ORCA Foundry/Synplicity Interface Table of CONTENTS Contents OVERVIEW ...... 1 Cover Page SOFTWARE REQUIREMENTS ...... 1
SETTING THE DESIGN ENVIRONMENT ...... 2 ORCA Web Site Environment Variables ...... 2 ORCA/SYNPLIFY LIBRARY FILES ...... 3 ORCA FAQs DESIGN FLOW ...... 5 Series 4 Synthesis Flow ...... 7 Tech Support DESIGN ENTRY ...... 10
SETTING TIMING CONSTRAINTS ...... 14 Index When to Set Timing Constraints ...... 14 Synplify Timing Attributes ...... 14 Synplify Timing Report ...... 16
I/O BUFFER INSERTION ...... 17 I/O Macrocell Instantiation ...... 17 Overriding the Default Padtype for Automatic I/O Insertion ...... 22 Locking I/O Pins ...... 23 Locking I/O in the HDL File ...... 23 Locking I/O in the ORCA Preference File ...... 25 Placing Registers Near I/Os ...... 26 Bidirectional Buffer Insertion ...... 27
DESIGN EXAMPLES ...... 29 Designing with ORCA ...... 29
MACROCELL INSTANTIATION ...... 31 ORCA 2CA/2TA/2TB Macro Library Elements ...... 31 ORCA Series 3 Macro Library Elements ...... 32 ORCA Series 4 Macro Library Elements ...... 34
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GO TO ¾ ORCA Foundry/Synplicity Interface Table of CONTENTS Contents Hard Macro Instantiation ...... 38 Cover Page SIMULATION OF NETLISTS GENERATED BY SYNPLIFY ...... 40
DESIGN IMPLEMENTATION ...... 41 ORCA Web Site DESIGN VERIFICATION ...... 43
ORCA THE ORCA ENVIRONMENT in ispLEVER ...... 44 FAQs Mapping the Design ...... 44
Tech APPENDIX ...... 46 Support Memory Initialization ...... 46 Setting Initial Values in the in the HDL File ...... 46 Index Setting Initial RAM Values ...... 47 Using GSR in ORCA Designs With Synplify ...... 51 Illegal Names/Characters in ORCA Design Flows ...... 51 Programmable GSR Support (Series 3) ...... 51 Passing Frequency Preferences (Series 3 and 4) ...... 53
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GO TO ¾ ORCA/Synplicity Interface Table of Contents
Cover Page OVERVIEW
ORCA This manual describes the Optimized Reconfigurable Cell Array (ORCA)® Library and Web Site the interface between the Synplicity® design tools and the ORCA place and route tools. Together, the tools provide a powerful and integrated high-level design environment for ORCA ORCA Field-Programmable Gate Arrays (FPGA). FAQs Note Tech Support Note that version numbers for the interface software are continually being updated with each release. Check with the vendor on version number and how it Index affects the file names or syntax that make it possible to perform tasks as they relate to creating designs with ORCA. Check with technical support with compatibility and support issues.
SOFTWARE REQUIREMENTS
The ORCA/Synplicity Interface is compatible with the following software:
• Latest version of ispLEVER software with ORCA devices installed • Synplify version 7.3 or later
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GO TO ¾ SETTING THE DESIGN ENVIRONMENT
Table of Contents This section helps you customize your Synplicity environment for designing an ORCA FPGA. Cover Page Environment Variables
ORCA Make sure you have installed the latest version of ispLEVER with ORCA devices Web Site installed and that the FOUNDRY environment variable is set. The FOUNDRY variable points to the ispFPGA (PC) or ispfpga (UNIX) directory. ORCA FAQs The variable should be set as follows:
Tech $ setenv FOUNDRY
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GO TO ¾ ORCA/SYNPLIFY LIBRARY FILES
Table of Contents The following libraries are provided for the ORCA 2A FPGAs. These files are available in your synplcty/lib/lucent directory. Cover Page orca.vhd This VHDL file defines the ORCA components. In order to be able to directly instantiate ORCA library primitives in your VHDL design files, you will need to add the ORCA Web Site following statements in your VHDL design to access these components:
ORCA library orca; FAQs use orca.orcacomp.all;
Tech Support orca.v This Verilog® file defines the ORCA components for use with Verilog designs. Include this file at the top of the source file list when you want to directly instantiate Index ORCA library primitives in your verilog source.
If you have version 7.3 or later of Synplify with ORCA Series 3 and Series 4 support, the library files have been renamed as below:
orca2.vhd The VHDL library file for ORCA 2 components. For Synplify version 7.3 and later, if targeting the ORCA 2 architecture, add the following:
library orca2; use orca2.orcacomp.all;
orca3.vhd The VHDL library file for ORCA Series 3 components. For Synplify version 7.3 and later, if targeting the Series 3 architecture, add the following:
library orca3; use orca3.orcacomp.all;
orca4.vhd The VHDL library file for ORCA Series 4 components. For Synplify version 7.3 and later, if targeting the Series 4 architecture, add the following:
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GO TO ¾ library orca4; use orca4.orcacomp.all; Table of Contents
Cover The Verilog library files are now named orca2.v, orca3.v, and orca4.v for the respective Page architectures. Please contact Synplicity support in case of discrepancies.
For updated library files for Verilog and VHDL in the ispLEVER environment, you can ORCA Web Site retrieve the files in the userware directory after ispLEVER installation. Refer to the complete paths below for PC and UNIX.
ORCA Verilog header files: FAQs $FOUNDRY\userware\NT\4E_VERILOG_HEADERS\orca4_synplify.v Tech $FOUNDRY/userware/unix/4E_Verilog_Headers/orca4_synplify.v Support VHDL header files (also in same path): Index $FOUNDRY\userware\NT\4E_VERILOG_HEADERS\orca4_synplify.vhd $FOUNDRY/userware/unix/4E_Verilog_Headers/orca4_synplify.vhd
Note
There are many HDL source files available in the userware directory to ensure the successful instantiation of ORCA library elements in all architectures.
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GO TO ¾ DESIGN FLOW
Table of Contents This section describes the interface between Synplicity’s Synplify and ORCA. The interface allows you to:
Cover Page • Synthesize an ORCA design using Synplify.You can use the integrated version of Synplify in ispLEVER’s Project Navigator. Use the Tools > Synplify Synthesis command to open the program. ORCA Web Site • In Project Navigator, set up an ORCA FPGA project and import your source file. • In Project Navigator, run your ORCA project’s imported source file through the Place ORCA & Route Design process in the Process window. Right click on the process and click FAQs Start. • In Project Navigator, run the Generate Bitstream process in the Process window. Tech Support Right click on the process and click Start.
Index Note
You can also run the design flow from the command line.
The design flow for generating logic designs with Synplicity’s Synplify and ORCA is shown in Figure 1 on page 6.
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GO TO ¾ Figure 1. Synplicity Interface Design Flow
Table of Contents CREATE HDL Module/IP DESIGN .edn FILE Cover Manager Page
ORCA SYNPLIFY ispLEVER Web Site ENVIRONMEN ADD DESIGN ORCA MAP DESIGN FILES INTO DESIGN FLOW (map) SYNPLIFY ORCA FAQs MAP TRACE SET TARGET REPORT ORCA ARCH. Tech (trce) Support
Index PLACE & SET DEVICE ROUTE TRACE OPTIONS & REPORT ESTABLISH (par) AREA/TIMING TRADEOFF PLACE & Netlist Writer ROUTE TRACE (ngd2vhd/ REPORT COMPILE ngd2ver) (trce) DESIGN
WRITE WRITE Write VHDL, GENERATE VHDL/Verilog EDIF Verilog SDF BITSTREAM NETLIST NETLIST Netlists (bitgen)
Frontend Backend Simulation using NeoPriM Simulation using Verilog/VHDL VITAL/ Verilog/VHDL ORCA Simulator Verilog Simulator Device
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GO TO ¾ Series 4 Synthesis Flow
Table of This section contains any information that is necessary for performing design synthesis Contents using VHDL and Verilog HDL for Series 4 designs.
Cover Series 4 library elements, for example, Block RAMs (BR512X18), Programmable PLLs Page (PPLL), and LVDS buffers, should be fully supported by most synthesis vendors; however, there is some user intervention required for instantiation and assigning any properties to these elements.For updated library files for Verilog , retrieve the ORCA Web Site orca4_synplify.v or orca4_synplify.vhd from the $FOUNDRY/userware/nt | sol/ 4E_VERILOG_HEADERS directory.
ORCA FAQs Actions necessary to ensure proper instantiation and for assigning properties for Series 4 elements are described in the following subsections.
Tech Support Using VHDL Through Synthesis If some Series 4 elements are not yet supported by Synplicity, VHDL designs may require Index these elements to be defined as black boxes or macros during synthesis. Please check with your vendor for details on ORCA Series 4 support.
For example, a PPLL library element using Synplify for synthesis would be instantiated as:
library synplify;
use synplify.attributes.all; entity top is port (clk, rst, en, data: in bit; q: out bit); end top;
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GO TO ¾ architecture structural of top is Table of -- In this example, PPLL is a user-defined macro Contents -- that you want to directly instantiate in your -- design as a black box. Cover Page architecture structural of top is -- In this example, PPLL is a user-defined macro ORCA -- that you want to directly instantiate in your Web Site -- design as a black box.
ORCA component PPLL FAQs PORT
Tech CLKIN : IN STD_LOGIC; Support FB : IN STD_LOGIC; MCLK : OUT STD_LOGIC; Index NCLK : OUT STD_LOGIC; LOCK : OUT STD_LOGIC; INTFB : OUT STD_LOGIC ); end component; attribute syn_black_box of PPLL: component is true;
To enter attributes for Series 4 elements using VHDL, the syntax structures are the same for most synthesis vendors. Examples of assigning attributes for Synplicity is provided below.
VHDL syntax for use with Synplicity:
attribute initval: string;
attribute initval of mem_0_0_15 : label is “0x00000000000000000000000000000000”;
Using Verilog Through Synthesis When you instantiate Series 4 elements in Verilog HDL, synthesis tools may issue warning or error messages. To avoid this, we have provided Verilog header files, which contain port definitions for all Series 4 elements. These files are provided for all the synthesis tools and for Synplicity Synplify is located in the file path as:
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GO TO ¾ $FOUNDRY/userware/pc | unix/4E_Verilog_Headers/orca4_synplify.v
Table of where $FOUNDRY is the directory path where your ispfpga folder is stored. Contents Depending on what tool is being used, you should add proper header file along with other Cover Verilog files to the project. Page To enter attributes for Series 4 elements using Verilog, the syntax varies depending upon ORCA which one of the three major synthesis vendors (i.e., Synopsys™, Exemplar™, or Web Site Synplicity) is then used to synthesize the design. Examples of assigning properties for the various synthesis vendors are provided below. ORCA FAQs Verilog syntax for use with Synplicity:
Tech /* synthesis INITVAL=”0x00000000000000000000000000000000” */; (in each instance) Support
Index
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GO TO ¾ DESIGN ENTRY
Table of Contents The following steps outline how to synthesize designs for ORCA with Synplicity design tools and ORCA: Cover Page 1. Create a design in Verilog HDL or in VHDL. The designs may be technology- independent or contain ORCA-specific functions; however, they cannot contain instances of functions from other technology libraries. See the Synplify online help ORCA Web Site system for a list of names and characters that should not be used for components, nets, or sites (instances).
ORCA 2. Use ispLEVER’s Module/IP Manager to create a SCUBA® (Synthesis Compiler for FAQs User programmaBle Arrays) module, which is a parameterized module generator optimized for ORCA FPGAs. The output from Module/IP Manager can be in EDIF, Tech VHDL, or Verilog. Since the modules generated are optimized for the ORCA Support architecture, they provide speed and area benefits over synthesis. The output from Module/IP Manager (VHDL or Verilog only) can be directly read into Synplify or can Index be integrated with the user design as a sub-module. For a complete description of Module/IP Manager, refer to the Module/IP Manager online help system in ispLEVER.
Note
You can run SCUBA from the command line; however, we recommend using the Module/IP Manager as options can contain lengthy arguments for more complex modules.
3. (Optional) Verify that the design description is correct by simulating the HDL description.
4. Create Project: ADD the design files to create a project for the design. If the design contains ORCA specific cells, do the following to access these cells:
a. For Verilog designs, include the file orca.v at the top of the source file list so that it gets compiled first.
b. For VHDL designs, add the following lines at the top of your design files: library orca; use orca.orcacomp.all;
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GO TO ¾ 3. Change/Specify Result file. This is the name of the EDIF file which will be generated after synthesis. Table of Contents 4. Set Target Architecture: to, for example, ORCA 3C/3T/3L as desired.
Cover 5. Set Device Options: This lets you select the ORCA part desired and set the following Page options. • Fanout Limit: Default fanout value is 100. Large fanouts can cause large delays ORCA Web Site and routability problems. During technology mapping, the Synplify ORCA mapper tries to keep the fanout under the fanout limit. Synplify uses the fanout limit as a guideline, and not as a hard limit. Synplify first reduces fanout by ORCA replicating the driver of the high fanout net and splitting the net into segments. If FAQs replication is not possible, then Synplify buffers the signals. Buffering is expensive both in terms of intrinsic delay and consumption of resources, and is Tech therefore not used until a slightly higher fanout limit than specified. Support • Force GSR Usage: Synplify will create a GSR block to access the GSR resource for ORCA if it is appropriate for the design. By default, if there is a single reset Index used in the design, then Synplify will connect that reset signal to a GSR instance. It will do this even if some flip-flops have no reset at all. Usually, flip-flops without set or reset may be safely initialized because the reset is only used when the device is turned on. If this is not the case, then you will need to turn off the Force GSR Usage option. When Synplify sees this option turned off, Synplify requires that all flip-flops have resets and that the resets are all the same, before it uses GSR. • Disable I/O Insertion is used for creating multiple EDIF files for your project or if you do not want any I/Os inserted automatically. Note that I/Os have to be inserted at the top level design for ORCA.
6. RUN Synplify to synthesize the design to meet a desired area target and/or desired timing constraints. RUN Synplify in the default configuration with no timing constraints (Frequency = 0 MHz) in order to get the smallest possible area for the synthesized design.
7. If you need a smaller result, use HDL Analyst to generate the RTL view, browse the schematic to view the hardware generated by the tool. If you do not see what you expected, edit your source code, re-synthesize, and view again in HDL Analyst. Continue this process till you get the expected smallest design.
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GO TO ¾ 8. If the design has state machines, you may get smaller results if you turn on the Symbolic FSM Compiler option and then synthesize your design. When this is turned Table of on, Synplify automatically finds and extracts state machines. The Symbolic FSM Contents Compiler re-encodes the extracted state machines into a one-hot form regardless of their original encoding. Future releases of the tool will provide the user an override Cover option so that the designer can choose the encoding style. Page 9. To get a faster result, you can specify timing constraints in a Constraint File (.sdc). ORCA The constraint files are added to the Project source files list. If the design has multiple Web Site clocks, override the default clock frequency with the DEFINE CLOCK timing constraint. If you know the delays outside your chip for inputs and outputs, set them ORCA with the define_input_delay and define_output_delay timing constraints. FAQs 10. Rerun Synplify and check the Synplify Log file to see how close you are to your Tech target frequency. If you are within 5-10 percent of your desired goal, the design can Support be taken through map, place and route. If not, rerun the design with additional constraints and/or code changes until you achieve the desired results. Index 11. Complete one iteration of the ORCA design flow in Project Navigator (Map Design, Map TRACE Report, Place & Route, and Place & Route TRACE Report) or from the command line. The final TRACE run will give you the delays through your critical paths. If you still do not meet your timing goals, you can resynthesize your design through Synplify with code changes or add or subtract route delay differences using the -route option to the Synplify define_input_delay, define_output_delay, define_reg_input_delay, and define_reg_output_delay timing constraints in the Synplify constraint file. When you rerun Synplify, the tool will add (or subtract) these route delays to its estimates during timing analysis.
12. To have Synplify restructure your design to speed up paths, add the -improve option to the timing constrains. Refer to the Synplify documentation for more information on timing constrains, syntax, and their use in Synplify.
13. Decreasing the fanout limit can also sometimes result in a faster design.
14. Other Synplify Timing Attributes can be used to synthesize to a faster design. Refer to the next section and Synplify Docs for more details.
15. Other ways of improving timing for ORCA designs are by using DIN, DOUT, properties wherever appropriate.
16. Synplify will write out an EDIF netlist into a file name specified as the Result file.
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GO TO ¾ 17. Synplify can also write out VHDL (.vhm file) and Verilog (.vm file) netlists after synthesis for simulation purposes. In order to use this feature, click on the Impl Table of Options (Implementation Options) button on the left side of the interface and select Contents the Implementation Results tab to enable Write Mapped VHDL Netlist and/or Write Mapped Verilog Netlist. To functionally verify the design, you can simulate Cover these netlists using a standard VHDL or Verilog simulator. Refer to the section Page Simulation of Netlists Generated by Synplify for more details.
ORCA Web Site
ORCA FAQs
Tech Support
Index
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GO TO ¾ SETTING TIMING CONSTRAINTS
Table of Contents Synplify supports attributes for specifying external and internal timing constraints to speed up paths through designs. Synplify automatically generates default constraints, and Cover you may not be required to specify any timing constraints. It is recommended that you try Page a complete run through an ORCA design flow, that is, Map Design, Map TRACE Report, Place & Route Design, Place & Route TRACE Report processes in Project Navigator or equivalent command line options), before applying any timing constraints in Synplify. ORCA Web Site When to Set Timing Constraints ORCA FAQs 1. After running the Place & Route Design process in Project Navigator or par from the command line, some nets were discovered to have a larger than normal, or larger than Tech acceptable delay. Support 2. The design has a late arriving strobe that must have priority (arrive faster) over other Index inputs which you know will be stable earlier.
3. The design has inputs or register outputs that are known to be stable early or for multiple cycles.
Synplify Timing Attributes
syn_speedup: Speeds up or slows down all paths through this object
syn_inspeedup: Speeds up or slows down paths coming to this object
syn_outspeedup: Speeds up or slows down paths leaving this object
Synplify timing attributes accept integers as values. Positive integer values emphasize paths for timing optimization, in order to reduce delay. Negative integer values de- emphasize paths as less important for a timing optimization. A value of ’10’ corresponds roughly to a LUT. Synplify timing attributes can be places on input ports, output ports, and registers.
Timing constraints can be placed on the top level module, which becomes a default for all pins. This is very useful when the paths of interest are register-to-register paths. The following example de-emphasizes all paths from and to the I/Os.
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GO TO ¾ Verilog:
Table of module top (out, a, b, clk) /* synthesis syn_speedup=-10 */; Contents ..... Cover endmodule Page
ORCA VHDL: Web Site architecture behavior of top is ORCA attribute syn_speedup : integer; FAQs attribute syn_speedup of all : architecture is -10;
Tech begin Support ...... end; Index
Refer to information on setting timing constraints section for Verilog and VHDL designs in the Synplify online help system.
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GO TO ¾ Synplify Timing Report
Table of Synplify generates a Resource Usage Report, a Timing Report, and a Net Buffering Contents Report for ORCA designs.
Cover The Resource Usage Report lists the number of each type of cell used, including the Page number of look-up tables and registers.
ORCA The Net Buffering Report lists each near that had its source replicated, and the number of Web Site segments created for the net. The summary reports the number of registers and look-up tables added by replication. ORCA FAQs Synplify Timing Reports show all instances and connections in the design that are near the critical path. Near means within one "level" of the most critical path. The reported Tech instances are sorted by the arrival time at their pins, with the path ends at the top of the Support report and the path beginnings are the bottom. Each connection is listed with the delay to the connection and the length of the longest path passing through the connection.
Index Typically, path ends will be inputs to flip-flops or primary output cells. Path beginnings will be flip-flop outputs and primary input cells. You can trace paths through the report by matching net names on connections.
Synplify’s Timing Reports are an estimate. The actual timing of the design depends heavily on placement and routing, the device, and speed grade.
In order to get a better estimate of the delays, run the Map TRACE Report process in Project Navigator (trce) on the mapped design to get an estimate of the logic delays. After this step, then go through one iteration of Place & Route Design process (par) and the Place & Route TRACE Report process (trce) to obtain an estimate of the routing delays and the critical paths in the design. The final frequency of the design depends on a number of factors: the number of logic levels in the design, the number of connections and number of nets in the design, the packing factor (also number of inputs to a PFU), utilization of tristate buffers, number of I/Os (and number of tristatable I/Os and the number of controls), the device size, and speed grade.
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GO TO ¾ I/O BUFFER INSERTION
Table of Contents You must insert I/O buffers to implement an ORCA FPGA design. If your design has multiple EDIF files, insert I/O buffers only at the top-level. There are two ways to insert I/ Cover O buffers in your HDL code: Page • Inserted by default during synthesis through Synplify, or
ORCA • I/O Macrocell Instantiation (disable I/O insertion under Set Device Options in the Web Site Synplify window)
ORCA I/O Macrocell Instantiation FAQs Table 1 lists the ORCA I/O buffers that may be instantiated in your Verilog HDL or Tech VHDL source. Support Table 1. ORCA 2A, Series 3 Input/Output Buffers Index I/O Macrocell Name Inputs Outputs I/Oputs Special Functions Input Buffers – CMOS Levels IBM I O IBMS I O Delay IBMPD I O Pull-Down IBMPDS I O Pull-Down, Delay IBMPU I O Pull-Up IBMPUS I O Pull-Up, Delay Input Buffers – TTL Levels IBT I O IBTS I O Delay IBTPD I O Pull-Down IBTPDS I O Pull-Down, Delay IBTPU I O Pull-Up IBTPUS I O Pull-Up, Delay Output Buffers – 12mA Sink, 6mA Source OB12 I O OB12F I O Fast OBZ12 I,T O Tristate OBZ12F I,T O Tristate, Fast OBZ12PU I,T O Tristate, Pull-Up
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GO TO ¾ Table 1. ORCA 2A, Series 3 Input/Output Buffers OBZ12FPU I,T O Tristate, Pull-Up, Fast Table of Contents OBZ12PD I,T O Tristate, Pull-Down OBZ12FPD I,T O Tristate, Pull-Down, Fast Cover Output Buffers – 6mA Sink, 3mA Source Page OB6 I O OBZ6 I O Tristate ORCA OBZ6PU I O Tristate, Pull-Up Web Site OBZ6PD I O Tristate, Pull-Down Bidirectional Buffers – CMOS Levels, 12mA Sink, 6mA Source ORCA BMZ12 I,T O B Tristate FAQs BMZ12F I,T O B Tristate, Fast BMZ12PU I,T O B Tristate, Pull-Up Tech BMZ12FPU I,T O B Tristate, Fast, Pull-Up Support BMZ12PD I,T O B Tristate, Pull-Down BMZ12FPD I,T O B Tristate, Fast, Pull-Down Index Bidirectional Buffers – CMOS Levels, 12mA Sink, 6mA Source, Delayed Inputs BMS12 I,T O B Tristate BMS12F I,T O B Tristate, Fast BMS12PU I,T O B Tristate, Pull-Up BMS12FPU I,T O B Tristate, Fast, Pull-Up BMS12PD I,T O B Tristate, Pull-Down BMS12FPD I,T O B Tristate, Fast, Pull-Down Bidirectional Buffers – CMOS Levels, 6mA Sink, 3mA Source BMZ6 I,T O B Tristate BMZ6PU I,T O B Tristate, Pull-Up BMZ6PD I,T O B Tristate, Pull-Down Bidirectional Buffers – CMOS Levels, 6mA Sink, 3mA Source, Delayed Inputs BMS6 I,T O B Tristate BMS6PU I,T O B Tristate, Pull-Up BMS6PD I,T O B Tristate, Pull-Down Bidirectional Buffers – TTL Levels, 12mA Sink, 6mA Source BTZ12 I,T O B Tristate BTZ12F I,T O B Tristate, Fast BTZ12PU I,T O B Tristate, Pull-Up BTZ12FPU I,T O B Tristate, Fast, Pull-Up BTZ12PD I,T O B Tristate, Pull-Down
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GO TO ¾ Table 1. ORCA 2A, Series 3 Input/Output Buffers BTZ12FPD I,T O B Tristate, Fast, Pull-Down Table of Contents Bidirectional Buffers – TTL Levels, 12mA Sink, 6mA Source, Delayed Inputs BTS12 I,T O B Tristate Cover BTS12F I,T O B Tristate, Fast Page BTS12PU I,T O B Tristate, Pull-Up BTS12FPU I,T O B Tristate, Fast, Pull-Up ORCA BTS12PD I,T O B Tristate, Pull-Down Web Site BTS12FPD I,T O B Tristate, Fast, Pull-Down Bidirectional Buffers – TTL Levels, 6mA Sink, 3mA Source ORCA BTZ6 I,T O B Tristate FAQs BTZ6PU I,T O B Tristate, Pull-Up BTZ6PD I,T O B Tristate, Pull-Down Tech Bidirectional Buffers – TTL Levels, 6mA Sink, 3mA Source, Delayed Inputs Support BTS6 I,T O B Tristate BTS6PU I,T O B Tristate, Pull-Up Index BTS6PD I,T O B Tristate, Pull-Down
Figure 2a illustrates I/O buffer instantiation in Verilog HDL and Figure 2b illustrates I/O buffer instantiation in VHDL. Refer to the section titled MACROCELL INSTANTIATION in this document for information on instantiation.
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GO TO ¾ Figure 2a. Instantiating I/O Buffers in Verilog HDL
Table of Contents module example(data, clock, out_put); Cover input [1:0] data; Page input clock; output [1:0] out_put; ORCA wire [1:0] data_in, data_out; Web Site wire clk;
ORCA IBM u0(.I(data[1]),.O(data_in[1])); FAQs IBM u1(.I(data[0]),.O(data_in[0])); IBM u2(.I(clock),.O(clk)); Tech OB6 u3(.I(data_out[1]),.O(out_put[1])); Support OB6 u4(.I(data_out[0]),.0(out_put[0]));
// logical description goes here... Index endmodule
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GO TO ¾ Figure 2b. Instantiating I/O Buffers in VHDL
Table of Contents library IEEE, orca; Cover use orca.orcacomp.all; Page use IEEE.std_logic_1164.all;
entity example is ORCA Web Site port( data : in std_logic_vector(1 DOWNTO 0); clock : in std_logic; ORCA FAQs out_put : out std_logic_vector(1 DOWNTO 0) );
end example; Tech Support architecture io_buf of example is
Index component IBM port( I : in std_logic; O : out std_logic ); end component;
component OB6 port( I : in std_logic; O : out std_logic ); end component;
signal data_in,data_out :std_logic_vector(1 DOWNTO 0); signal clk : std_logic;
begin
u3 : OB6 port map( I => data_out(1), O => out_put(1)); u4 : OB6 port map( I => data_out(0), O => out_put(0)); u0 : IBM port map( I => data(1), O => data_in(1)); u1 : IBM port map( I => data(0), O => data_in(0)); u2 : IBM port map( I => clock, O => clk);
end io_buf;
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GO TO ¾ Overriding the Default Padtype for Automatic I/O Insertion
Table of Synplify automatically inserts input/output (I/O) pads into the synthesized design. The Contents default input pad is "IBM", which is a CMOS padtype. The default output pad is "OB6". The padtype can be changed for a particular Cover I/O by using the Synplify "orca_padtype" attribute. Page The "orca_padtype" attribute is a string attribute which has to be attached to a top level ORCA port to override the I/O cell used by Synplify when synthesizing the I/O cell. Web Site Figure 3a. Overriding Default Padtype in VHDL ORCA FAQs entity example is port (data: in std_logic; Tech Support clock : in std_logic; out_put : out std_logic_vector(1 DOWNTO 0) ); Index -- declare the orca_padtype attribute attribute orca_padtype: string; -- Choose padtype OB12 for output "out_put" attribute orca_padtype of out_put: signal is "OB12" end example;
Figure 3b. Overriding Default Padtype in Verilog HDL
module example(data, clock, out_put); // Choose padtype IBT to select a TTL input for // data input data /*synthesis orca_padtype="IBT" */;
// logical description goes here... endmodule
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GO TO ¾ Locking I/O Pins
Table of Contents There are two methods for locking I/O pins using the ORCA/Synplify design flow:
Cover Locking I/O in the HDL File Page The following steps outline how to lock I/O in an ORCA design using the ORCA/Synplify ORCA design flow: Web Site 1. The ORCA LOC property is used to specify and lock the PIC/IOB site in the FPGA. ORCA The property is assigned to a PAD. In order to specify it in the Synplify flow, the FAQs instance name of the buffer must be known. The best way to do this is to instantiate the buffer in the HDL design and specify the LOC property on the instance using the Tech attribute construct in VHDL or the Synplify synthesis directive in Verilog. Please Support refer to the Synplify Online Help for more information on Synthesis Directives and Attributes for designing using Synplify. Index
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GO TO ¾ Figure 4a. Locking pins in a VHDL Design
Table of Contents library ieee; use ieee.std_logic_1164.all; library orca; Cover Page use orca.orcacomp.all;
entity dff1 is ORCA Web Site port (data, clk, reset : in std_logic; qr : out std_logic); end dff1; ORCA FAQs architecture async_reset of dff1 is attribute loc: string; Tech attribute loc of U1: label is "A21"; Support attribute loc of U2: label is "B21"; signal data_tmp, qr_tmp : std_logic; Index begin U1: IBM port map (data, data_tmp); reset: process (clk, reset) begin if reset = '1' then qr_tmp <= '0'; elsif rising_edge(clk) then qr_tmp <= data_tmp; end if; end process reset; U2: OB6 port map (qr_tmp, qr);
end async_reset;
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GO TO ¾ Figure 4b. Locking Pins in a Verilog Design
Table of Contents // Simple flip-flop example without set or reset `include "/home/fpgacae/synplcty/lib//orca.v"
Cover Page module dff(q, d, clk); output q ; input d ; ORCA Web Site input clk; reg q_tmp; wire d_tmp; ORCA IBM u1 (d,d_tmp) /* synthesis LOC="A21" */; FAQs always @(posedge clk) begin Tech q_tmp = data_tmp; Support end
Index OB6 u2 (q_tmp, q) /* synthesis LOC="B21" */;
endmodule
Locking I/O in the ORCA Preference File
The second method is to lock I/O using the preference file in ORCA. The syntax for the preference is: LOCATE COMP "I1" SITE "A7"; The problem with this method is that unless I1 is an instantiated buffer, the instance name changes during each run of synthesis. As a result, the designer would have to check the EDIF file or the mapped NCD file (.ncd) for the correct name. To check the NCD file, the file has to be converted to text using the ncdread command: ncdread mapped.ncd > mapped.txt where mapped.ncd is the NCD file to convert and mapped.txt is the text file. The ncdread program utility is located in the $FOUNDRY/bin/nt | sol path.
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GO TO ¾ Placing Registers Near I/Os
Table of To improve the performance of an ORCA design, you can pass the Direct In (DIN) and Contents Direct Out (DOUT) attributes to ORCA to specify that a register driving or being driven by an I/O be placed next to that I/O during place and route. Cover Page DIN and DOUT can be placed on top level ports or on instantiated I/O cells. DIN and DOUT are string attributes that take no arguments. In the Synplify flow, use the attribute construct in VHDL or the Synplify synthesis directive in Verilog to specify the DIN/ ORCA DOUT attributes on the top level ports. Web Site The second way of specifying the DIN/DOUT property in the Synplify flow is to ORCA instantiate the buffer in the HDL design and specify the DIN/DOUT property on the FAQs instance using the attribute construct in VHDL or the Synplify synthesis directive in Verilog. Please refer to the Synplify On-line Help for more information on Synthesis Tech Directives and Attributes for designing using Synplify. Support Please refer to the earlier section on Locking I/O Pins for HDL design examples with the DIN/DOUT properties for use with the ORCA/Synplify flow. Index Note
For DIN/DOUT to work, a LOC property must be attached to the pad. If the property is attached to a component that does not feed a register (or is not a register output), an error is generated. An error also is generated if the property is attached to a multi-fanout(fanin) component. Please refer to the online help system on ORCA attributes and error conditions.
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GO TO ¾ Bidirectional Buffer Insertion
Table of Bidirectional buffers can either be instantiated in the same manner as regular I/O Buffers Contents as defined earlier, or inferred in the HDL as shown in the examples below.
Cover Page Figure 5a. Inferring Bi-Directional Buffers in Verilog
ORCA module bireg (din, clk, en_o, G, Qo1, Qio); Web Site input din, clk, en_o, G; output Qo1; ORCA inout Qio; FAQs reg Qo1; reg Q_reg; reg Qio_reg; Tech Support wire Qio = Qio_reg;
always @(posedge clk) Index begin Q_reg = din; end
always @(en_o or din or G or Qio or Q_reg) begin if (en_o) Qio_reg = Q_reg; else Qio_reg = 1'hz; if (G) Qo1 = Qio; end endmodule
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GO TO ¾ Figure 5b. Inferring Bi-Directional Buffers in VHDL
Table of Contents library ieee; use ieee.std_logic_1164.all; Cover Page entity bireg is
ORCA port ( din,clk,en_o,G : in std_logic; Web Site Qo1 : in std_logic; Qio : inout std_logic); ORCA end bireg; FAQs
Tech architecture beh of bireg is Support signal iosig : std_logic; begin Index process(clk,iosig,Qio,en_o,G) begin if clk'event and clk = '1' then iosig <= din; end if; if en_o = '1' then Qio <= iosig ; else Qio <= 'Z'; end if; if (G = ’1’) then Qo1 <= Qio; end if; end process; end beh;
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GO TO ¾ DESIGN EXAMPLES
Table of Contents This section explains how to create and process various HDL (Verilog and VHDL) based designs, target them to the appropriate ORCA device, and compile them using the Cover Synplicity tool. The section also touches upon mapping, placement, routing, and Page performing timing analysis using the ORCA tools.
ORCA Designing with ORCA Web Site The ORCA Cell Library contains most of the elements described in the ORCA Macro ORCA Library section of the ORCA Libraries Manual. Not all the cells are used automatically FAQs during synthesis, but all the cells can be instantiated in the behavioral code. The example in this section explains how to create and process an adder/subtracter circuit, called Tech addsub, in Verilog HDL. Figure 6a shows the addsub circuit described in Verilog HDL Support and Figure 6b describes the design in VHDL.
Index Figure 6a. Sample Verilog Adder/Subtracter addsub.v
module addsub (a, b, c, clk, z); input [7:0] a; input [7:0] b; input c; input clk; output [7:0] z; reg [7:0] z; always @ (posedge clk) begin if (c == 1’b1) z = a + b; else z = a - b; end endmodule
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GO TO ¾ Figure 6b. Sample VHDL Adder/Subtracter addsub.vhd
Table of library IEEE; Contents use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; Cover Page entity addsub is
ORCA port( a : in signed(7 DOWNTO 0); Web Site b : in signed(7 DOWNTO 0); c, clk : in std_logic; ORCA z : out signed(7 DOWNTO 0) ); FAQs end addsub; Tech Support architecture addsub of addsub is
Index begin
add_sub : process begin wait until CLK'event and CLK = '1'; if (c = '1') then z <= a + b; else z <= a - b; end if; end process; end addsub;
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GO TO ¾ MACROCELL INSTANTIATION
Table of Contents ORCA 2CA/2TA/2TB Macro Library Elements
Cover The ORCA Macro Library contains some specialized cells which are used to perform Page some complex operations in the ORCA architecture. These cells may be used only through instantiation. ORCA Web Site Arithmetic: ADD, ADSU, FADD4O, FADSU4O, FSUB4O, SUB
ORCA Counters: CB4P3BX, CB4P3DX, CB4P3IX, CB4P3JX, CD4P3BX, FAQs CD4P3DX, CD4P3IX, CD4P3JX, CU4P3BX, CU4P3DX, CU4P3IX, CU4P3JX, LB4P3AX, LB4P3AY, LD4P3AX, Tech LD4P3AY, LU4P3AX, LU4P3AY Support Specialized Logic: COMP, COMP4, FAC4P3D, FMULT4, LTGT, PFUND, PFUND0, PFUXR, PFUXR0, PFUMX Index Registers: RD4S3A, RD4S3B, RD4S3D, RD4S3I, RD4S3J, RLS4P3A, RS4P3A, RS4P3B, RS4P3D, RS4P3I, RS4P3J, RS4S3A, RS4S3B, RS4S3D, RS4S3I, RS4S3J
Memory: RPP16X2, RPP16X2Z, RPP16X4, RPP16X4Z.
Figures 7a and 7b illustrate a method to instantiate a 4-bit loadable up-counter (cell LU4P3AY) in Verilog HDL and VHDL.
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GO TO ¾ ORCA Series 3 Macro Library Elements
Table of A number of cells listed above in the 2CA/2TA/2TB section are no longer available in the Contents Series 3 architecture. For a complete list of library elements in the Series 3 architecture, please refer to the ORCA Libraries Manual. The Series 3 architecture also contains some Cover specialized cells which are used to perform some complex operations in the ORCA Page architecture. New additions to the architecture include 8-bit arithmetic elements. These cells may be used only through instantiation. ORCA Web Site Arithmetic: FADD4O, FADD8, FADD8O, FADSU4O, FADSU8, FADSU8O, FSUB4O, FSUB8, FSUB8O, FMULT8, ORCA INC4, INC8, DEC4, DEC8, INCDEC4, INCDEC81 FAQs Comparators: AGEB8, ANEB8, ALEB4, ALEB8 Tech Support Counters: CB4P3BX, CB4P3DX, CB4P3IX, CB4P3JX, CB8P3BX, CB8P3DX, CB8P3IX, CB8P3JX, CD4P3BX, CD4P3DX, CD4P3IX, CD4P3JX, CD8P3BX, CD8P3DX, CD8P3IX, Index CD8P3JX CU4P3BX, CU4P3DX, CU4P3IX, CU4P3JX, CU8P3BX, CU8P3DX, CU8P3IX, CU8P3JX, LB4P3AX, LB4P3AY, LB8P3BX, LB8P3DX, LB8P3IX, LB8P3JX, LD4P3AX, LD4P3AY, LD8P3BX, LD8P3DX, LD8P3IX, LD8P3JX, LU4P3AX, LU4P3AY, LU8P3BX, LU8P3DX LU8P3IX, LU8P3JX
Specialized Logic: PFUMX, PUR, CFD1P3BX, CFD1P3DX, CFD1P3IZ, CFD1P3JZ, CFD1P3IX, CFD1P3JX
SLIC Cells: SAOI442, SAOI44, SAOI42, SAND2, SAND4, SAND6, SAND8, SAND10, SOR2, SOR4, SOR6, SOR8, SOR10
PIC Registers: IFD1P3BX, IFD1P3DX, IFD1P3IZ, IFD1P3JZ, IFD1S1B, IFD1S1D, IFD1S1I, IFD1S1J, OFE1P3BX, OFE1P3DX, OFE1P3IZ, OFE1P3JZ, OFS1P3BX, OFS1P3DX, OFS1P3IZ, OFS1P3JZ, IFD1P3IX, IFD1P3JX, OFE1P3IX, OFE1P3JX, OFS1P3IX, OFS1P3JX, ILF2P3BX, ILF2P3DX, ILF2P3JX, ILF2P3IX, ILF2P3IZ, ILF2P3JZ
2-I/P Func. Generators: OEAND2, OEOR2, OEND2, OEXOR2, OEXNOR2, OSAND2, OSOR2, OSND2, OSNR2, OSXOR2, OSXNOR2
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GO TO ¾ Clock Controls: CLKCNTLB, CLKCNTLT, CLKCNTLL, CLKCNTLR, CLKCNTHB, CLKCNTHT, CLKCNTHL, CLKCNTHR Table of Contents PCM: DLL1XB, DLL1XT, DLL2XB, DLL2XT, DLLPDB, DLLPDT, PLLB, PLLT, PCMBUFB, PCMBUFT Cover Page Memory: DCE32X4, RCE32X4, ROM32X4, ROM16X1, ROM32X1 ORCA Web Site
ORCA Note FAQs Use port references for net connections when instantiating ORCA Tech library cells. Refer to the ORCA Macro Library for cell port names. Support
Index
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GO TO ¾ ORCA Series 4 Macro Library Elements
Table of A number of cells listed in the Series 3 section are no longer available in the Series 4 Contents architecture. For a complete list of library elements in the Series 4 architecture, please refer to the ORCA Libraries Manual. The Series 4 architecture also contains some Cover specialized cells which are used to perform some complex operations in the ORCA Page architecture.
Tech Comparators: AGEB4, AGEB8, ALEB4, ALEB8, ANEB4, ANEB8 Support Counters: CU4, CU4P3BX, CU4P3DX, CU4P3IX, CU4P3JX, CU8P3BX, CU8P3DX, CU8P3IX, CU8P3JX, CD4, Index CD4P3BX, CD4P3DX, CD4P3IX, CD4P3JX, CD8P3BX, CD8P3DX, CD8P3IX, CD8P3JX, CB4, CB4P3BX, CB4P3DX, CB4P3IX, CB4P3JX, CB8P3BX, CB8P3DX, CB8P3IX, CB8P3JX, LU4P3AX, LU4P3AY, LU4P3BX, LU4P3DX, LU4P3IX, LU4P3JX, LU8P3BX, LU8P3DX, LU8P3IX, LU8P3JX, LD4P3AX, LD4P3AY, LD4P3BX, LD4P3DX, LD4P3IX, LD4P3JX, LD8P3BX, LD8P3DX, LD8P3IX, LD8P3JX, LB4P3AX, LB4P3AY, LB4P3BX, LB4P3DX, LB4P3IX, LB4P3JX, LB8P3BX, LB8P3DX, LB8P3IX, LB8P3JX
Specialized Logic: BNDSCAN, OSCIL, READBK, STRTUP, GSR, TSALL, PUR, MUX21, MUX21E, MUX41, MUX41E, MUX81 , PFUMX41
SLIC Cells: SAND2, SAND4, SAND6, SAND8, SAND10, SOR2, SOR4, SOR6, SOR8, SOR10, SAOI42, SAOI44, SAOI442
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GO TO ¾ PIC Flip-Flops/Latches: IFS1P3BX, IFS1P3DX, IFS1P3IX, IFS1P3IZ, IFS1P3JX, IFS1P3JZ, OFE1P3BX, OFE1P3DX, OFE1P3IX, Table of OFE1P3IZ, OFE1P3JX, OFE1P3JZ, OFS1P3BX, Contents OFS1P3DX, OFS1P3IX, OFS1P3IZ, OFS1P3JX, OFS1P3JZ, ILF2P3BX, ILF2P3DX, ILF2P3IX, Cover ILF2P3IZ, ILF2P3JX, ILF2P3JZ, IFS1S1B, IFS1S1D, Page IFS1S1I, IFS1S1J, OFE1S1B, OFE1S1D, OFE1S1I, OFE1S1J, OFS1S1B, OFS1S1D, OFS1S1I, OFS1S1J ORCA Web Site PIC Registers/DDR: HIODDR, HIOSR2, HIOSR4, HOSR2X2, IODDR, IOSR2, IOSR4, OSR2X2 ORCA FAQs 2-I/P Func. Generators: OEAND2, OEND2, OENR2, OEOR2, OEXNOR2, OEXOR2, OSAND2, OSND2, OSNR2, OSOR2, OSXNOR2, OSXOR2 Tech Support PCM: DLL1XB, DLL1XT, DLL2XB, DLL2XT, DLLPDB, DLLPDT, PLLB, PLLT, PCMBUFB, PCMBUFT Index Memory: DCE32X4, RCE32X4, ROM16X1, ROM32X1, ROM32X4, BR512X18 , BR1024X18, CAM2X256X16, CMULT16, FF512X18, FF256X36, FF1024X9, FF2X512X9, MULT8X8, SBR512X18, SBR1024X18, ULIM, ULIS
Note
Use port references for net connections when instantiating ORCA library cells. Refer to the ORCA Macro Library for cell port names.
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GO TO ¾ Figure 7a. Instantiating an ORCA 4-bit Loadable Counter in Verilog HDL
Table of Contents module cntup (d, carry_in, enable, clk, c); input [3:0] d; /* loadable data */ Cover input carry_in, enable, clk; Page output [3:0] c; /* count */
ORCA LU4P3AY u1(.D0(d[0]),.D1(d[1]),.D2(d[2]),.D3(d[3]), Web Site .SD(set),.CI(carry_in),.SP(enable),.CK(clk), .Q0(c[0]),.Q1(c[1]),.Q2(c[2]),.Q3(c[3])); ORCA FAQs endmodule
Tech Support
Index
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GO TO ¾ Figure 7b. Instantiating an ORCA 4-bit Loadable Counter in VHDL
Table of Contents library IEEE, orca; use orca.orcacomp.all; Cover use IEEE.std_logic_1164.all; Page entity cntup is ORCA Web Site port( d : in std_logic_vector(3 DOWNTO 0); carry_in, enable, clk : in std_logic; ORCA c : out std_logic_vector(3 DOWNTO 0) ); FAQs end cntup;
Tech Support architecture counter of cntup is
component LU4P3AY Index port( D : in std_logic_vector(3 DOWNTO 0); CI, SP, CK, SD : in std_logic; CO : out std_logic; Q : out std_logic_vector(3 DOWNTO 0) ); end component;
signal set : std_logic;
begin
u1 : LU4P3AY port map( D(0) => d(0), D(1) => d(1), D(2) => d(2), D(3) => d(3), CI => carry_in, SP => enable, CK =>clk, SD =>set, CO =>open, Q(0) =>c(0), Q(1) => c(1), Q(2) => c(2), Q(3) => c(3) );
end counter;
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GO TO ¾ Hard Macro Instantiation
Table of This section discusses the methodology for instantiating hard macros in your design. Hard Contents macros are created with EPIC.
Cover When a design containing a hard macro instantiation is read in, the designer must identify Page the input and output pins on the hard macro and the appropriate port names and also define the component as a black box. ORCA Web Site Note ORCA FAQs Hard Macro Instantiation is necessary for taking advantage of certain ORCA-specific architecture features which are not available through Tech synthesis. For example, if the design requires an 11-input XOR Gate, Support create a macro containing two 5-input XOR Gates and a PFUXR.
Index This hard macro is treated as a black box in the Synplify environment. The designer has to define the black-box component in his HDL design file with the proper black box attributes.
Figure 8a. Instantiating a Black Box Component in Verilog HDL
module DCE16X2Z ((AD0, AD1, AD2, AD3, DI0, DI1, CK, WREN, WPE, TRI, RAD0, RAD1, RAD2, RAD3, DO0, DO1, RDO0, RDO1); // synthesis black_box
input AD0, AD1, AD2, AD3, DI0, DI1, CK, WREN, WPE, TRI, RAD0, RAD1, RAD2, RAD3; output DO0, DO1, RDO0, RDO1;
endmodule
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GO TO ¾ Figure 8b. Instantiating a Black Box component in VHDL
Table of Contents architecture structure of top is
Cover attribute black_box: boolean; Page component DCE16X2Z port (AD0: in std_logic; AD1: in std_logic; AD2: in std_logic; AD3: in std_logic; ORCA Web Site DI0: in std_logic; DI1: in std_logic; CK : in std_logic; WREN: in std_logic; WPE: in std_logic; TRI: in std_logic; ORCA FAQs RAD0: in std_logic; RAD1: in std_logic; RAD2: in std_logic; RAD3: in std_logic; DO0: out std_logic; DO1: out std_logic; Tech RDO0: out std_logic; RDO1: out std_logic); Support end component; attribute black_box of DCE16X2Z: component is true; Index begin ...... end;
The designer may also instantiate other cells from the ORCA cell library. Use port references for net connections when instantiating ORCA library cells. Refer to the ORCA Macro Library section of the ORCA Libraries Manual for cell port names.
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GO TO ¾ SIMULATION OF NETLISTS GENERATED BY SYNPLIFY
Table of Contents After synthesizing to an ORCA device, an EDIF netlist is generated by the tool to take into the ORCA design flow in Project Navigator, or from the command line if you prefer. Cover Before taking the netlist into the back-end tools, the designer can functionally verify the Page correctness of the synthesized design by writing out a VHDL/Verilog netlist and then simulating the design using a standard VHDL/Verilog simulator. Select the Impl Options button in the Synplify GUI and the Implementation Results tab to select the options to ORCA Web Site write out VHDL/Verilog netlists. When Synplify is run with these options, the tool will generate a .vhm VHDL netlist file and/or a .vm Verilog netlist file in addition to the EDIF file generated. ORCA FAQs In order to simulate the design, use a standard VHDL/Verilog simulator. Note with the current release of Synplify, no ORCA libraries are needed. Synplify generates behavioral Tech code for all the ORCA library cells used in the design. For VHDL simulation, the designer Support has to create a library called synplify and compile into that directory the file: synplify.vhd shipped with the Synplify software in the synplcty/lib/vhdl_sim/ directory. The designer Index would then be ready to simulate the design using a standard VHDL simulator. The .vm Verilog netlist can be directly simulated using a standard Verilog simulator. Simulating the synthesized netlist prior to map, place and route, ensures functional correctness of the design through Synthesis.
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GO TO ¾ DESIGN IMPLEMENTATION
Table of Contents In this step of the design process, the circuit is mapped, placed and routed using the following steps:
Cover Page • Compile the EDIF netlist for ORCA with the ORCA design flow process Map Design in the Processes window in Project Navigator. You can also use the map command line option. The output of the mapping phase is an NCD data base, a ORCA physical design file, named
ORCA • To analyze the timing of your design, use the Place & Route TRACE Report process FAQs (trce). • To interactively edit the physical design, use EPIC. Tech Support Figure 9 shows a typical design implementation flow using the ORCA tools. For a complete description of how to use the ORCA design implementation tools, see the Index appropriate topic in the online help system.
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GO TO ¾ Figure 9. Design Implementation
Table of Contents ORCA Build Database Cover .ngd Page (Logical Generic Description) File
ORCA Web Site Map Design ORCA FAQs
Tech Preferences Timing Support EPIC Device- Editor Specific Analysis Design Files Index
Place & Route Design
.ncd (Circuit Description) File
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GO TO ¾ DESIGN VERIFICATION
Table of Contents Design verification involves three operations: • (Optional) Using a standard supported simulator to perform full timing simulation of Cover the Verilog, VHDL, or EDIF output file generated by ORCA. Currently, we support Page Model Technology V-System and Synopsys VSS simulators for VITAL (VHDL) simulations, Cadence Verilog-XL for Verilog simulations, and Viewlogic® ORCA Viewsim® for EDIF simulations. Web Site • Producing a data bitstream that will be written into the device.
ORCA • Physically loading the configuration data into the device. FAQs Note Tech Support You do not have to simulate the design to perform the second and third operations shown above. Index For a complete description of how to use the ORCA design verification tools, see the appropriate topic in the online help system and the appropriate simulator interface and reference manuals.
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GO TO ¾ THE ORCA ENVIRONMENT in ispLEVER
Table of Contents This section discusses the method for reading Synplicity-created EDIF designs into the ORCA ispLEVER design environment. It addresses only the process of mapping a Synplicity EDIF netlist into a circuit description, or physical design (.ncd) file. Once the Cover Page design is represented as an .ncd, the full complement of the ORCA tools may operate on it. This includes providing detailed static timing analysis of the design and creating a physical implementation of the design using timing driven PAR and bitgen. ORCA Web Site Mapping the Design ORCA Each of the ORCA tools may be run from either the command line or from within FAQs automatically from within ispLEVER’s Project Navigator. The following steps describe how to convert the Synplicity-created .edn into an ORCA .ncd design file using Project Tech Navigator. Support 1. Import your source file in a new ORCA project in Project navigator using the Source Index > Import command.
2. Before running the design flow, set your Map properties. Properties are mapping options. To set properties, right click on the Map Design process in the Processes window and select Properties. A Properties dialog will open. For example, the Pack Logic Blocks factor varies from 0 to 100, with 0 indicating a very tight pack and 100 indicating a loose packing. Press F1 in the dialog box to see online help for each option.
3. If desired, import an existing preference (.prf) file (e.g., you may wish to specify a previously created preference file, perhaps containing I/O specifications,for the design) using the Source > Import Constraint File.
4. Run Map Design in the Processes window.
The Map Design process creates a script file (output_filename.msc) which is run (and may be later modified and rerun). Then the Build Database process ( (ngdbuild) creates the generic database (.ngd) design file, which contains the fully expanded design. Finally, the Map Design process creates the circuit description (.ncd) file, which represents the mapped physical FPGA design.
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GO TO ¾ The timing constraints which are contained within the preference (.prf) file are written into the .ngo files as Preference Language preferences. These constraints are then written into Table of the .prf preference file during the technology mapping operation. Contents The next step in the process is to run the Map TRACE Report process (trce) on the Cover mapped design to get an estimate of the logic delays, number of logic levels, and the Page critical paths.
ORCA For additional information on how to run other ORCA tools in the design flow, refer to the Web Site appropriate ORCA Flow topic in the ispLEVER Flow Help system.
ORCA FAQs
Tech Support
Index
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GO TO ¾ APPENDIX Table of Contents APPENDIX
Cover Memory Initialization Page The ORCA memory components can be initialized by writing out the initial values (INITVAL) in the EDIF netlists. In the ORCA/Synplicity design flow this can be done by ORCA Web Site passing INITVAL attributes through the HDL design:
ORCA Setting Initial Values in the in the HDL File FAQs The following steps outline how pass initial values for the RAM/ROM elements in an ORCA design using the ORCA/Synplicity design flow: Tech Support 1. The ORCA INITVAL or INIT property is used to specify the initial values for the memory elements in ORCA. In order to specify it in the Synplicity flow, the instance Index name of the memory element must be known. The best way to do this is to instantiate the memory element in the HDL design and specify the initial value through the INITVAL property on the instance, using the VHDL attribute construct or the Synplify synthesis directive in Verilog. Please refer to the Synplify On-line help for more information on Synthesis Directives and Attributes for designing using Synplify. For all initial values, the format is the highest to lowest address.
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GO TO ¾ Setting Initial RAM Values
Table of For all initial values, the format is the highest to lowest address. Contents For example, for a 16x8 RAM, each initial value should consist of 16 2-bit binary or hex Cover values as follows: Page attribute INITVAL of RAM1: label is "00011011000110110001101100011011"; ORCA (or in hex as: "0x01230123012301230123") Web Site attribute INITVAL of RAM2: label is "10011011100110111001101110011011"; attribute INITVAL of RAM3: label is "01001100010011000100110001001100"; ORCA attribute INITVAL of RAM4: label is "00110011001100110011001100110011"; FAQs This would put an initial value in the address locations of the 16x8 RAM. Tech Support For a 32x2 RAM, similarly it would be:
Index attribute INITVAL of RAM1: label is "00011011000110110001101100011011"; attribute INITVAL of RAM2: label is "01001100010011000100110001001100";
RAM2 represents address locations 31–16, RAM1 represents address locations 15–0. This would put an initial value of ’01’ in address ’31’ and a ’00’ in address location ’15’ of the 32x2 RAM.
RAM initial values must be assigned on an individual basis.
Examples of Memory Initialization through structural HDL netlists in Synopsys are shown below.
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GO TO ¾ Figure A-1. Structural VHDL Netlist with ORCA Memory Components Table of Contents library IEEE; Cover use IEEE.std_logic_1164.all; Page entity initest is port (waddr: in std_logic_vector(3 downto 0); ORCA datain: in std_logic_vector(3 downto 0); Web Site clk: in std_logic; wren: in std_logic; ORCA raddr: in std_logic_vector(3 downto 0); FAQs dataout: out std_logic_vector(3 downto 0)); attribute din : string; attribute dout : string; Tech attribute loc : string; Support attribute loc of wren : signal is "56"; attribute din of wren : signal is ""; Index end initest;
architecture Structure of initest is -- internal signal declarations signal scuba_vhi: std_logic; -- local component declarations
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GO TO ¾ Figure A-1 (cont’d). Structural VHDL Netlist with ORCA Memory Components (continued) Table of Contents component DCE16X2 port (AD0:in std_logic;AD1:in std_logic;AD2:in std_logic; Cover AD3:in std_logic;DI0:in std_logic;DI1:in std_logic; Page CK:in std_logic;WREN:in std_logic;WPE:in std_logic; RAD0:in std_logic;RAD1:in std_logic; ORCA RAD2:in std_logic;RAD3:in std_logic; Web Site DO0:out std_logic;DO1:out std_logic; RDO0:out std_logic;RDO1: out std_logic); ORCA end component; FAQs component VHI port (Z: out std_logic); end component; Tech attribute INITVAL : string; Support attribute INITVAL of mem_0_0_1 : label is "0x0000000000000000"; Index attribute INITVAL of mem_0_1_0 : label is "0x12135D24204A98C6";
begin -- component instantiation statements mem_0_0_1: DCE16X2 port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>waddr(2), AD3=>waddr(3), DI0=>datain(2), DI1=>datain(3), CK=>clk, WREN=>wren,WPE=>scuba_vhi,RAD0=>raddr(0),RAD1=>raddr(1), RAD2=>raddr(2), RAD3=>raddr(3), DO0=>open, DO1=>open, RDO0=>dataout(2), RDO1=>dataout(3));
scuba_vhi_inst: VHI port map (Z=>scuba_vhi);
mem_0_1_0: DCE16X2 port map (AD0=>waddr(0), AD1=>waddr(1), AD2=>waddr(2), AD3=>waddr(3), DI0=>datain(0), DI1=>datain(1), CK=>clk, WREN=>wren, WPE=>scuba_vhi, RAD0=>raddr(0), RAD1=>raddr(1), RAD2=>raddr(2), RAD3=>raddr(3), DO0=>open,DO1=>open,RDO0=>dataout(0), RDO1=>dataout(1));
end Structure;
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GO TO ¾ Figure A-2. Structural Verilog Netlist with ORCA Memory Components
Table of `timescale 1 ns / 100 ps Contents module initest (waddr,datain,clk,wren,raddr,dataout); input [3:0] waddr; Cover input [3:0] datain; Page input clk; input wren /* synthesis din="" LOC="56" */; ORCA input [3:0] raddr; Web Site output [3:0] dataout; DCE16X2 mem_0_0_1 (.AD0(waddr[0]), .AD1(waddr[1]), .AD2(waddr[2]), .AD3(waddr[3]), .DI0(datain[2]), ORCA .DI1(datain[3]), .CK(clk), .WREN(wren), FAQs .WPE(scuba_vhi), .RAD0(raddr[0]),.RAD1(raddr[1]), .RAD2(raddr[2]), .RAD3(raddr[3]), Tech .RDO0(dataout[2]), .RDO1(dataout[3])) Support /* synthesis INITVAL="0x0000000000000000" */; VHI scuba_vhi_inst (.Z(scuba_vhi)); DCE16X2 mem_0_1_0 (.AD0(waddr[0]), .AD1(waddr[1]), Index .AD2(waddr[2]), .AD3(waddr[3]), .DI0(datain[0]), .DI1(datain[1]), .CK(clk), .WREN(wren), .WPE(scuba_vhi), .RAD0(raddr[0]),.RAD1(raddr[1]), .RAD2(raddr[2]), .RAD3(raddr[3]), .RDO0(dataout[0]), .RDO1(dataout[1])) /* synthesis INITVAL="0x12135D24204A98C6" */;
endmodule
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GO TO ¾ Using GSR in ORCA Designs With Synplify
Table of The ORCA family has a Global Set Reset (GSR) resource for global set and reset. Contents Synplify will automatically create a GSR instance to access the GSR resource if it is appropriate for the design. The GSR resource is a pre-routed signal that goes to the reset/ Cover preset input of each flip-flop in the FPGA. Using the GSR resource instead of general Page routing for the reset/preset signal has a significant positive impact on the routability and performance of the design. ORCA Web Site By default, if there is a single reset/preset used in the design, then Synplify will connect that reset/preset signal to a GSR instance. It will do this even if some flip-flops have no reset/preset at all. Usually, flip-flops without reset or preset may be safely initialized ORCA FAQs because the reset/preset is only used when the device is turned on. If this is not the case, then you must turn off the force GSR usage option. To turn off the GSR usage option, choose Set Device Options from the Target menu, and deselect the checkbox. When Tech Support Synplify sees this option turned off, it requires that all flip-flops have resets/presets and that the resets/presets are all the same, before it uses GSR.
Index Illegal Names/Characters in ORCA Design Flows Certain names and characters used in a design may cause problems at some point in your ORCA design flow. See the appropriate topic in the online help system for a list of names and characters to avoid.
Programmable GSR Support (Series 3) Programmable GSR support allows the user to disable the GSR functionality on selected register elements. This feature gives the user the ability to retain design information on a PFU basis when using GSR to set/reset the rest of the design.
The PUR component will now be used to set/reset register elements at power-up. GSR is used for global set/reset at all other times of operation. The PUR signal will need to be instantiated in your HDL design since it is currently not inferred.
In ORCA 2002 programmable GSR will be supported via an attribute attached to instantiated library cell instances in the HDL design netlist. The attribute is "DISABLED_GSR" with value "1". The resulting synthesized output EDIF netlist will contain the property "DISABLED_GSR" with value "1" for each component instance containing the attribute. The ORCA tools will recognize this property and disable the GSR functionality accordingly.
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GO TO ¾ Example VHDL to implement programmable GSR:
Table of library IEEE; Contents use IEEE.std_logic_1164.all; entity attr_chk is Cover port(d, clk, preset : in std_logic; Page qout : out std_logic ); architecture flop of attr_chk is ORCA component FD1S3BX Web Site generic (disabled_gsr: String); port(D, CK, PD : in_std_logic; ORCA Q, QN : out std_logic ); FAQs end component; attribute disabled_gsr: String; Tech attribute disabled_gsr of u1:label is "1"); Support begin u1 : FD1S3BX generic map (disabled_gsr => "1") Index port map( D => d, CK =>clk, PD => preset, Q => qout, QN => open); end flop;
Example Verilog to implement programmable GSR:
module attr_chk (d, clk, preset, qout); input d, clk, preset; output qout;
FD1S3BX u1(.D(d),.CK(clk),.PD(preset),.Q(qout)); defparam u1.DISABLED_GSR=1 // synthesis attribute DISABLED_GSR "1" endmodule
* Note that boldfaced code is necessary for simulation.
The HDL code examples include "generic map" entries (VHDL) and a "defparam" entry (Verilog). These must be manually added to your post-synthesis HDL netlist for simulation after synthesis. Synthesis tools currently do not produce these entries in their synthesized netlists.
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GO TO ¾ Passing Frequency Preferences (Series 3 and 4)
Table of FREQUENCY attributes will be converted into properties in the EDIF during synthesis Contents which the mapper will then translate into FREQUENCY preferences on the output of the PLL. You must ensure that the FREQUENCY values are consistent with the input clock Cover frequency, DIV0, DIV1, DIV2, DIV3 values and external divider, if any. Page The following example shows how attributes are passed in the HDL code using ORCA Synplicity: Web Site wire oclk2_t/*synthesis syn_keep=1 FREQUENCY = “30.000” */; wire oclk1_t/*synthesis syn_keep=1 FREQUENCY = “20.000” */; ORCA FAQs PPLL macro_synplify_0_0 (.CLKIN(clk), .FB(fb), .MCLK(oclk1_t), .NCLK(oclk2_t), .LOCK(lock), .INTFB(fb)) /* synthesis VCOTAP=”2” Tech */ /* synthesis NCLKMODE=”DELAY” */ /* synthesis MCLKMODE=”DELAY” Support */ /* synthesis DIV3=”2” */ /* synthesis DIV2=”3” */ /* synthesis DIV1=”4” */ /* synthesis DIV0=”1” */; Index assign oclk2 = oclk2_t; assign oclk1 = oclk1_t;
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GO TO ¾ INDEX Table of Contents A Overriding the default padtype, 22 Synopsys library model for hard macro Cover Attributes MUX4H, 48 Page passing FREQUENCY preference in HDL, 53 Verilog Adder/Subtracter addsub.v, 29 VHDL Adder/Subtracter addsub.vhd, 30 B Files ORCA orca2.v, 4 Bidirectional buffers Web Site orca2.vhd, 3 inferring in Verilog (figure), 27 orca3.v, 4 inferring in VHDL (figure), 28 orca3.vhd, 3 insertion, 27 ORCA orca4.v, 4 FAQs orca4.vhd, 3 D orca.v, 3 Tech Design orca.vhd, 3 Support entry, 10 .sdc (constraint), 12 environment FREQUENCY preference, 53 setting, 2 Index flow, 5 G (figure), 6 GSR implementation, 41 defining in Synplify, 51 (figure), 42 verification, 43 H E Hard macro instantiation, 38 EDIF reading designs, 44 I Environment variables, 2 I/O placing registers near, 26 F I/O buffers (table), 17 Figures insertion, 17 Design flow, 6 instantiating in Verilog HDL (figure), 20 Design implementation, 42 instantiating in VHDL (figure), 21 Inferring Bidirectional Buffers in Verilog, 27 I/O macrocell instantiation, 17 Inferring Bidirectional Buffers in VHDL, 28 I/O padtypes, 22 Instantiating a Black-box Component in (figure), 22 Verilog HDL, 38 I/O pins Instantiating an ORCA 4-bit Loadable Counter locking, 23 in Verilog HDL, 36 locking (figure), 24, 25 Instantiating an ORCA 4-bit Loadable Counter Inferring in VHDL, 37 bidirectional buffers in Verilog (figure), 27 Instantiating I/O Buffers in Verilog HDL, 20 bidirectional buffers in VHDL (figure), 28 Instantiating I/O Buffers in VHDL, 21 Inserting bidirectional buffers, 27 Locking pins in a Verilog design, 25 Inserting I/O buffers, 17 Locking pins in a VHDL design, 24
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GO TO ¾ Instantiating P black-box component in Verilog HDL (figure), Padtypes Table of 38 Contents hard macros, 38 overriding the default, 22 I/O buffers in Verilog HDL (figure), 20 overriding the default (figure), 22 I/O buffers in VHDL (figure), 21 passing using Synplicity, 53 Cover I/O macrocells, 17 Placing registers near I/Os, 26 Page macrocells in ORCA Library, 31 ORCA 4-bit loadable counter in Verilog HDL R (figure), 36 Reading ORCA ORCA 4-bit loadable counter in VHDL EDIF designs, 44 Web Site (figure), 37 Registers placing near I/Os, 26 ORCA L Requirements FAQs Libraries software, 1 ORCA Macro, 31 S Tech Synplify, 3 Locking I/O pins, 23 Support .sdc (constraint) files, 12 in a Verilog design (figure), 25 Series 4 in a VHDL design (figure), 24 synthesis using VHDL and Verilog, 7 Index Series 4 architecture M synthesis with Synplicity, 7 Macrocell instantiation Setting and ORCA library elements, 31 design environment, 2 I/O, 17 timing constraints, 14 MAP Software requirements, 1 mapping the design, 44 Synopsys Memory initialization, 46 library model for hard macro MUX4H (figure), 48 O Synplicity synthesizing Series 4 designs in, 7 ORCA Synplicity Synplify input/output buffers (table), 17 passing FREQUENCY preferences as Macro library, 31 attributes in HDL, 53 orca2.vhd library file, 3 Synplify orca2.v library file, 4 library files, 3 orca3.vhd library file, 3 timing attributes, 14 orca3.v library file, 4 timing reports, 16 orca4.vhd library file, 3 using GSR, 51 orca4.v library file, 4 Synthesis ORCA Foundry passing FREQUENCY preferences during, 53 environment, 44 orca.vhd library file, 3 T orca.v library file, 3 Overriding the default padtype, 22 Timing (figure), 22 attributes, Synplify, 14 constraints, 14, 45 reports, Synplify, 16
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GO TO ¾ V Verilog Table of Contents adder/subtracter addsub.v (figure), 29 inferring bidirectional buffers (figure), 27 Cover instantiating Page black box component, 38 I/O buffers (figure), 20 ORCA 4-bit loadable counter (figure), 36 ORCA VHDL Web Site adder/subtracter addsub.vhd (figure), 30 inferring bidirectional buffers (figure), 28 ORCA instantiating FAQs I/O buffers (figure), 21 ORCA 4-bit loadable counter (figure), 37 Tech using to synthesize Series 4 design, 7 Support
Index
ORCA/Synplicity Interface Manual 56 Index