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Digital Design Tools Guide

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Digital Design Tools Guide LATTICE SEMICONDUCTOR Digital Design Tools Guide Lattice’s new ispDesignEXPERT ™ combines the power of HDL and ISP™ devices to support design with all ispLSI,® ispMACH,™ MACH,® ispGDX,® ispGAL,® GAL® and PAL® products. These tools are targeted to maximize user productivity and device performance. Linked with industry-leading third party VHDL and Verilog Synthesis and RTL Simulation tools from Exemplar Logic,® Model Technology,® Synplicity,® Synopsys ® and I Advanced Design Assistant Tools ® Innoveda (formerly Viewlogic ), these systems provide a fully integrated • Performance Analyst and ispTA front to back design solution. • Explore Tool • Pin Editor Key Features: • Physical Viewer I Powerful Open Systems • ispANALYZER I Push Button Operation I Lattice Functional and Timing I Shrink Wrapped Solutions Including Simulator Leading CAE Vendor Tools I Total ISP Programming Tools • Exemplar Logic I UNIX Solutions • Model Technology • Combined UNIX Release • Synplicity Includes: • Innoveda - DesignDirect-Summit (Workstation) I Easy to Learn and Use I Design Support for all Lattice Devices - ispDesignEXPERT Compiler- Advanced (Workstation) • CPLD, ispGDX & SPLD Design Support I HDL Optimized Logic Compiler Leading Third Party Tools I Lattice Schematic Tools I VHDL and Verilog Synthesis I ABEL-HDL Entry I RTL Simulation Tools I Schematic Entry I State Machine Entry I Functional and Timing Simulation Product Offering orkview Office Exemplar ispDesignEXPERT Products MacrocellSupport LevelLeonardoSynplicity SpectrumSynplifySynopsysFPGA ExpressViewlogicW ModelModelSIM Tech License Type ispDesignEXPERT–HDL (Base) ≤600 GG GNode Locked ispDesignEXPERT–HDL (Advanced) ALL GG GNode Locked ispDesignEXPERT–Viewlogic (Base) ≤600 GG Node Locked ispDesignEXPERT–Viewlogic (Advanced) ALL GG Node Locked ispDesignEXPERT–Exemplar (Advanced) ALL GGFloating ispDesignEXPERT (Starter) ≤600 G Node Locked ispDesignEXPERT (Advanced) ALL Floating UNIX Design Tools ALL Floating 1 Complete Third Party Support ulation SynthesisSchematicCompilerSim PC UNIX ispLSI ispMACH/MACH Aldec GG GG G Cadence GG G GGG ExemplarLogic GGGGG Mentor Graphics GG G GGG Model Technology GGGGG OrCAD (Cadence) GG GGG GG Synopsys GGGGG Synplicity GGGGG VeriBest (Mentor Graphics) GG GG G Innoveda (Viewlogic) GG GGGGGG OVI Compliant Verilog GGGGG VITAL Compliant VHDL GGGGG Software Ordering Information Product Part Number Maintenance Maintenance Reinstatement* ispDesignEXPERT-HDL (Base) DE-HDL-BASE-PC-N DE-HDL-BASE-PCM-N DE-HDL-BASE-PCMR-N ispDesignEXPERT-HDL (Advanced) DE-HDL-ADV-PC-N DE-HDL-ADV-PCM-N DE-HDL-ADV-PCMR-N ispDesignEXPERT-Viewlogic (Base) DE-VLG-BASE-PC-N DE-VLG-BASE-PCM-N DE-VLG-BASE-PCMR-N ispDesignEXPERT-Viewlogic (Advanced) DE-VLG-ADV-PC-N DE-VLG-ADV-PCM-N DE-VLG-ADV-PCMR-N ispDesignEXPERT-Exemplar (Advanced) DE-EXM-ADV-PC-F DE-EXM-ADV-PCM-F DE-EXM-ADV-PCMR-F ispDesignEXPERT-Starter n/a n/a n/a ispDesignEXPERT (Advanced) DE-ADV-PC-F DE-ADV-PCM-F DE-ADV-PCMR-F UNIX Design Tools EXDD-ADV-WS-F EXDD-ADV-WSM-F EXDD-ADV-WSMR-F Innoveda-Speedwave VHDL PDS3307-PC3 PDS3307M-PC3 PDS3307MR-PC3 Simulator (Advanced) *Maintenance period lapsed longer than 60 days Maintenance for Continued Support Platform Support One year of maintenance support is included with the purchase I PC of every Lattice software product. Annual maintenance agreements • Windows 2000 are available to cover continued device and feature support. • Windows NT 4.x • Windows 98 • Windows 95 I UNIX • Solaris 2.5, 2.6 • HPUX 10.x 2 Lattice’s ispDesignEXPERT is a fourth generation logic Design Entry compiler supporting ispLSI, ispMACH, MACH, GAL and PAL design. Lattice has teamed with leaders in third party synthesis VHDL and Verilog Lattice offers synthesis tools from and simulation software, such as Exemplar Logic, Model the world’s leading CAE vendors Technology, Synopsys, Synplicity, and Innoveda Systems, I Exemplar Logic to provide the very best in design entry, verification, and I Synopsys implementation tools. With ispDesignEXPERT, designing with I Synplicity Lattice programmable devices is easy and efficient. Lattice Schematic and Symbol Editor Each design tool package includes Lattice’s Schematic and Symbol Editor I Hierarchical Design I Mixed Language and Schematic I Extensive Primitive Library ABEL ABEL language entry is included in every Lattice design tool package I Powerful Syntax I Familiar and Easy to Use ispDesignEXPERT– Product Navigator I Built-in Text Editor Whether you use schematic, state machine, ABEL or high-level VHDL and Verilog design entry, ispDesignEXPERT is optimized for high performance logic implementation. Advanced Design Assistants provide quick and easy design analysis and debug capabilities. Innoveda’s ViewDraw Included in Lattice’s Viewlogic packages, ViewDraw allows mixed mode design I Mixed Schematic and VHDL Design I Schematic and Symbol Editor I Dynamic Links to Simulator 3 Simulation and Verification Design Assistants Programming ModelSIM Pin Assignment Editor ispVM™ System ModelSIM, a world leader in simulation, Graphical pin editor for ispLSI PC programming tools integrated is included with each of Lattice’s HDL device design into the Project Navigator and Exemplar tools I Define and Assign Pins Graphically I ISP Daisy Chain Download I VHDL and Verilog RTL Simulator I Point and Click Operation I LatticePRO I Gate-Level Timing Simulator I Multiple Views I ispVM Download I Integrated into the Project Navigator ispVM EMBEDDED New Virtual Machine source pro- Lattice Simulator grams which can be embedded into Physical Viewer Included in every package and microprocessor or microcontroller completely integrated into the Graphically displays design routines for programming devices implementation details design flow I Single Chain In-System I I Gate-level Timing Simulator Displays Logic Resource Usage Programming I I Functional Equation Simulator Shows Data Propagation Paths I Multi-Vendor I I Waveform Viewer Device Navigator and Connectivity I Multi-Device Windows Innoveda’s ViewSim ispATE® Static Timing Analyzers ViewSim is a high performance, Built-in utility generates program- event-driven digital simulator Performance Analyst and ispTA for ming vectors for popular final ispMACH and ispLSI devices board test equipment I Timing and Functional Simulator I Spreadsheet Format I Genrad, HP, Teradyne, Marconi I Back Annotation to ViewDraw I Trace any Path with a Simple Click Support I Co-simulation Interface to I I Graphical User Interface SpeedWave Path Analysis Based on Sources and Destinations Innoveda’s SpeedWave-Lite ispANALYZER VHDL RTL and timing simulator included with Lattice’s Viewlogic products A unique tool to simplify in-system debugging I RTL and Gate-Level Capabilities I Probe Internal Registers and Nodes I VHDL Bounds Checking Feature I No Disruption of the Logic Design I Co-simulation Interface to ViewSim I Graphical Interface Automatically Lists Observable Nodes and Available Pins 4 The ispDesignEXPERT-Starter provides the full capabilities of ispDesignEXPERT for devices up to 600 macrocells. ispDesignEXPERT-Starter provides multiple options for device entry, device fitting, timing analysis, debug tools, and programming utilities. Download the software from the Web, or request a Starter CD and start designing today! Key Features I VHDL I Verilog I ABEL I Schematic I Functional Simulator I Timing Simulator I Static Timing Analysis I Explore Tool* I Pin Editor* I Physical Viewer* I ispANALYZER* I Third Party Design Libraries I Industry Standard Interfaces *ispLSI Devices Only ispDesignEXPERT– Starter Product Navigator The ispDesignEXPERT-Starter Kit is a comprehensive design tool kit which allows you to develop designs up to 600 macrocells. This kit enables you to evaluate the potential of designing with Lattice ISP devices quickly and easily. The kit includes: I ispDesignEXPERT and LatticePRO Software CD-ROM I 44-pin In-System Programming (ISP™) Board with LED Display I ispDOWNLOAD® Cable I MACH ISP Manual I MACH 4-32/32 and MACH 4-64/32 Sample Devices 5 Device Programming is quick and easy from the engineering desktop to the final board test facility. Lattice’s newest innovation, ispVM EMBEDDED, provides in-system programming through the target board’s own microprocessor or microcontroller. ispVM® System Top level GUI launches Lattice programming tools. Supports ispLSI, ispMACH, MACH, ispGAL, ispGDX, and ispGDS® device programming. Includes Turbo ispDOWNLOAD, ispATE and ispSVF™ programming. I ispVM Download • Supports Multi Vendor Programming • Supports Serial Programming of ANY ISP Device I ISP Daisy Chain Download • Supports ispLSI, ispGAL, ispGDX, and ispGDS Device Programming • Includes Turbo ispDOWNLOAD, ispATE and ispSVF Programming I LatticePRO • Supports Select ispLSI and ispMACH/MACH Device Programming Embedded Programming I ispVM EMBEDDED • Virtual Machine Based Programming Utility ispVM System –Total ISP Programming • True Multi-Vendor Support • Fast Programming Times and Small File Sizes I C Source Code Routines • JTAG ISP-Source Code • ispCODE Lattice’s ispGDX Development System is a self contained tool for designing ispGDX/V devices. Using a simple design description language, users can create highly integrated designs quickly and easily. Key Features Self Contained Design Tool Built-In Text Editor Supporting ispGDX/V Device Detailed Timing Reports and Design On-line Help I VHDL/Verilog Language Design Interfaces to Industry Standard through Addition of Synplify Simulators for Timing Verification Synthesis Tool PC and UNIX Versions ispGDX Development
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