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A Guide to Modern Fpgas Fpgas Are Growing Fast in Technology and Density TECHNOLOGY FOCUS A Guide to Modern FPGAs FPGAs are growing fast in technology and density. The latest advances have generally helped the design engineer to handle complex designs in FPGAs with better accuracy in lesser time. Let us see how it is done takes, similar to how it is done for ASIC design tools. The tool itself takes care of so many things, saving your valuable time in repeating the design process. Denser FPGAs One of the points I came across in a white paper from Altera was that, be- cause of shrinking of design cycles and design teams, cost-conscious designers were trying to move away from multi- chip solutions that were too costly and lacked flexibility. They were also mov- ing away from single-chip solutions that could not meet power or performance objectives, or ASIC systems on chips (SoCs) which are too slow to get to market. Microsemi IGLOO2 FPGA ARM-based SoCs combine a hard ARM processor, memory controllers and peripherals with customisable ANAGHA P. key here is the ASIC-like class archi- FPGA fabric in a single SoC. Initially, tecture. There are several changes FPGAs were not dense enough and did esign architects are now we made in the architectures that are not have hard cores on them. more comfortable select- like ASICs. ASICs are always good in Now, even for a single family of ing a field-programma- power and performance. product, the user has quite a few op- ble gate array (FPGA) as “FPGAs, traditionally, have an tions to select from, such as ARM-based the central piece on the overhead, but we are trying to bridge SoCs that are user-customisable. This Dboard. Given the quantum of vendor this gap, and we did quite well in helps reduce system power and board and community resources available at 28nm. But in 20nm, we are going to do size while increasing system perfor- their disposal, FPGAs makes it easier even better.” for them to complete their design with- Earlier, FPGAs had few global in stipulated timelines and budget. clocks. As the density grew, FPGAs are now capable of serving as skew problem also increased. suitable alternatives to application-spe- Vendors, such as Xilinx, added cific integrated circuit (ASIC) or applica- more clocking regions, resulting tion specific standard product (ASSP) in more clocking resources placed implementations in many systems—so at different areas of the chip. This is much so that some vendors are market- how exactly it is done in ASICs to solve ing their FPGAs as ASIC-likes. skew problem, and this is the reason Neeraj Varma, director of sales why it is called an ASIC-class clocking. at Xilinx explained in an interview, Here, the software used is also an “The whole belief is that the FPGAs in ASIC-strength design suite. The design UltraScale generation have a lot many suite has many built-in features where more features that are ASIC-like. The you are not allowed to make any mis- Virtex C2 AE-5 TXT FPGA from Xilinx 52 MAY 2014 | ELECTRONICS FOR YOU WWW.EFYMAG.COM TECHNOLOGY FOCUS mance by integrating discrete FPGAs, Selecting FPGAs for an application digital signal processing (DSP) and microprocessor devices into a single, High-end FPGAs feature: Low-end FPGAs feature: High performance Low power consumption per chip user-customisable SoC. High logic density Low cost The built-in hardcore IP cores, High-speed interfaces Low complexity which were not present earlier, are UltraScale and 3D architecture Low speed of operation available now, providing more predict- Support complex features, architectural Low logic density able performance figures. Every year blocks and intensive computations Low-speed interconnects High power consumption Do not support some features and we see shrinking of the process node High cost architectural blocks in line with the industry growth and Example: Virtex family by Xilinx, Example: Spartan family by Xilinx, Moore’s Law. Now 45nm, 28nm, 20nm Stratix family by Altera, ProASIC3 family Cyclone family by Altera, Mach XO and and 16nm FPGAs are available. Also, by Microsemi and Speedster 22i family ICE40 families by Lattice Semiconductor now we are moving towards 14nm by Achronix and Fusion family by Microsemi and 10nm nodes. This favours better Mid-range FPGAs density and reduction of power. The mid-range FPGAs are an optimal solution that provide the users with a balance of cost and performance. Adaptive look-up tables Example: Artix-7 and Kintex-7 series by Xilinx, Arria series by Altera, ECP5/ECP3 series Over the years, the basic building by Lattice Semiconductor and IGLOO2 series by Microsemi block of the FPGA logic fabric—the look-up table (LUT) based function Selecting FPGAs generator—has remained almost the Over the past few years, a distinct same. Experimentations were done segmentation of FPGA vendors has with the number of inputs for LUT occurred depending on the device such as three, four, six and eight. Now capabilities: distinct high-end and they have adaptive LUTs which allow low-end product lines. If the applica- two outputs per LUT with two func- tion requires intensive computation, tion generators to be implemented, the FPGAs preferred are those with sharing some of the inputs. The FPGAs complex DSP blocks, high-speed in- mainly evolved by providing the same puts/outputs (I/Os) and configurable set of resources with different number memories. They are seen serving con- of resources per family. sumers looking at ultra-high-definition Lattice ECP3 low-power FPGA In addition, today it is all about televisions, 3D televisions and medical providing ecosystems to the design- applications, such as 265-channel ultra- mance, FPGA families, such as Spartan, er—evaluation boards, reference de- sound. Examples of FPGAs delivering Cyclone ECP5 and Fusion, are used. signs, design communities and partner these requirements are Virtex, Stratix, Typical applications include emerg- IPs, ensuring FPGAs are able to meet ProASIC3 and Speedster 22i. ing communication products, such the stringent time-to-market goals of For low-cost applications, where as heterogeneous networks (HetNet), the customer. a trade-off has to be made for perfor- gigabit passive optical network optical line terminals (GPON OLTs) and small Things to consider while selecting an FPGA form-factor pluggable (SFP) modules. If we presume that a device meets the basic design requirements, the next four things an engineer needs to consider are power consumption, board space, solution cost and design Choice of process node time. Whatever the application may be, these four factors can bias an engineer’s decision Process nodes are available in 45nm, across the vendors. When it comes to low power consumption, iCE40 FPGA family from Lattice 40nm, 32nm, 28nm, 22nm, 20nm and Semiconductor and IGLOO series of low-power FPGAs from Microsemi are some great 16nm values. The 10nm nodes are al- choices in most low-power and battery-operated applications. It is particularly favourable ready under development. in the Internet of Things (IoT) space where ultra-low-power programmable devices with From the user’s perspective, a ultra-small packaging are what a design engineer would be looking for. process node is not everything and the Available resources, such as look-up tables (LUTs), registers, I/Os, phase-locked loops (PLLs) and memory, are considered before selecting an FPGA. user does not have much control on Another point to look for is the dedicated hard blocks that could be interfaced with the it. Provided a device meets the design FPGA, such as the physical coding sublayer (PCS), peripheral component interconnect specifications, power and cost budgets express (PCIe) end point and double data rate (DDR) memory controller. These could be and availability, designers often tend added to the periphery for high-speed interface with the external world. to overlook the process node. If the application requires a processor and an FPGA, then user-customisable SoCs are the best choice. However, because of the reduc- tion in process node values, the newer WWW.EFYMAG.COM ELECTRONICS FOR YOU | MAY 2014 53 TECHNOLOGY FOCUS dyes are much denser and hence, for Major contributors to this report the same dye size of an older process Neeraj Varma, director of sales, Xilinx India node, more logic can fit in on the lower Rahul Prakash Joshi, technical manager, eInfochips process node devices. Thus, lower Rajesh Chakkingal, lead architect, Mistral Solutions process node certainly provides higher Rajiv Nair, regional sales manager - India, Lattice Semiconductor performance if the chip is fully utilised. Sheik Abdullah, project leader - FPGA design, iWave Systems Technologies Pvt Ltd Up to 130nm, as the process node Shubha S., senior tech lead, Dexcel Electronics Designs is lowered, the power and cost are also reduced. Beyond that, any decrease in size of the transistor will cause leak- interfaces for videos. age to increase. This results in higher The video applications power consumption. Due to this reason, require frame or line buff- relatively higher process nodes are more ering at multiple points in preferred for low-power consumption the path. With HD video, applications. the video resolution and the When we consider the higher power frame rates have increased. consumption due to leakage, the higher With high-performance clock rates that new nodes provided did devices, DDR memory in- not seem as much of a value proposi- terfaces, readily-available tion for every designer. But now with DDR controller IPs and the introduction of FinFET technology, high-speed I/Os, the FP- the semiconductor fabs and so FPGA GAs are meeting the re- Altera Stratix HC IV FPGA firms are able to solve this problem to quired high bandwidth for an extent. video applications. rived based on fast computations, pos- sibilities of platforms having multiple New and exciting fields FPGAs in other fields of application FPGAs with design comprising register- The wearable electronics market has transfer level (RTL), soft-core processor While the bread-butter market for been touted as the next big wave in and high-speed serial interfaces with FPGAs has always been wired/wire- consumer electronics industry.
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