FPGA Devices ECE 448 Lecture 5

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ECE 448 Lecture 5

FPGA Devices

ECE 448 – FPGA and ASIC Design with VHDL George Mason University Required reading

• Spartan-6 FPGA Configurable Logic Block: User Guide

§ CLB Overview § Slice Description

2 Recommended reading

Highly recommended for the Wednesday lab section using Nexys 4 boards

• 7 Series FPGAs Configurable Logic Block: User Guide

§ Overview § Functional Details

3 What is an FPGA?

Configurable Logic Blocks Block RAMs Block RAMs Block I/O Blocks

Block RAMs

ECE 448 – FPGA and ASIC Design with VHDL 4 Modern FPGA

RAMRAM bblockslocks Multipliers/DSPMultipliers units LogicLog resourcesic blocks

(#Logic resources, #Multipliers/DSP units, #RAM_blocks)

Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) 5 Major FPGA Vendors SRAM-based FPGAs ~ 51% of the market • Xilinx, Inc. ~ 85% • Altera Corp. ~ 34% of the market (subsidiary of Intel since 2015) • Lattice Semiconductor • Atmel • Achronix • Tabula (went out of business in 2015) Flash & antifuse FPGAs • Microsemi SoC Products Group (formerly Actel Corp.) • Quick Logic Corp.

ECE 448 – FPGA and ASIC Design with VHDL 6 Xilinx

u Primary products: FPGAs and the associated CAD software

Programmable Logic Devices ISE Alliance and Foundation Series Design Software

u Main headquarters in San Jose, CA

u Fabless* Semiconductor and Software Company

u UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}

u Seiko Epson (Japan)

u TSMC (Taiwan)

u Samsung (Korea)

ECE 448 – FPGA and ASIC Design with VHDL 7 Xilinx FPGA Families Technology Low-cost Mid-range High- performance 220 nm Virtex 180 nm Spartan-II, Spartan-IIE 120/150 nm Virtex-II, Virtex-II Pro 90 nm Spartan-3 Virtex-4 65 nm Virtex-5 45 nm Spartan-6 40 nm Virtex-6 28 nm Arx-7 Kintex-7 Virtex-7 FPGA Family

9 Spartan-6 FPGA Family

ECE 448 – FPGA and ASIC Design with VHDL 10 Artix-7 FPGA Family

ECE 448 – FPGA and ASIC Design with VHDL 11 CLB Structure

ECE 448 – FPGA and ASIC Design with VHDL George Mason University General structure of an FPGA

Programmable interconnect

Programmable logic blocks

ECE 448 – FPGA and ASIC Design with VHDL 13 Xilinx Spartan-6 & Artix-7 CLB

ECE 448 – FPGA and ASIC Design with VHDL 14 Row & Column Relationship Between CLBs & Slices

ECE 448 – FPGA and ASIC Design with VHDL 15 Basic Components of the Slice

LUTs

Storage Elements

ECE 448 – FPGA and ASIC Design with VHDL 16 Example of a 4-input LUT (Look-Up Table) (used in earlier families of FPGAs)

• Look-Up tables x1 x 2 y x x x x y x3 LUT x x x x y are primary 1 2 3 4 x 1 2 3 4 0 0 0 0 1 4 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 elements for 0 0 1 0 1 0 0 1 0 0 0 0 1 1 1 0 0 1 1 0 logic 0 1 0 0 1 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 implementation 0 1 1 1 1 0 1 1 1 1 1 0 0 0 1 1 0 0 0 0 1 0 0 1 1 1 0 0 1 1 • Each LUT can 1 0 1 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 1 0 implement any 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 x x x x function of 1 1 1 0 0 1 2 3 4 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 4 inputs

x1 x2

ECE 448 – FPGA and ASIC Design with VHDL 17 LUT of Spartan-6 and Artix-7

ECE 448 – FPGA and ASIC Design with VHDL 18 19 Reset and Set Configurations

• No set or reset • Synchronous set • Synchronous reset • Asynchronous set (preset) • Asynchronous reset (clear)

ECE 448 – FPGA and ASIC Design with VHDL 20 Three Different Types of Slices in Spartan-6

50% 25% 25%

ECE 448 – FPGA and ASIC Design with VHDL 21 Two Different Types of Slices in Artix-7

ECE 448 – FPGA and ASIC Design with VHDL 22 SLICEX

ECE 448 – FPGA and ASIC Design with VHDL 23 SLICEL

24 Fast Carry Logic

u Each SliceL and SliceM contains separate logic and routing for the fast generation MSB of sum & carry signals

• Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters Routing Carry Logic Carry u Carry logic is independent of LSB normal logic and routing resources

25 Accessing Carry Logic

u All major synthesis tools can infer carry logic for arithmetic functions • Addition (SUM <= A + B) • Subtraction (DIFF <= A - B) • Comparators (if A < B then…) • Counters (count <= count +1)

26 ECE 448 – FPGA and ASIC Design with VHDL 27 SLICEM

ECE 448 – FPGA and ASIC Design with VHDL 28 Xilinx Multipurpose LUT (MLUT)

132-bit6-bit SRSR

1646 x x 1 1 RRAMAM

464-in px u1t ROMLUT (logic)

29 Single-port 64 x 1-bit RAM

30 Single-port 64 x 1-bit RAM

31 Memories Built of Neighboring MLUTs

Memories built of 2 MLUTs:

• Single-port 128 x 1-bit RAM: RAM128x1S • Dual-port 64 x 1-bit RAM : RAM64x1D

Memories built of 4 MLUTs:

• Single-port 256 x 1-bit RAM: RAM256x1S • Dual-port 128 x 1-bit RAM: RAM128x1D • Quad-port 64 x 1-bit RAM: RAM64x1Q • Simple-dual-port 64 x 3-bit RAM: RAM64x3SDP (one address for read, one address for write)

32 Dual-port 64 x 1 RAM

• Dual-port 64 x 1-bit RAM : 64x1D • Single-port 128 x 1-bit RAM: 128x1S

33 Dual-port 64 x 1 RAM

• Dual-port 64 x 1-bit RAM : 64x1D • Single-port 128 x 1-bit RAM: 128x1S

ECE 448 – FPGA and ASIC Design with VHDL 34 Total Size of Distributed RAM in Spartan-6

35 Total Size of Distributed RAM in Artix-7

36 MLUT as a 32-bit Shift Register (SRL32)

ECE 448 – FPGA and ASIC Design with VHDL 37 Input/Output Blocks (IOBs)

ECE 448 – FPGA and ASIC Design with VHDL George Mason University Basic I/O Block Structure

Three-State D Q EC FF Enable Three-State Clock SR Control Set/Reset

Output D Q FF Enable EC Output Path SR

Direct Input FF Enable Input Path Registered Q D Input EC SR

ECE 448 – FPGA and ASIC Design with VHDL 39 IOB Functionality

• IOB provides interface between the package pins and CLBs • Each IOB can work as uni- or bi-directional I/O • Outputs can be forced into High Impedance • Inputs and outputs can be registered • advised for high-performance I/O • Inputs can be delayed

ECE 448 – FPGA and ASIC Design with VHDL 40 Family Attributes

ECE 448 – FPGA and ASIC Design with VHDL George Mason University Spartan-6 FPGA Family

ECE 448 – FPGA and ASIC Design with VHDL 42 Artix-7 FPGA Family

ECE 448 – FPGA and ASIC Design with VHDL 43 FPGA device present on the Digilent Nexys 3 board

XC6SLX16-CSG324C

Size Spartan-6 324 pins family Logic Package type Optimized (Ball Chip-Scale) Commercial temperature range 0° C – 85° C

ECE 448 – FPGA and ASIC Design with VHDL 44 FPGA device present on the Digilent Nexys 4 DDR board

XC7A100T-1CSG324C

Speed Grade Size Artix-7 324 pins family Package type (Ball Chip-Scale) Commercial temperature range 0°C – 85° C

ECE 448 – FPGA and ASIC Design with VHDL 45