SpaceCubeX: A Path Towards Hybrid On-Board Processing Architectures

Mahew French and Andrew Schmidt – USC/ ISI Thomas Flatley – GSFC Carlos Villalpando – JPL June 23, 2015 Movaon: NASA Earth Science Missions

• Instruments produce essenal data to help sciensts answer crical 21st century quesons - Global climate change, air quality, ocean health, ecosystem dynamics, etc… • On-board processing ~100-1,000x than previous missions (compression, storage, downlink) - Current/near-term data at rates >108 to 1011 bits/second • Adding new capabilies such as low-latency data products for extreme event warnings • Missions specifying instruments with significantly increased: - Temporal, spaal, and frequency resoluons à to global, connuous observaons • Meeng inter-mission reusability goals

ACE GEO-CAPE 3D-Winds Hybrid architecture is a key cross-cung technology directly applicable to missions recommended in the Decadal Survey ASCENDS HyspIRI PACE

ICESat II LIST PATH

2 SpaceCubeX Project

• Develop high performance on-board compung capability for flight missions: - Leverage heterogeneous processor types (COTS à Rad-Hard) - Incorporate industry experience with commercial device specializaon - Improve computaon/energy efficiency - Support persistent, long-term mission operaons - Provide potenal infusion into (P)ACE, HyspIRI, GEO-CAPE, ICESat-2… • Address key characteriscs to support mission design: - Size, weight, area, power - Mission capabilies, cost, risk - Risks of supply chain disrupon - Benchmark compilaon for robust characterizaon - Commercial tools/compilers interoperability

3 SpaceCube Family

4 SpaceCube Next?

Mul-. • Mul-core processors more easily provide: Core' Memory' IF# IF# – General OS support

IF# IF# IF#

– Sensor' High-level funcons DSP' FPGA' – Coarse grained applicaon parallelism

• Co-processors then provide: IF# Mul$% Mul$% IF# IF# IF# IF# IF# Core* Memory* IF# Core*

– Customized acceleraon IF# IF# IF#

IF# IF# IF# – High throughput IF# FPGA* IF# Memory* IF# FPGA* IF#

IF# IF# IF# – Fine-grained data parallelism IF# IF# Sensor* Sensor* • Sparked quesons: – What devices to use? Mul-. – How to connect the devices? Core' IF# IF# Memory'

IF# – How to program the system? IF# IF# IF# IF# – (and many more…) Sensor' IF# FPGA' IF# IF# DSP'

5 Hybrid Architecture Device Candidates

Category Candidates Mul-core Boeing Maestro, Tilera Tile64, Aeroflex LEON4, ... FPGA Xilinx Virtex7, Altera StraxV, Microsemi, Achronix S22i DSP BAE RADSPEED, ClearSpeed CSX700, TI 320C6701 ... Memory Atmel M65609E, Honeywell HXSR06432, ... Interconnects PCIe (Gen2/3), XAUI, RapidIO, SpaceWire ... Topologies Bus, Mesh, Ring, Crossbar, Buerfly ... Sensors I/O RS-422, Ethernet, SpaceWire Direct I/O, I2C ...

6 Tradional Development Process

Tradi&onal*Hardware*Development:* Benchmarks' Manual'' Topology'' Hardware'' Specifica.ons' Component'' &'Netlist'' Performance'' Implementa.on' Analysis' Crea.on' Results'

SpaceCubeX*Heterogeneous*Hardware*Development:*

While number of processors available to aerospace industry Specifica.ons' is tractable, number of combinaons of these elements and number of interconnect topology permutaons makes this Applica.ons'' Compila.on'Environment' process difficult and error prone for a human to do manually. &'Benchmarks' Designer' Evolvable'Testbed' Inputs' Flight'Hardware' Architecture'' Performance'' Genera.on' Engineering'Hardware' Results' TRL* Hardware'Emula.on' 7 Design'Explora.on'' Simula.on' Feedback'Loop' SpaceCubeX Approach

• Develop avionics architecture and generator suite: – Candidate device analysis – Evaluate with benchmark applicaons • Profile architectures in simulaon environment and select leading candidates for emulaon testbed • Implement architecture with selected hardware in emulaon testbed • Evaluate implementaon • Assess results and lessons learned

8 SpaceCubeX Development Process

• Updated to support hybrid architecture with focused design space exploraon • Ulize generaon and analysis tools to eliminate manual fit analysis Tradi&onal*Hardware*Development:* – Incorporate micro & complex benchmarks throughout testbed evaluaon process Benchmarks' Manual'' Topology'' • Common infrastructure for code reuse (simulaon Hardware''à flight hardware) Specifica.ons' Component'' &'Netlist'' Performance'' Implementa.on' – Explore and compare several permutaons in rapid succession Analysis' Crea.on' Results'

SpaceCubeX*Heterogeneous*Hardware*Development:*

Specifica.ons'

Applica.ons'' Compila.on'Environment' &'Benchmarks' Designer' Evolvable'Testbed' Inputs' Flight'Hardware' Architecture'' Performance'' Genera.on' Engineering'Hardware' Results' TRL* Hardware'Emula.on'

Design'Explora.on'' Simula.on' Feedback'Loop'

9 Simulaon Testbed

User*Selec'on** Benchmarks*Suite* • Microkernels' • Applica:ons'

Simula'on*Environment:* ArchGen* Compile*&** • Processor' Mul'Gcore* FPGA* DSP* • Accelerator' Par''on* Sim*IF* Sim*IF* Sim*IF* Board' C* • Topology' Model' O* • Interconnects' N* Sim*IF* Sim*IF* (xml)' T* Simula'on* • Interfaces' Memory* I/O* • Memory' R* Interface* Simula'on** O* Translator* • Sensor' L* interfaces' Generator* Sim*IF* Sim*IF* • I/O' Sensor* Peripherals*

MONITOR*

Report* Component' Performance' @Power' Database' Models' @Area' @Radia:on' @Performance'

SpaceCubeX extends tradional simulaon to incorporate enre hybrid system

10 Emulaon Testbed

Benchmarks)Suite) • Microkernels+ • Applica/ons+ • System+

Emula&on)Environment:)

Compile)&)) Mul&Fcore)Board) FPGA)Board) DSP)Board) Par&&on) Emu)IF) Emu)IF) Emu)IF) Board+ C) Model+ O) (xml)+ N) Emu)IF) Emu)IF) T) Interface) R) Memory) I/O) Emula&on) O) Emulator) Generator) L) Emu)IF) Emu)IF) Sensor)Emulator) Peripherals)

MONITOR) Performance+ Models+ Report) 9Power+ 9Area+ 9Radia/on+ 9Performance+

SpaceCubeX emphasizes end-to-end board level architecture emulaon

11 SpaceCubeX - Redsharc

REconfigurable Data-stream Hardware/Soware ARChitecture: • Provides rapid construcon of Mul-System-on-Chip plaorms (HW & SW) • Enables design space exploraon of heterogeneous resources (Dev. Spirals) • System infrastructure supplied as IP, raising focus to algorithm development • Combines situaonal awareness with high performance processing – On-chip run-me control – Dynamic resource management – System and kernel-level performance tuning • Redsharc is not a high-level synthesis tool – Supports use of HLS tools use to create HW cores – Fills gaps in HLS tools: Integraon, communicaon, and run-me management

Redsharc Philosophy: Interoperate and leverage current and emerging devices, tools, and technology to make developers more producve

12 Redsharc Development Spectrum

Accelerang Development Maturity

Host PC: SW FPGA: SW FPGA: HW FPGA: HW FPGA: HW

On-Chip Kernel System System Towards Full-System Integraon Simulaon Simulaon Run-me

Redsharc infrastructure supports rapid tesng across a variety of development environments to allow users to leverage preferred design and debugging tools such as Eclipse, GDB, ModelSim, and ChipScope.

13 Redsharc APIs

• Applicaon Programming Interfaces: – Soware Kernel Interface – Hardware Kernel Interface – Dataflow Graph (DFG) – System – Scheduling • Run-me Execuon – Control Kernel Operaon

End-user leverages higher levels of abstracon to implement applicaon on heterogeneous resources

14 Redsharc Build Environment

DSP M.C.

Redsharc Generate flow constructs finished system from user provided design files

15 Soware Compilaon Flow

Applica'ons+&+Benchmarks+

Task+ Task+ Task+

Task+

Manual+Task+Par''oning+ SoLware/Hardware+ CoBDesign+Library:! Hw+ Sw+ Sw+ Task+ Task+ Task+ ,!Communica4ons! ,!Interfaces! Hw+ Task+ ,!Protocols! ,!Run,4me!controls! Redsharc+Libraries+

Mul'Bcore+ Accelerator+ FPGA++ FPGA+Resource++ Library:+ Compiler+ Compiler+ Synthesis+ B!Interfaces! B!Interconnects! , Accelerator!! Cores! Bitstream+ Bitstream+ Executable+ Executable+ Executable+ Executable+ Core+0+ Core+1+ …! Core+n" DSP" FPGA+0" …! FPGA+n"

Evolvable+Testbed+

16 List of Benchmarks

Benchmark Description Micro Benchmarks Kernels to benchmark architecture subcomponents and measure system viability. ALHAT Analyze landing sites; Image processing (interpolation, correlation, kalman filter), Autonomous Landing and Hazard Avoidance and Detection System 4 sensors, task/data parallelism. ASPEN Artificial intelligence, multi-threaded, low level scheduler to satisfy constrained Automated Scheduling and Planning Environment mission goals. ROCKSTER Autonomous spacecraft tasking, geological feature identification, analysis, and Rock Segmentation Through Edge Regrouping data handling. Global, continuous real-time ocean radiometer for carbon assessment enabling ACE Mission Scenario research and coordinated activities based on live ocean color data; multi-spectral Aerosol-Cloud-Ecosystem image, data parallel processing Synthetic aperture radar and multi-beam lidar instruments produce voluminous raw data (future data rate concepts >1012 bits/second); benchmarks perform Radar/Lidar Mission Scenario terrain, vegetation and/or glacial ice mapping; high data rate processing, data parallelism. Hyper-spectral Earth science event detection algorithms (fire, flood, coastal HyspIRI Mission Scenario spills); Autonomously reconfigures for Visible to Short Wavelength Infrared data for real-time mapping and transmission.

17 Result Metrics

Parameter Units Power Watts Estimated board size cm2 Estimated board weight kg Processing performance Instructions or Operations per second Input Output Bandwidth Bits per second Radiation Tolerance Total Ionizing Dose and Single Event Upset rate Cost $

Provide designers and sciensts more feedback earlier in development process

18 Example Results

Performance unit(Area, Architecture1 Power, Processing…) Architecture2

Architecture3

SingleCPU baseline 1 1 1 N N 1 N N App App App App App App App App Sequential Streaming Server Bitlevel

19 Geng “On-Board”

• We want to learn from the community – Understand applicaons and instruments – Advice on applicaon/algorithm implementaons – Suggesons on devices to consider • How is the current technology performing? • Hard restricons on data precision? • Applicaon’s demand for radiaon tolerance?

20 Summary

SpaceCubeX aims to: • Alleviate computaon limitaons for on-board processing • Enable selecon of SWAP efficient processing architecture: – Impact on mission capabilies, cost, and risk • Reduce risk due to supply chain disrupon • Require minimal extensions to integrate new devices • Support persistent, long-term mission operaons • Provide potenal infusion into many missions: – (P)ACE, HyspIRI, GEO-CAPE, ICESat-2…

The SpaceCubeX Project is a structured approach to assess and develop hybrid architectures, fundamentally changing avionics processing architecture development process.

21 QUESTIONS

22 BACKUP SLIDES

23 Project Milestones

• Project start 05/15 • Complete inial scenario benchmarks 11/15 • Inial architecture 12/15 • Final architecture 03/16 • Final benchmark package 04/16 • Inial emulaon testbed 12/16 • Final emulaon testbed 03/17 • Benchmark demonstraon 04/17

24 Development Abstracons

Hardware Kernel Interface Soware Kernel Interface

Data accesses are abstracted from the kernel implementaon

25 TRL Assessment

Category Component Initial 6 Mos 12 Mos 18 Mos Final Component Selection 3 3 4 4 5 Hardware Interconnect Topology 3 3 4 4 5 Architecture Control Software 3 3 4 4 5 Hardware Architecture Subtotal 3 3 4 4 5 Programming Model 4 5 5 5 5 Total 3 3 4 4 5

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