Trends in SOI Technology: Hot and Green

Journal of the Korean Physical Society, Vol. 58, No. 5, May 2011, pp. 1461∼1467

Sorin Cristoloveanu∗ Institute of Microelectronics, Electromagnetism and Photonics (UMR 5130), Grenoble Institute of Technology, IMEP-LAHC, BP 257, 38016 Grenoble Cedex 1, France

(Received 27 October 2010)

The current status of Silicon-On-Insulator (SOI) technology and its near-future trends are re- viewed. SOI is the subject of hot strategic debate with huge economic implications. SOI oﬀers ample room for scaling, performance improvement, and innovations. SOI memories and logic circuits also provide substantial power savings for a green world. Several options and technology boosters for SOI will be discussed. They can infuse further gains in performance and miniaturization while enriching the circuits’ functionality. Among several emerging applications, we address the context of capacitorless single-transistor Dynamic Random Access Memories (1T-DRAMs) and focus on two novel approaches.

PACS numbers: 85.30.Tv, 85.30.De Keywords: SOI, CMOS, Microelectronics, Nanoelectronics, Strain, DRAM, 1T-DRAM DOI: 10.3938/jkps.58.1461

I. INTRODUCTION mance or for both. We will show that there is wide space for further improvements enabling a massive increase of the SOI segment in the global market for integrated cir- Silicon-On-Insulator (SOI) technology is gaining mo- cuits. mentum as bulk CMOS (Complementary Metal-Oxide- Semiconductor) is confronted with scaling, power and performance challenges. The topic is hot, being situated at the crossing of two Moore Avenues: one is going down II. STATUS AND PROSPECTS and the other laterally. The milestones of the descend- ing route are measurable in nanometers for the transistor 1. SOI Context feature size and in billions for the number of transistors in a System-on-Chip. SOI is certainly able to take us SOI technology is penetrating the market place. Many far beyond the current status. This is so because the SOI chips are present in our servers, laptops, cars, device miniaturization is more efficient and comfortable watches, play stations, lighting systems, etc. The fastest if transistors are fabricated ‘on Insulator.’ SOI circuits CPUs are on SOI. Out of the top 10 supercomputers, 9 are denser, smaller, and faster. are ‘SOI-made.’ SOI CMOS is indeed unchallenged when The lateral avenue departs from the traditional forms considering the combination of ultimate scalability, high of scaling. This route is imposed by the need for en- speed and low power. riched circuit functionality. SOI is amenable to the It is predicted that the Mobile Internet (including lap- co-integration of heterogeneous technologies and multi- tops, cell and smart phones, mobile and home enter- functional devices. Skilled circuit design can take advan- tainment, car equipments, wireless appliances, etc.) will tage of multiple gates, independently biased, to reduce drive the microelectronic market with more than 10 bil- the transistor count for a given logic function or to elab- lion devices sold in 2020 [1]. While desktop production orate new schemes of operation. will hardly increase, the availability of portable devices On the other hand, SOI technology is green. SOI cir- will experience an exponential growth. Users are de- cuits naturally offer power savings without fundamen- manding faster Internet, free wireless connectivity, uni- tally disrupting the current CMOS process and design versal multi-purpose devices, no battery issues, and un- infrastructure. A comparison of state-of-the-art bulk and limited memory. In this context, SOI is offering not only SOI circuits provides unquestionable evidence. In this superior speed and lower voltage/power operation but paper, examples will be given showing that SOI circuits also reduced variability and junction leakage. can be tuned for power savings or for enhanced perfor-

∗E-mail: [email protected]; Fax: +33-456-52-95-01 -1461- -1462- Journal of the Korean Physical Society, Vol. 58, No. 5, May 2011

2. Hot SOI

Fully-depleted SOI Metal-Oxide-Semiconductor Field- Effect Transistors (MOSFETs) exhibit rather ideal subthreshold swing and are more immune to short channel effects than their bulk-Si counterparts [2]. These benefits translate into performance gain. A comparison of SOI and bulk circuits of various flavors has repeatedly demonstrated the assets of SOI technology. Operated at same power, SOI circuits are 20 - 30% faster, which corresponds to the performance expected from the ‘next’ technology node. Fig. 1. TEM image of a fully-depleted SOI MOSFET Switching from bulk to SOI technology and design li- featuring an ultrathin strained Si film, a thin BOX, a kigh- braries is viewed as an impediment. However, cell li- k/metal gate stack, and raised and silicided source and drain. braries can be ported from bulk to partially-depleted SOI. Fully-depleted SOI requires more dedicated design efforts, but the reward consists of circuits on smaller real the threshold voltage is lowered, and leakage is gov- estate, mixed n-MOS and p-MOS within the same island, erned by the subthreshold current. SOI enables further suppressed body contacts, improved scalability, etc. A threshold voltage (VT ) reduction; hence, the static power good sense strategy is to re-use as much of bulk Intellec- can be increased. However, several solutions can be tual Property (IP) as possible. combined to control leakage: process options, multi-VT Short-channel effects in fully-depleted SOI are re- CMOS, power management, and process-compensation strained not by increasing the doping level, as in bulk design techniques [1,3]. or partially-depleted SOI, but by reducing the thickness of the Si film and buried oxide (BOX). Film thinning at- tenuates the junction capacitance, leakage current, and single-event upsets [2]. Low doping relaxes the problems III. SOI CMOS BOOSTERS of variability, mobility degradation, band-to-band tunneling (GIDL), and junction leakage. There are two knobs for tuning the performance, functionality, and size of SOI MOSFETs: electrostatic behavior and carrier transport. Short-channel effects are 3. Green SOI governed by the gate-induced electrostatic properties of the device. Gate control is reinforced if the transistor Device scaling leads to power inflation: there are more body is very thin [2]. This is why ‘on insulator’ struc- devices, more activity (higher frequency), and more leak- tures are unavoidable. Since ultrathin SOI MOSFETs age per mm2. More power increases the chip temperature (Fig. 1) are naturally fully depleted, the preferred option and reduces the battery lifetime. Power saving means is to keep the film undoped. A very thin buried oxide ‘green’. Circuits operated at the same frequency require (BOX) and a ground plane underneath the BOX are ef- significantly less power if fabricated on SOI. The advan- fective solutions for scaling; they reduce the penetration tage of SOI for Low Operating Power (LOP) results from of fringing fields from the source and the drain into the reductions in the parasitic capacitances and the operat- body via the substrate and BOX [2]. Ideal body control ing voltage (VDD) which can be lowered in SOI by 10 - is actually achieved using multiple gates or a surround- 20%. ing gate. These aspects were well documented recently Recent reports from ARM company address the case and will not be addressed here. We focus on the im- of 45-nm processors on SOI and bulk, tuned for low- provements in the transport properties by using various power (100 mW) and a 500-MHz core frequency; the SOI boosters. The discussion is based on experimental data variant features 38% saving in total power at 500 MHz collected in advanced SOI MOSFETs. due to its much lower dynamic power (50%) and VDD scaling [3]. Operating the SOI processor at 600 MHz still maintains a 28% power saving as compared to the bulk 1. Series Resistance Control processor operated at 500 MHz. The capability to operate at Low Standby Power (LSTP) is related to the leakage current. When the leak- Reducing the series resistance is the starting point for age is dominated by the junctions (i.e., circuits with rela- device optimization, especially in ultrathin SOI where tively high threshold voltage), SOI is the perfect solution. the sheet resistance of the source and the drain is intrin- Ultralow-power chips (for watch operation, for example) sically large and the implantation process is less effective. are ‘SOI-inside.’ In order to enhance the circuit speed, The solution is to form ‘raised’ source and drain termi- Trends in SOI Technology: Hot and Green – Sorin Cristoloveanu -1463-

the mobility. A single SOI transistor is an ideal tool for in-situ comparison of the transport properties at the high-k and SiO2 interfaces. Figure 2(b) shows that the carrier mobility is much higher at the back channel (Si- SiO2 interface) compared to the front channel (Si-high-k interface). It is clear that yet another scattering mechanism, inher- ent to the high-k interface, comes into play. Our results tend to confirm the prominent role of Coulomb scattering induced by remote charges located in the high-k dielectric or at its interface with the pedestal oxide [4]. Note that the back-channel mobility increases at low temperatures, even in short transistors, being only marginally affected by the neutral defects. The localiza- tion of the neutral defects at the front interface suggests that the film-BOX interface may accommodate their re- combination.

3. Metal Gates

Mid-gap metal gates suppress the poly-depletion effect and, in FD SOI MOSFETs, allow simultaneously the ad- justment of threshold voltage of the N- and P-channels. Gate optimization is conducted in terms of materials, Fig. 2. Low-field mobility versus temperature in SOI MOS- thickness, and deposition techniques. The various gate FETs. (a) Comparison of front-channel mobility in long and stacks (TiN or TaN over HfZrO2, HfSiON or HfO2) do short devices. (b) Comparison between the front channel not alter the short-channel (40 nm) electrostatic prop- (Si/high-k interface) and the back channel (Si/SiO2 inter- erties: Drain-Induced Barrier Lowering (DIBL) below face). 100 mV/V and subthreshold swing of 90 mV/decade (60 mV/decade in long channels) [6]. The thinning of the metal gate from 10 nm down to 3 nals (Fig. 1) by using single- or double-step Selective nm results in a 30% electron mobility improvement and Epitaxial Regrowth, spike annealing, and silicidation [4]. a 100-mV threshold voltage shift. There is no marked difference between TiN and TaN gates or between ALD and PVD deposition methods. Gate thickness control 2. High-k Dielectrics can, therefore, serve for threshold voltage tuning.

High-k dielectrics improve the gate capacitance and the gate leakage current at the expense of a more defec- 4. Strain tive interface with silicon [5]. A detailed investigation of the carrier mobility behavior is summarized in Fig. 2. Strain engineering has multiple facets. Biaxial strain, In long-channel transistors, the electron mobility in- beneficial for both N- and P-channel MOSFETs, is im- creases (µ ∼ T−0.7) at low temperature, being domi- plemented with the Smart-Cut process [2]. The strained nated by acoustic phonon scattering (µ ∼ T−1) with a Si film is (i) grown on a relaxed SiGe layer, (ii) partially contribution from Coulomb scattering (µ ∼ T). In short oxidized to form the BOX, and (iii) transferred onto a MOSFETs, the mobility µ(T) curve becomes nearly flat, support Si wafer. The BOX maintains the strain after independent of temperature, pointing to an additional the SiGe template layer is removed. The thinner the Si scattering mechanism that is more effective in shorter film, the higher the stress level. Some of the wafer-level channels. This mobility component, extracted with the strain is lost during the processing of small-area MOS- Matthiessen rule, is attributed to the presence of neutral FET islands. defects concentrated near the source/drain junctions. Uniaxial strain, compressive for holes and tensile for ‘Edge’ defects are generated during the source/drain im- electrons, is introduced locally at the transistor level. plantation or the gate stack processing [4]. A long chan- Longitudinal strain is achieved by source-drain engineer- nel is free from the influence of localized defects, but ing: SiGe and SiC terminals are, respectively, used for in short MOSFETs, the defective ‘edge’ regions overlap, P- and N-MOSFETs [7]. Transversal strain can be gen- leading to an increased density of defects, which degrades erated, essentially in narrow devices, by using sidewall -1464- Journal of the Korean Physical Society, Vol. 58, No. 5, May 2011

distributed along the channel. The hole mobility decrease at channel lengths below 80-100 nm points out an adversely competing mechanism to stress, presumably neutral defect scattering [6]. An interesting aspect in Fig. 3(a) is that the mobility gain is even more pronounced at the back channel. We infer that the strain is transmitted from the CESL through the whole film and may increase in the vertical direction from the top interface to the bottom interface. Figure 3(b) shows that, in long channels, the mobility increases at temperatures from 300 K to 77 K as a consequence of attenuated phonon scattering. At room temperature, the hole mobility is much higher in short devices due to the strain effect. At lower temperatures, the mobility tends to saturate, and the benefit of strain disappears. The mobility dependence on temperature and gate length reveals a competition between several mechanisms in short devices. The distributions of strain, neutral defects and scattering rate are highly inhomogeneous along the channel. These profiles do not affect the performance of long MOSFETs, but become efficient in short transistors. We note that the back-channel mobility increases at low temperature in both short and long channels, which implies less impact from neutral defects. A recent model accounts for the stress tensor and Fig. 3. Low-field hole mobility in compressively-strained its profile under the gate from the source to the drain SOI MOSFETs versus (a) channel length and (b) tempera- [6]. Several contributions are included: (i) phonon ture. scattering, (ii) neutral defect scattering, and (iii) remote Coulomb scattering due to lateral depletion in the source/drain regions, next to the metallurgical junction. isolation techniques (STI, SiGe, etc.). We focus on the Combined with the Matthiessen rule, these effects pro- Contact Etch Stop Layer (CESL), which transfers ver- vide a ‘local’ mobility profile µ(x) along the channel. tical strain from the gate stack and capping layers into The ‘global’ mobility is obtained by integration of 1/µ(x) the body. from the source to the drain. This model successfully The local strain depends on the device’s geometry and reproduces the experimental variation of hole mobility dimensions. In a large-area MOSFET, regions with com- with both channel length (Fig. 3(a)) and temperature pressive and tensile strain can coexist whereas in nano- (Fig. 3(b)). We conclude that the compressive CESL size transistors, the strain tends to be homogeneous. The strain boosts the hole mobility in short devices whereas strain effect can be modulated according to the CESL neutral defects and remote Coulomb centers jeopardize composition and location (on top of the gate, on gate the mobility gain in very short transistors. An exciting edges, on spacers, on extensions, etc.) [8]. The strain is trend is to combine various types of stressors (vertical, not uniform along the vertical direction and increases for lateral and longitudinal) and crystal orientations in order ultrathin bodies and thicker CESL. to achieve ideal transport properties. Systematic measurements indicate that while the strain does not modify the electrostatic behavior of short-channel devices, the transport properties and ON- current are strongly impacted. Figure 3(a) illustrates the 5. Novel SOI Materials effect of compressive strain on the hole mobility, which reaches an outstanding gain of 80% in 100-nm-long P- What about breaking the happy marriage of Si and MOSFETs. SiO2 by introducing alternative materials? Any combi- The mobility variation in Fig. 3(a) reveals strain lo- nation of a semiconductor film and a buried dielectric, calization at the channel extremities. Detailed mechani- still part of the Semiconductor on Insulator SOI family, cal simulations confirm the presence of ‘stressed pockets’ can be achieved by bonding and Smart-Cut processes [2]. within 50 nm from the corner between the source/drain Germanium, Silicon Germanium and compound semi- region and the offset spacer [9]. The central region of conductors (GaN, AsGa, etc.) are envisioned for superior a long channel (∼1 µm) remains unstressed. In 30- to transport properties and optoelectronic functionalities. 100-nm-long devices, the strain is strong and uniformly Direct wafer bonding is also capable of mating circuits Trends in SOI Technology: Hot and Green – Sorin Cristoloveanu -1465- pre-processed on a variety of substrates, eventually leading to 3D stacks. Germanium on Insulator (GeOI) substrates are fabricated by using Ge condensation [10], which exploits the selective oxidation of a SiGe layer grown on SOI. During oxidation, only Si atoms are consumed whereas the dif- fusion of Ge atoms is blocked by the BOX barrier. This process results in a thinner Ge-enriched film; the initial SOI layer can be totally converted into a 10-nm-thick GeOI film. The layer thickness can be completed via Ge epitaxy. Our experimental results show that the hole mobility increases with increasing Ge content, reaching excellent Fig. 4. (Color online) MSDRAM cell. (a) Measured drain values far beyond Si capabilities (200 cm2/Vs in a 10- current versus decreasing and increasing front-gate bias in a nm film, 400 cm2/Vs in 50- to 100-nm films, and even long SOI MOSFET with a thick BOX (30-V back-gate bias 700 cm2/Vs for strained GeOI) [11]. This improvement and 0.1-V drain bias). (b) Simulated drain current versus for holes is balanced by a clear decrease in the electron time during the ‘0’ and the ‘1’ states reading in a 50-nm-long mobility, probably due to a peculiar distribution of traps DG-MSDRAM: 0.25-V back-gate bias, 0.1-V drain bias, and 40-nm-thick film. The retention time is 14 s for I1/I0 = 10 in the band gap [12]. An attractive solution is the co- ◦ integration of N-channel SOI and P-channel GeOI tran- and 30 C. sistors within the same chip. Local Ge condensation in selected islands enables the fabrication of SOI-GeOI hy- generated by (i) impact ionization, (ii) bipolar junction brid substrates and related devices [13]. transistor effect, (iii) band-to-band tunneling, or (iv) A parallel avenue is to change the BOX material to gate tunneling current [16]. State ‘0’ features a lower solve the problem of transistor self-heating. The heat current as a result of the removal of majority carriers dissipation in the silicon substrate is blocked by the poor from the body. The hole extraction for 0-state program- thermal conductivity of SiO2. Buried alumina, Si or ming is achieved by forward biasing the drain-body or Al nitrides, and other dielectrics have been positively the source-body junction, either by briefly reversing the evaluated as possible replacements [14]. Silicon on Di- drain bias or by capacitive coupling (a short positive amond (SOD) wafers were recently demonstrated, and pulse on the gate, higher than the flatband voltage, in- SOD MOSFETs exhibit excellent characteristics [15]. creases up the body potential). An interesting concept is to promote the BOX as an For compatibility with scaling trends, fully-depleted active layer. For example, a nitride BOX can induce 1T-DRAMs are preferable. The floating-body effect is strain in the film whereas a transparent BOX (quartz, emulated by biasing the substrate (back gate); a nega- glass, diamond) opens the door to photonic applica- tive voltage maintains the generated holes in the body. tions. A buried oxide-nitride-oxyde (ONO) stack is use- The substrate bias is reduced by using an ultrathin BOX ful as a reservoir of non-volatile charges, enabling a new [17, 18] or a double-gate MOSFET, with a planar or a paradigm of a ‘unified’ SOI memory. The idea is to use FinFET/SOI configuration. (Bulk FinFETs can be dis- a single SOI transistor for both volatile and non-volatile carded because of transient radiation effects, which gen- functions. This brings us to the next section. erate numerous electron-hole pairs in the substrate, leading to bit upsets (SEU) [19]). The top gate controls the programming phase, as well as the reading, of the elec- IV. 1T-DRAM tron current. States ‘1’ and ‘0’ are discriminated by the difference in the front-channel threshold voltages (i.e., 1. Basic Principles drain currents) between the cases where the back channel is accumulated or deep depleted [17,18]. This basic 1T-DRAM approach suffers from an insufficient memory The scaling of conventional 1T-1C (1 Transistor + 1 window, which does not allow safe separation of the two Capacitor) DRAM cells will soon hit a wall. An attrac- threshold voltage distributions. We will now discuss two tive solution is the capacitor-less single-transistor 1T- novel, alternative concepts. DRAM on SOI. These cells have the advantage of a floating-body and coupling effects that are unique features of SOI MOSFETs. The storage capacitor is re- placed by the body of the transistor, where the charge is 2. MSDRAM generated and, thanks to the SOI isolation, conserved. State ‘1’ reflects an excess of majority carriers in the The Meta-Stable DRAM (MSDRAM) cell is based on body, which increases the potential and the drain cur- the Meta-Stable Dip (MSD) hysteresis effect [20] illus- rent. This extra charge (holes in n-MOSFETs) can be trated in Fig. 4(a). Note the very wide memory win- -1466- Journal of the Korean Physical Society, Vol. 58, No. 5, May 2011

fied memory cell, which combines non-volatile memory and DRAM functionalities in a single transistor. Ac- cording to the application, the cell can be operated as a MSDRAM (temporary storage of holes in the floating body) or as a flash memory (permanent electron charging in the ONO via Fowler-Nordheim or hot-electron injec- Fig. 5. (Color online) A-RAM cell: (a) schematics; (b) ‘0’ tion) [24]. state: the two semibodies are fully depleted and the drain current is zero; (c) ‘1’ state: holes are stored in the upper semibody and enable electrons in the lower semibody: the 3. A-RAM drain current is high. All 1T-DRAMs require the presence, within the same body, of holes (stored charge) and electrons (reading cur- dow and the current ratio I1/I0, which exceeds 6 orders rent). The necessary coexistence of holes and electrons of magnitude. The back gate is biased in the moder- actually stands as the main limiting factor for cell minia- ate inversion regime. State ‘0’ is programmed by simply turization, which implies film thinning. In MOSFETs switching the front gate from 0 V to the reading voltage: with ultrathin bodies (∼10 nm), the super-coupling ef- -3 V (Fig. 4(a)) or -1.5 V (Fig. 4(b)). Since no holes fect makes it impossible to maintain an inversion chan- are immediately available to complete the front accumu- nel facing an accumulation channel [25]; only one type lation channel, the body potential drops via capacitive of carriers can survive. coupling, and the back channel is suppressed: I0 ≈ 0. The Advanced Random Access Memory (A-RAM) cell This state requires refreshing because parasitic carrier has been conceived to suppress the super-coupling effect generation tends to supply the missing holes at the front [25] by physically isolating the holes and the electrons channel. [26,27]. The transistor body is divided in two regions by For state ‘1’ programming, the front gate is pulsed using an intermediate dielectric (MOX). The upper semi- for a few nanoseconds to a more negative bias (VG = body serves for majority carrier storage, and the lower -6 V in Fig. 4(a) [20] or VG = -2 V and VD = +2 V semibody for sensing the electron current (Fig. 5(a)). in Fig. 4(b) [21]). The electric field in the gate-to-drain The A-RAM architecture enables the electron and the overlap region is large enough to generate holes by band- hole layers to face each other, on each side of the dielec- to-band tunnelling. When the front-gate voltage returns tric layer MOX, even in ultrathin SOI films where the to the reading value (-3 V in Fig. 4(a)), the number of Si and MOX layers are 3- to 4-nm thick. If no holes holes is sufficient to restore the accumulation channel. are stored, the electron current I0 in the lower semibody The device is at equilibrium which means that the back is zero (’0’ state, Fig. 5(b)). To write ‘1’ (Fig. 5(c)), inversion channel is no longer depleted and the current excess holes are generated by impact ionization or band- I1 is high. This state is stable. Cell reading requires a to-band tunneling in the upper semibody. As a result, small drain bias. the semibody potential increases and initiates electro- The main MSDRAM advantages include [21] long re- static coupling. To summarize, the positive charge acts tention (seconds), low-power operation, fast program- to ‘attract’ an electron channel in the lower semibody, so ming, easy discrimination of state levels (‘0’ state yield- that a drain current I1 can be sensed. ing zero current), non-destructive read, wide memory The A-RAM is basically a single-gate cell, which can window, etc. Recent measurements confirm that the be further enriched with double-gate and FinFET con- MSD memory effect is maintained in small MOSFETs figurations. This concept has been validated so far by with gate areas below 0.1 µm2 [22]. Further optimiza- numerical simulations [26]. Beside its scalability, the A- tion of the device architecture aims at controlling the RAM features competitive programming and retention band-to-band tunnelling effect. It should be amplified time, low-power operation, comfortable memory window, for fast writing of the ‘1’ state and minimized for ‘0’ non-destructive read, and very simple waveforms on bit retention. These opposite constraints imply combining and word lines. Except during programming ‘1’, the gate various technology solutions: lower bandgap materials voltage is always negative (-1 V), and the drain voltage or high-low doping profiles for the source and the drain, is low (0 or 0.1 V). underlapped back gate, recessed junctions, thicker back- The A-RAM architecture is versatile with undoped gate oxide, etc. [23]. or P/P or P/N semibodies (the latter case implies A double-gate MSDRAM with an ONO stack as a depletion-mode operation) [27]. The cell is amenable to buried dielectric has been demonstrated [24]. A non- ‘unified’ memory operation by functionalizing the MOX volatile positive charge can be stored in the Si-nitride and/or the BOX with nanocrystals or ONO. The device layer in order to invert the back channel. The trapped can be fabricated by using epitaxial regrowth or by us- holes replace the back-gate action, so the MSDRAM vir- ing the Silicon-On-Nothing (SON) replacement method. tually becomes a single-gate device. Even more interest- The proof-of-concept still needs to be validated by device ing is the capability of this structure to operate as a uni- processing and measurements. Trends in SOI Technology: Hot and Green – Sorin Cristoloveanu -1467-

V. CONCLUSION [6] L. Pham-Nguyen, C. Fenouillet-Beranger, G. Ghibaudo, T. Skotnicki and S. Cristoloveanu, Solid-State Electron. 54, 123 (2010). ‘More than Moore’ and ‘Beyond CMOS’ strategies will [7] D. Chanemougame et al., VLSI Symp. Tech. Dig., 180 make available a variety of carbon nanotubes, graphene, (2005). spin and other innovative structures. We believe that [8] C. Gallon et al., Jpn. J. Appl. Phys. 45, 3058 (2006). beyond the ‘Beyond CMOS’ era, CMOS will remain the [9] F. Payet, F. Boeuf, C. Ortolland and T. Skotnicki, IEEE overwhelming technology in excellent shape. Twenty Trans. Electron Devices 55, 1050 (2008). years from now, our computers will still contain many [10] T. Tezuka, S. Nakaharai, Y. Moriyama, N. Sugiyama and MOS transistors made on silicon and its cousins (SOI, S. Takagi, VLSI Symp. Tech. Dig., 198 (2004). Ge, SiGe, GaN, etc.). [11] Q. T. Nguyen, J-F. Damlencourt, B. Vincent, L. Clave- The Mobile Internet will generate an astronomical de- lier, Y. Morand, P. Gentil and S. Cristoloveanu, Solid- mand for integrated circuits. Memory and low power will State Electron. 51, 1172 (2007). be the technology drivers. The superiority of SOI comes [12] W. Van Den Daele, E. Augendre, C. Le Royer, J.-F. Damlencourt, B. Grandchamps and S. Cristoloveanu, from the combined benefits in performance, scalability, Solid-State Electron. 54, 205 (2010). power savings and variability. SOI is hot and green as [13] C. Le Royer et al., in Proceedings EUROSOI 2010 the Korean ‘cheong-yang’ pepper. SOI is, therefore, fit (Grenoble, France, January 25-27, 2010), p. 21. to become a symbol of the Korean IC industry. [14] N. Bresson, S. Cristoloveanu, C. Mazuré,F. Letertre and H. Iwai, Solid-State Electron. 49, 1522 (2005). [15] J.-P. Mazellier et al., in Proceedings IEEE Int. SOI Conf. (Foster City, California, USA, October 5-8, 2009), p. 1. ACKNOWLEDGMENTS [16] M. Bawedin, S. Cristoloveanu, A. Hubert, K. H. Park and F. Martinez, Springer, in press (2011). Thanks for competent cooperation are due to very [17] T. Hamamoto et al., IEEE Trans. Electron Devices 54, many SOI colleagues, including Drs. M. Bawedin, N. Ro- 563 (2007). driguez, F. Gamiz, K.-H. Park, Y.-H. Bae, K.-I. Na, and [18] U. E. Avci, I. Ban, D. L. Kencke and P. L. D. Chang, in J.-H. Lee. Support from Kyungpook National Univer- Proceedings IEEE Int. SOI Conf. (New Paltz, New York, USA, October 6-9, 2009). sity (KNU) and World Class University (WCU) project [19] D. R. Ball, M. L. Alles, R. D. Schrimpf and S. is gratefully acknowledged. Cristoloveanu, in Proceedings IEEE Int. SOI Conf. (San Diego, USA, October 11-14, 2010. [20] M. Bawedin, S. Cristoloveanu, J-G. Yun and D. Flandre, REFERENCES Solid-State Electron. 49, 1547 (2005). [21] M. Bawedin, S. Cristoloveanu and D. Flandre, IEEE Electron Device Lett. 29, 795 (2008). [1] H. Mendez, in Proceedings EUROSOI 2010 (Grenoble, [22] A. Hubert, M. Bawedin, S. Cristoloveanu and T. Ernst, France, January 25-27, 2010), p. 11. Solid-State Electron. 53, 1280 (2009). [2] S. Cristoloveanu and G. K. Celler, Handbook of Semi- [23] M. Bawedin, S. Cristoloveanu, D. Flandre, C. Renaux conductor Manufacturing Technology, edited by Y. Nishi and A. Crahay, Patent WO2009087125 (A1), 2008. and R. Doering, 2nd ed. (CRC Press, London, 2007), [24] K.-H. Park, M. Bawedin, J.-H. Lee, Y.-H. Bae, K.-I. and references therein. Na and S. Cristoloveanu, Solid-State Electron., in press [3] R. Pottier, J. Tong, C. Hawkins, R. Kundu and J.-L. (2010). Pelloie, in Proceedings IEEE Int. SOI Conf. (Foster City, [25] S. Eminente, S. Cristoloveanu, R. Clerc, A. Ohata and California, USA, October 5-8, 2009). G. Ghibaudo, Solid-State Electron. 51, 239 (2007). [4] L. Pham-Nguyen, C. Fenouillet-Beranger, A. Vandooren, [26] N. Rodriguez, F. Gamiz and S. Cristoloveanu, IEEE T. Skotnicki, G. Ghibaudo and S. Cristoloveanu, IEEE Electron Device Lett. 31, 972 (2010). Electron Device Lett. 30, 1075 (2009). [27] S. Cristoloveanu, N. Rodriguez and F. Gamiz, Patent [5] G. Bersuker and C. S. Park et al., J. Appl. Phys. 100, PCT F2010/050716 (2009). 094108 (2006).