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Silicon-On-Insulator (SOI) Technology – Pushing the Limits of CMOS by Dr

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Silicon-On-Insulator (SOI) Technology – Pushing the Limits of CMOS by Dr Electronics Technical Silicon-on-insulator (SOI) technology – pushing the limits of CMOS by Dr. Jayson Koh, Frost and Sullivan Semiconductor devices are the basic building blocks of the electronics that lie at the core of most modern-day devices and products. To support technological advancement, transistors the depletion width. However, the implants can from the bulk. This oxide separation enables are put back on drawing boards every two to three cause severe short channel effects where an transistors to be packed closer and allows a years to push their speeds higher and squeeze abnormal increase in threshold voltage (Vt) can variety of active and passive elements to be extra performance out of them. For the past occur as gate length shrinks. The “kink” in Vt versus included on the same integrated circuit (IC). four decades, the semiconductor industry has gate length trends is not desirable for the device SOI wafers can have thick and thin top layer film. been driven by the increasing requirements from as the large V drift would cause unacceptable t For CMOS applications, thin film SOI is used as the new design rules. For each new technology drain or drive current fluctuations. thick film is difficult to be depleted. node, transistor feature size is reduced by about These issues led researchers to ponder on the 30%, while the transistor density and speed are Thick-film SOI wafers are manufactured by possibility of depleting the entire silicon film, which doubled. traditional wafer bonding and etched back would minimise the loss of voltage and current by chemical and mechanical polishing (CMP) However, as we enter the sub-100-nanometer leakage paths. processes. Typical applications include micro- era, keeping up with scalability demands requires However, in order to do so, the silicon film must electro-mechanical systems (MEMS) applications, more than slight modifications to the transistor be made thin enough (less than 400 Å) so that optoelectronic, high voltage electronics design and manufacturing process. Researchers the channel can be fully depleted even without applications, and/or combinations of these. are facing the difficulty of continuously shrinking any applied gate voltage. Calculations have transistor size, lowering active and off-state power Thin-film SOI wafers with top silicon film of less consumption, and increasing chip performance. than 1 micrometer are manufactured by several A major problem began to emerge as the leakage patented processes. The earliest method was current increases exponentially as the technology separation by implantation of oxygen (SIMOX). node changes. There are a few sources of For each new technology It uses ion implantation to inject oxygen into the leakage. Firstly, gate oxide thickness has thinned node, transistor feature size is silicon film and oxidises it to form a silicon dioxide down to its physical limits. Several atomic layers of layer during subsequent high temperature silicon dioxide are absolutely necessary in order reduced by about 30%, while annealing (around 1300 oC). This method was first to provide a good insulating layer which would developed by Nippon Telegraph and Telephone prevent excessive gate leakage. While doping the transistor density and Corporation, Japan, and later, Ibis became with nitrogen has improved the insulating property the leading company producing SIMOX SOI of the layer, a long-term solution is to introduce a speed are doubled wafers. However, the emergence of a new SOI thicker high dielectric constant (high-k) material, manufacturing technique has prompted the exit for example hafnium-based oxide, to increase of this technology. Today, the SmartCut (Unibond) the scalability. process has become the most popular and shown that in this way, it is possible to improve the widely accepted method in the industry, holding Another major current leakage path lies between subthreshold-slope from 90 mV/dec to 65 mV/ about 90% of the SOI market. the bottom edges of the source/drain-doped dec and would boost drive currents by up to 20% regions. The source/drain regions of the transistor at equivalent off-state current. The superior insulation of SOI technology offers are formed by “doping” of impurities which have the simplification in design process and superior Gaussian-type of concentration profiles. The non- The idea led to the rejuvenated interest in device performance. Devices on SOI have higher uniformity in the doping of silicon surfaces causes using silicon-on-insulator (SOI) to solve the immunity from radiation (alpha particles), lower a larger charge depletion region to form at the complementary metal oxide semiconductor power, higher speed, denser geometries, and bottom of the junctions. Problems arise when this (CMOS) scaling challenges. Before this, another simpler device processing. In addition, CMOS region is inverted faster than the silicon surface or type of SOI with a silicon-on-sapphire (SOS) structure devices built on SOI enjoy a high immunity to channel region. The implications of this are poor was used in military applications because of its latch-up as the parasitic low resistance path threshold voltage control, large current leakage, good radiation-hardness characteristics. through the bulk is unavailable. and a false turn-on phenomenon known as The common SOI wafer consists of a layer of The speed improvement of SOI is mainly derived punch-through effect. insulator, usually silicon dioxide, sandwiched from the reduced junction capacitances and The common solution is to use additional between a top layer of thin silicon and a bottom body effect. SOI CMOS transistors are reported to implantation steps at low angles and with high layer of thick silicon for mechanical support. The be about 25% faster than the operating speed energy to increase the concentration of the insulating layer minimises or removes the leaky of bulk transistors. SOI is also better suited for low doping species at these areas, thus reducing junction for separating the active silicon regions power and low voltage applications than bulk 54 July 2007 - EngineerIT silicon because of the low parasitic junction shrinking devices with lower voltages can operate the technology in the production of their next- capacitance (lower leakage) and superior correctly. The current power supply voltage for generation video game consoles. Except for transistor on-off characteristics. In addition, due leading edge semiconductor devices is around Sony’s Playstation, IBM has been involved in the to its good insulating ability, SOI devices are less 1 V to 1,2 V. For these devices, supervisory manufacturing of most SOI based-processors in susceptible to charging damage. circuits need to operate at 0,6 V. Present FDSOI the market. Apple’s Power PC-based systems and developments for voltage-reset circuits are high-end IBM servers are switching to SOI-based SOI devices can be fabricated on fully or partially targetting reset thresholds of 0,7 V and below. microprocessors. depleted-SOI (PD-SOI). For PD-SOI, the thickness of the active silicon layer is thicker than the maximum High-temperature applications IBM has also licensed the technology to, or depletion width under the gate. This would leave partnered with Sony, AMD and Chartered a thin neutral region that extends down to the SOI devices have a huge potential for high- Semiconductor, to develop different SOI-based buried oxide (BOX) layer. Fully depleted-SOI (FD- temperature applications that the bulk silicon technologies. IBM, the Sony group, and Toshiba SOI) devices have a layer of ultrathin active silicon devices cannot satisfy. Automotive electronics have adopted SOI technology for cell processors. so that the depletion width extends completely to require a higher performance than standard The world’s third largest foundry, Chartered the underlying oxide layer. Due to the absence electronic applications. In particular, on-engine Semiconductors had taken an early adoption of of a neutral layer, the subthreshold slope of the and on-transmission applications may require SOI technology and its latest Fab 7 has reported o device is steeper and closer to the theoretical maximum temperatures of up to 200 C, and a respectable earning since the end of 2005. value of 63 mV/dec. This reduces the leakage wheel-mounted applications may need even Currently, Chartered has engaged four or more current, when measured at the same Vt. However, higher. Application areas such as aerospace and clients for its SOI processes. PD-SOI is rarely used in volume production due to environmental monitoring may also require even As more work is done on SOI, a number of new several challenges in the fabrication process. higher temperature tolerance. applications are emerging as possible uses for A major deterrence for using SOI wafers is the high One of the main limitations of optical sensors the technology. These include a new transistor cost and supply issue of these wafers, compared to is their limited working temperature range, structure known as FinFET, novel semiconductor the traditional epitaxy silicon wafers. However, the which is typically about zero to greater than memory devices, SOI bipolar-CMOS (BiCMOS), o cost factor can be offset by the enhancement in 40 C. SOI enables optical sensors to have micro-electro-optical-mechanical systems devices built on SOI. SOI technology also enables higher temperature sensing and lower power (MEOMS) and SOI MEMS, amongst others. All of advanced devices that are extremely difficult to consumption. these technologies have specific requirements which could be satisfied by SOI’s properties. build on epitaxy wafers. In addition, the increasing Extremely low-power applications throughput in SOI wafers worldwide will eventually The success of layer transfer technology for solve the supply problem. By having lower power consumption, battery life fabricating SOI has also found new applications. can be extended significantly. Watches can be For a long time, it has been difficult to integrate SOI technology is currently used in the following concealed in a hermetic case where the battery photonics and CMOS due to the different applications: is not changeable.
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