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ELECTRICAL PROPERTIES of SILICON FILMS on SAPPHIRE SUBSTRATES a Thesis Presented for the Degree of Doctor of Philosophy in the U

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ELECTRICAL PROPERTIES of SILICON FILMS on SAPPHIRE SUBSTRATES a Thesis Presented for the Degree of Doctor of Philosophy in the U ELECTRICAL PROPERTIES OF SILICON FILMS ON SAPPHIRE SUBSTRATES A thesis presented for the degree of Doctor of Philosophy in the University of London by ALEXANDER BELL MARR ELLIOT Department of Electrical Engineering, Imperial College of Science and Technology and Post Office Research Centre Martlesham Heath, Ipswich January 1976 To Jan, Karen and Fraser 2 ACKNOWLEDGEMENTS The author is grateful to Mr R E Hines and Mr J W Woodward for assistance in the preparation of the test specimens and to his supervisor, Professor J C Anderson for his advice and encouragement. The work reported in this thesis was carried out at the Post Office Research Department and acknowledgement is made to the Director of Research for permission to publish this work. 3 • ABSTRACT A critical evaluation of published information on the properties of heteroepitaxial silicon layers on sapphire substrates is given, including a detailed comparative study of all the available data on the electrical properties of these layers. This review is followed by an account of an investigation of the electrical properties of thin layers as a function of depth in the film using two independent techniques, both of which employ the progressive penetration of a depletion region to vary the thickness of the layer measured. The first technique uses a deep depletion MIS Hall effect structure to measure the variation in carrier concentration and mobility through the epitaxial layer. Additional information is also obtained on the properties of the silicon-silicon dioxide and the silicon-sapphire interfaces. Because the MIS techniques is not capable of measuring the properties of all the films through to the sapphire interface a second technique, using a junction field-effect structure, is also used to obtain further carrier concentration and mobility information. The junction field-effect technique is not capable of measuring the properties of the region adjacent to the silicon dioxide interface and is therefore complementary to the MIS technique. It also provides information on the variation of carrier lifetime through the thickness Of the film. A concise discussion of the effect of variations in electrical properties on the performance, yield and reliability of MOS circuits fabricated in silicon-on-sapphire is given in the conclusions. 4 TABLE OF CONTENTS- CHAPTER 1 INTRODUCTION CHAPTER 2 PREPARATION AND PROPERTTRA OF HETEROEPITAXIAL FILMS OF SILICON ON SAPPHIRE 2.1 Deposition Techniques 2.2 Crystalline Properties 2.3 Stress 2.4 Autodoping 2.5 Deep Levels and Sapphire Interface States 2.6 Mobility 2.7 Lifetime CHAPTER 3 THE USE OF MIS DEEP DEPLETION HALL EntCT STRUCTURES TO STUDY THE CARRIER TRANSPORT PROPERTIES 3.1 Experimental Techniques 3.2 Mobility and Carrier Concentration 3.3 Temperature Dependence of Mobility 3.4 Detection of Phosphorus Transfer Anomaly 3.5 Electronic Interface Layers 3.6 Fast State Density at the Oxide Interface CHAPTER 4 CARRIER TRANSPORT STUDIES USING JUNCTION FIELD-EIEhCT STRUCTURES 4.1 Experimental Techniques 4.2 Calculation of Majority Carrier Density in the Presence of Traps 4.3 Conductivity Mobility 5 4.4 Lifetime Measurements from an Analysis of P-N Junction Reverse-Bias Currents 4.5 Experimental Results on p-type Evaporated Films 4.6 Experimental Results or n-type Films grown by the Pyrolysis of Silane 4.7 Slow Transients Resulting from Sapphire Interface States CHAPTER 5 GENERAL CONCLUSIONS REFERENCES APPENDIX 1 FABRICATION PROCESS FOR HALL EFFECT DEVICES APPENDIX 2 DEPLETION APPROXIMATION APPENDIX 3 FABRICATION PROCESS FOR N-CHANNEL JUNCTION FIELD- EFFECT DEVICES APPENDIX 4 LIST OF SYMBOLS APPENDIX 5 WORK PUBLISHED IN CONJUNCTION WITH THIS THESIS 6 CHAPTER 1 INTRODUCTION In conventional monolithic semiconductor integrated circuit technology the individual components in a circuit are isolated from each other by the depletion region surrounding a reverse-biased p-n junction. Whereas this isolation technique has been adequate for a large number of applications there is a requirement, particularly in the higher frequency applications, for an alternative isolation method which avoids the parasitic capacitance associated with the reverse-biased p-n junction. A variety of 'dielectric isolation' processes have been investigated and one of the simplest and most promising approaches has been to deposit a thin heteroepitaxial film of silicon on a suitable insulating substrate. Single-crystal a- alumina, (hereafter referred to as sapphire,) has been the most commonly used substrate material, (Allison et al 1969) although some work has also been done using magnesium aluminate spinel, (Cullen et al 1969). Most of the circuits fabricated in silicon on sapphire have been of the MOS type because they are more tolerant than bipolar circuits to the crystalline defects which inevitably occur in an imperfectly matched heteroepitaxial system. The silicon-on sapphire system has a number of advantages for MOS circuits. Firstly, although the individual transistors in MOS circuits do not require specific isolation there is always a possibility of spurious interconnection by means of inversion layers forming under thick oxide MOS structures. The use of separate islands of silicon, each isolated by the dielectric substrate, for all the circuit components completely eliminates the possibility of any such spurious interconnection. Secondly, the component packing density is improved because the 'channel-stopping' diffusions which are sometimes used to prevent the thick-oxide parasitic interconnection are unecessary and also because diffused regiairs can be placeli closer together without the possibility of depletion regions 'punching-through' to the adjacent diffusions. A third advantage is that if the films are only 1 to 2 microns thick and the source and drain are diffused through to the sapphire substrate significant speed improvements over bulk silicon circuits are obtained. The improvements result both directly from the reduction of junction capacitances and also from the ability to use gated silicon resistors (Wilcock 1971) as load components in place of the conventional load MOST. When complementary circuits are considered further advantages accrue. By using a two-stage epitaxial process or a one-stage epitaxial process and a diffusion, separate islands of n and p-type silicon can readily be made for the p and n-channel transistors repectively in a complementary circuit. Moreover a new design of complementary circuit using silicon islands of a single conductivity type is also possible (Boleky 1970) if deep-depletion transistors of the type described by Heiman (1966) are used. The two special silicon-on sapphire devices mentioned above„namdly the gated resistor and the deep-depletion transistor, operate by conduction in the bulk of the film and hence their characteristics will be influenced by any varia- tions in the carrier transport properties through the film. Although informa- tion on the variation of carrier transport properties in silicon on sapphire films of the order of 10 microns thick is available in the literature (Dumin and Robinson 1966 and 1968) and also some information on the average properties of thinner films there is little information on the variations in properties of films only 1 to 2 microns thick. The work reported herein was undertaken in an attempt to provide this missing information. • Before proceeding to the main experimental investigation a critical review of 8 all the published information on the electrical and structural properties of silicon on sapphire layers was conducted and this is presented in Chapter 2. Also included in this review is any information on the silicon on magnesium aluminate spinel system which is thought to be relevant to the silicon on sapphire system. The profiling technique employed in the thicker films was to gradually thin the film by mechanical or chemical means and to make Hall and conductivity measurements at each step either using a Hall bar or by the van der Pauw (1958) technique. However if the film is only 1.5 pm thick with a donor 15 -2 11 concentration of 5 x 10 cm there are only 7.5 x 10 donors per square cm of film and trapping of carriers at both silicon interfaces is likely to significantly influence the transport properties. Because the sapphire inter- face states will remain invariant during a set of measurements they will not influence the calculation of the properties of the removed layer unless the film is sufficiently thin for the space charge layer to penetrate the entire film. However the new air interface which is exposed at each removal step is unlikely to exhibit a constant surface state density and carrier density errors in excess of 10 per cent at a film thickness of 1.5 pm are probable for 10 -2 fairly moderate surface state density variations of 7.5 x 10 cm . There- fore, even if accurate thinning techniques could be developed for 1.5 pm thick films, the errors involved in using the conventional Hall techniques could become very large as the sapphire interface is approached. An alternative method of varying the thickness of a conducting layer is by progressively driving a depletion region into the film. This method of thickness modulation which has the advantage that the depletion layer boundary is free of interface states is the basis of both the profiling techniques used in this investigation. The e:cperimental structure used in the first technique is a 300/Lm square deep depletion 1:13 transistor and the depletion region is driven in from the oxide interface by applying the appropriate gate potential. The MIS Hi11 and conductivity measurements as a function of gate voltage are combined with C-V measurements to provide both the carrier concentration and mobility profiles. These measurements and results are presented in Chapter 3. Chapter 4 contains work done using the second technique which employs a large junction field-effect transistor with a channel width of 600pm and a channel length of 140pm. The carrier concentration profile is obtained from an analysis of the C-V characteristics of the reverse-biased gate junction and the Mobility profile from these characteristic together with channel conductivity measurements as a function of gate voltage.
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