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Sof-Fet) a New Device for the Next SILICON ON FERROELECTIC INSULATOR FIELD EFFECT TRANSISTOR (SOF-FET) A NEW DEVICE FOR THE NEXT GENERATION ULTRA LOW POWER CIRCUITS A THESIS IN Electrical Engineering Presented to the Faculty of the University of Missouri – Kansas City in partial fulfillment of the Requirements for the degree MASTER OF SCIENCE By Azzedin D. Es-Sakhi Bachelor of Science (BS) in Electrical and Computer Engineering, University of Missouri-Kansas City, USA 2011 Kansas City, Missouri 2013 ©2013 Azzedin D. Es-Sakhi ALL RIGHTS RESERVED SILICON ON FERROELECTIC INSULATOR FIELD EFFECT TRANSISTOR (SOF-FET) A NEW DEVICE FOR THE NEXT GENERATION ULTRA LOW POWER CIRCUITS Azzedin D. Es-Sakhi, Candidate for the Master of Science Degree University of Missouri - Kansas City, 2013 ABSTRACT Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub- nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor’s Law. Furthermore, the device is compatible with silicon fabrication process. iii Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low- power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage. iv APPROVAL PAGE The faculty listed below, appointed by the Dean of the School of Computing and Engineering have examined a thesis titled “Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET) a New Device for the Next Generation Ultra Low Power Circuits” presented by Azzedin Es-Sakhi, candidate for the master of science degree, and certify that in their opinion it is worthy of acceptance. Supervisory Committee Masud H Chowdhury Ph.D., Committee Chair Associate Professor, School of Computing and Engineering Ghulam M. Chaudhry Ph.D Chair for Department of Computer & Electrical Engineering Dr. Yang (Cindy) Yi Ph.D Associate Professor, School of Computing and Engineering Dr. Deb Chatterjee Ph.D Associate Professor, School of Computing and Engineering v CONTENTS ABSTRACT ....................................................................................................................... iii LIST OF ILLUSTRATIONS ............................................................................................. xi LIST OF TABLES ........................................................................................................... xvi ACKNOWLEDEMENTS ............................................................................................... xvii DEDICATION ............................................................................................................... xviii CHAPTERS 1. INTRODUCTION .................................................................................................... 1 1.1 Organization .............................................................................................................. 1 1.2 Thesis Objectives ...................................................................................................... 2 1.3 Nanotechnology Challenges ...................................................................................... 3 1.4 Recent and Emerging Device Technologies ............................................................. 4 1.4.1 Emerging Field of Ultra Low Power Devices ................................................. 4 1.4.2 Silicon-On-Insulator (SOI) Devices ................................................................ 9 1.4.3 Carbon Nanotube Field Effect Transistor (CNTFET)................................... 10 1.4.4 Multi-gate Transistors ................................................................................... 12 1.4.5 Tunneling Field Effect Transistors (TFETs) ................................................. 13 1.4.6 Negative Capacitance Gate Stock Transistors .............................................. 14 1.5 Contribution ............................................................................................................ 15 2. CARBON NANOTUBE FIELD EFFECT TRANSISTOR .................................... 17 2.1 Introduction ............................................................................................................. 17 2.2 Ballistic Transport and Mean Free Path .................................................................. 20 vi 2.3 Unique Properties of Carbon Nanotubes ................................................................. 21 2.4 Carbon Nanotube Field Effect Transistors .............................................................. 22 2.5 Carbon Nanotube Basics and Theoretical Considerations ...................................... 23 2.6 Capacitance Modeling of CNT-FET ....................................................................... 24 3. MULTI-GATE TRANSISTORS - FINFET ........................................................... 26 3.1 Introduction Into SOI and Multi-gate Devices ........................................................ 26 3.2 Silicon-On-Insulator Transistors (SOI) ................................................................... 27 3.3 The Road to Multi-gate Devices ............................................................................. 29 3.4 Introducing the FinFET ........................................................................................... 30 3.5 FinFET Structure Analysis ...................................................................................... 33 3.6 FinFET Advantages ................................................................................................. 36 3.7 Undoped Channel FinFET ...................................................................................... 39 4. SUBTHRESHOLD SWING .................................................................................... 41 4.1 Introduction ............................................................................................................. 41 4.2 How to Achieve S Less Than 60mV/ decade .......................................................... 46 4.3 High-k Gate Insulator .............................................................................................. 48 5. TUNNELING FIELD EFFECT TRANSISTORS ................................................... 50 5.1 Introduction ............................................................................................................. 50 5.2 Tunneling Phenomena- Esaki Tunnel Diode .......................................................... 51 5.3 Various Tunneling Field Effect Transistors ............................................................ 52 5.3.1 Inter-band SOI ............................................................................................... 53 5.3.2 Carbon Nanotubes CNT ................................................................................ 53 vii 5.3.3 Graphene Nanoribbon GRN .......................................................................... 59 5.3.4 Staggered Hetrojunctions .............................................................................. 61 6. I-MOS AND NANOWIRE FETS ........................................................................... 64 6.1 Impact Ionization Transistors .................................................................................. 64 6.2 Nanowire Transistors .............................................................................................
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