way presents its own set of technical advantages and challenges. For advanced RF SOCs, high Advanced Electronic Substrates impedance SOI substrates with a high resistivity handle wafer provide Volume 1–LOS ANGELES, CALIFORNIA significant advantages,23 while SOI for the Nanotechnology Era with ultra thin buried oxide (<50 FROM THE %#3 ,OS !NGELES MEETING /CTOBER nm) will enable IC architectures where n and p regions are defined 4HE FOLLOWING ISSUES OF %#3 4RANSACTIONS ARE FROM SYMPOSIA HELD DURING THE ,OS !NGELES MEETING !LL ISSUES ARE AVAILABLE IN by Carlos Mazuré and George K. Celler in the handle substrate for back ONLINE EDITIONS WHICH MAY BE PURCHASED BY VISITING HTTPWWWELECTROCHEMORGDLECST 3OME ISSUES ARE ALSO AVAILABLE IN HARD bias generation through the buried COVER EDITIONS 0LEASE VISIT THE %#3 WEBSITE FOR ALL ISSUE PRICING AND ORDERING INFORMATION oxide.24 Since attaining the highest or the last few decades the in order to boost carrier mobility. Wafer performance is not the focus here, performance of silicon integrated level tensile biaxial strain will further these SOI CMOS solutions will target !VAILABLE )SSUES(ARD #OVER /NLINE Fcircuits has steadily progressed, as enhance the channel engineering the lowest power consumption and anticipated by Moore’s law, primarily possibilities. Three-dimensional devices longest battery lifetime. Low standby 6OL 0HYSICS AND #HEMISTRY OF 3I/ 6OL #ORROSION AND %LECTROCHEMISTRY 6OL 3OLID 3TATE )ONIC $EVICES )6 through scaling of all critical device like FinFETs21,22 may supplement and low operating power devices .O AND THE 3I 3I/ )NTERFACE .O OF !DVANCED -ATERIALS IN (ONOR OF .O %DITORS % $ 7ACHSMAN & ( 'ARZON dimensions.1 This classical scaling is and eventually replace planar device will be built by taking full advantage %DITORS ( : -ASSOUD * ( 3TATHIS +OJI (ASHIMOTO % 4RAVERSA 2 -UNKUNDAN 6 "IRSS either no longer possible (for example structures.1 SOC applications will of dielectric isolation, while high 4 (ATTORI $ -ISRA AND ) "AUMVOL %DITORS 3 &UJIMOTO ( (ABAZAKI (ARD COVER - .- gate SiO2 thickness has reached its push PD SOI and high impedance resistivity substrates will substantially (ARD COVER - .- % !KIYAMA " -AC$OUGALL /NLINE - .- limit) or does not allow achieving the SOI designs, possibly transitioning improve performance of passive /NLINE - .- (ARD COVER - .- targeted device performance increase over to FD designs for very low power components such as inductors that are /NLINE - .- 6OL $URABILITY AND 2ELIABILITY OF ,OW per technology node. Starting with applications. Figure 1 is also a good placed directly on the silicon chip. 6OL 3TATE OF THE !RT 0ROGRAM ON .O 4EMPERATURE &UEL #ELLS 3YSTEMS the 90 nm technology, innovations illustration of some of the engineered .O #OMPOUND 3EMICONDUCTORS 6OL 0HYSICS AND 4ECHNOLOGY %DITORS 4 $ *ARVI ( 'ASTEIGER other than simple scaling are the main substrate options being evaluated for SOI Substrate Fabrication 3/4!0/#3 8,))) AND .ITRIDE AND .O OF (IGH K 'ATE $IELECTRICS ))) 3 #LEGHORN contributors to better performance. the 65, 45, and 32 nm nodes. Substrate engineering2,3 has enabled The high performance path will Silicon on Insulator (SOI) 7IDE "ANDGAP 3EMICONDUCTORS FOR %DITORS 3 +AR $ -ISRA ( )WAI (ARD COVER - .- 3ENSORS 0HOTONICS AND %LECTRONICS 6) - (OUSSA $ ,ANDHEER 7 4SAI /NLINE - .- the industry to overcome many continue to be the driver for the technology was initiated in the 1960s %DITORS * * 7ANG & 2EN 3 $E'ENDT of the limitations encountered by most advanced substrates and the by the demands of radiation-hard AND 2 # &ITCH traditional scaling. As a result, device material innovation. Ultra-thin (UT) circuits. During 1970s and ‘80s several (ARD COVER - .- architecture and engineered substrates SOI, mobility enhancing substrates SOI materials and structures were /NLINE - .- (ARD COVER - .- have become strongly coupled, a like strained SOI (sSOI), in addition conceived for dielectrically separating /NLINE - .- 6OL 0ROTON %XCHANGE -EMBRANE coupling that is growing stronger as to local strain techniques, as well the thin, active device volume from the IC industry moves to the 65 nm as improved thermal dissipation to the silicon substrate.5- 7 The background 6OL #LEANING 4ECHNOLOGY IN 3EMICONDUCTOR .O &UEL #ELLS 6 IN (ONOR OF technology node and beyond. Substrate 3UPRAMANIAM 3RINIVASAN .O $EVICE -ANUFACTURING )8 engineering started in earnest with %DITORS * 2UZYLLO 4 (ATTORI %DITORS 4 &ULLER # ,AMY # "OCK the industry transition to SOI wafers AND 2 % .OVAK (ARD COVER - .- in the late ‘90s.4-7 SOI substrates (ARD COVER - .- /NLINE - .- made possible increasing the drive /NLINE - .- current while simultaneously reducing parasitic leakage, thus improving IC performance and reducing power !VAILABLE )SSUES/NLINE /NLY SEE THE %#3 WEBSITE FOR PRICING AND ORDERING INFORMATION consumption. SOI has allowed the IC industry to develop superb solutions for high performance logic, 6OL #ORROSION 0ROTECTIVE #OATINGS AND 6OL -OLECULAR 3TRUCTURE %FFECTS 6OL #ORROSION 0OSTERS 'ENERAL including the latest gaming-dedicated .O )NHIBITORS %DITORS - +ENDIG .O IN (ETEROGENEOUS %LECTRON .O %DITOR * 7EIDNER microprocessors.8-10 Other highly 2 'RANATA ' / )LEVBARE 3 +URODA 4RANSFER +INETICS 6OL competitive designs address “smart %DITORS ' "RISARD $IELECTRICS AND THE $IELECTRIC 6OL .O power” for automotive,11 and very low !TOMIC ,AYER $EPOSITION 2 7 &AWCETT $ %VANS %LECTROLYTE )NTERFACE IN "IOLOGICAL .O %DITORS ! 2 ,ONDERGAN AND "IOMEDICAL !PPLICATIONS power ICs for consumer applications.12 ' 3 -ATHAD ( ' :OLLA 4 0 #HIANG 6OL 0HYSICAL %LECTROCHEMISTRY 'ENERAL %DITOR * 7EIDNER In more recent advances beyond .O %DITOR ' "RISSARD 6OL #OPPER )NTERCONNECTS .EW #ONTACT 6OL 4HERMAL AND 0LASMA conventional SOI, new substrates like 13-17 .O AND "ARRIER -ETALLURGIES3TRUCTURES 6OL !COUSTIC 7AVE "ASED .O #6$ OF .ANOSTRUCTURES strained SOI and hybrid bonding AND ,OW K )NTER LEVEL $IELECTRICS ))) .O 3ENSORS AND 3ENSOR 3YSTEMS %DITOR * 7EIDNER SOI18-20 have increased the number of %DITORS ' 3 -ATHAD - %NGLEHARDT %DITOR ' (UNTER options for enhancing device mobility. 6OL + +ONDO ( 3 2ATHORE 3OLID 3TATE 0OSTERS 'ENERAL 6OL 4HREE $IMENSIONAL -ICRO AND .O %DITOR * 7EIDNER While the 90 nm node is 6OL %LECTRODEPOSITION OF .ANOENGINEERED .O .ANOSCALE "ATTERY !RCHITECTURES characterized by the adoption of SOI 6OL 8- 10 .O -ATERIALS n %DITORS . 6 -YUNG %DITOR * 7EIDNER 3CIENCE 4ECHNOLOGY AND 4OOLS FOR for high performance applications, .O %LECTRODEPOSITION FROM ,AB TO &ACTORY 2 - 0ENNER . * 4AO $ 9 0ARK the future nodes are driving numerous Fig. 1. Device architectures that are either already in use or are anticipated in future 6OL 3ENSORS !CTUATORS AND -ICROSYSTEMS %DITOR * 7EIDNER substrate solutions. The device 6OL 'REEN %LECTRODEPOSITION .O %DITOR ' (UNTER : !GUILAR 3 !KBAR technology nodes. 6OL development of the future technology .O %DITORS 3 2OY ' :ANGARI # "RUCKNER ,EA - *OSOWICZ %NERGY 4ECHNOLOGY .O 2 -UKUNDUN AND * 2 3ETTER AND "ATTERIES 'ENERAL nodes appears to be marked by two reduce the impact of hot spots on idea is that in a bulk silicon MOS 6OL %NERGY FOR #LEANER 4RANSPORTATION %DITOR * 7EIDNER distinct technical strategies, one MOSFET performance, are among the transistor, only a superficial layer, .O %DITORS + :AGHIB * 0RAKASH 6OL 3ENSORS "ASED ON .ANOTECHNOLOGY )) 6OL focused on high performance, and most obvious engineered substrate typically <100 nm thick, is actually 2 $ -C#ONNELL & 2 -C,ARNON .O %DITOR ' (UNTER AND * 2 3ETTER 0HOTOVOLTAICS FOR THE ST #ENTURY ))) .O %DITOR * 7EIDNER one driven by system-on-chip (SOC) solutions. Device architectures are useful for electron transport, whereas 6OL %LECTROCHROMICS FOR %NERGY %FFICIENCY 6OL 3TUDENT 0OSTERS 'ENERAL applications, including low power, likely to remain planar at least for the the substrate causes undesirable effects. 6OL .O &ROM THE -ATERIAL TO THE 3YSTEM .O %DITOR * 7EIDNER 0HYSICS AND #HEMISTRY OF .O portable RF applications. Figure 1 is next two generations, with non-planar The overwhelming success of bulk- %DITORS + :AGHIB * 8U ,UMINESCENT -ATERIALS 8)6 6OL a tentative device roadmap for logic FinFETs on the horizon for the 32 nm Si CMOS confined SOI technology to # - *ULIEN & $3OUZA "ATTERY 3AFETY AND !BUSE 4OLERANCE %DITOR * 7EIDNER .O %DITOR * 7EIDNER applications. Today’s partially depleted node for the most aggressive IC players. niche applications until late 1990s. 6OL 6OL -ULTISCALE 3IMULATIONS OF /RGANIC AND "IOLOGICAL (PD) transistor architecture may evolve Partially depleted approaches will push Then several factors have increased 6OL .O .O %LECTROCHEMICAL 3YSTEMS 0RIMARY AND 3ECONDARY %LECTROCHEMISTRY 0OSTERS 'ENERAL into a fully depleted (FD) approach. the mobility enhancing substrates the interest in SOI: invention of .O #OMPUTATIONAL !SPECTS !QUEOUS "ATTERIES %DITOR * 7EIDNER High performance logic utilizes while others may switch to ultra-thin new fabrication methods for SOI %DITOR * 7EIDNER %DITORS 6 2 3UBRAMANIAN uniaxial tensile strain for n channels fully depleted SOI in order to improve ' ' "OTTE 2 # !LKIRE 6OL 2ECHARGEABLE ,ITHIUM and compressive strain for p channels electrostatic device characteristics. Each (continued on next page) * 3T 0IERRE * -EYERS + 2 (EBERT .O AND ,ITHIUM )ON "ATTERIES %DITOR * 7EIDNER The Electrochemical Society Interface • Winter 2006 33 Fig. 2. A schematic process flow for SOI wafer fabrication by Smart Fig. 3. Crystalline plane orientations and directions within the planes that Cut technology. improve electron and/or hole mobility in Si MOSFETs. materials and their optimization, need The Smart Cut technology is a Substrates with Enhanced Charge for lower power and higher speed powerful tool that applies to many Carrier Mobility circuits, emerging limitations of bulk materials, making it possible to create CMOS scaling. SOI transistors are a wide range of composite substrates Mobility enhancing substrates now unchallenged in extending the and their tailoring to the requirements are emerging as an essential tool in frontiers of ultimate CMOS scaling. of the application by properly the effort to continue improving Si Epitaxy and single crystal layer choosing the active layer, the buried circuit performance by 17% per year, transfer are the two most critical dielectric and the base substrate.28,29 as dictated by the ITRS.1 Two major processes for substrate engineering that approaches are hybrid orientation allow the tailoring of the composite High Resistivity SOI SOI and strained silicon SOI. In the substrate to the application. Smart first case, a composite substrate is CutTM technology is the dominant Cross-talk between RF analog built with (110) and (100) crystal method for thin layer transfer and SOI circuits and digital logic contained orientation regions for the p- and n- fabrication.25- 27 It consists in defining within the same “mixed signal” chips channels, respectively.20 In the second a splitting region within the donor is reduced in SOI substrates. High case, a biaxially strained Si film is substrate by ion implantation (e.g. H+ impedance SOI, i.e. SOI in which used as the top SOI layer to boost the or He+) that allows transferring a thin the handle substrate has resistivity electron mobility.13-17 film to a handle wafer by means of >1 kOhm-cm, enhances these Mobility optimization in composite bonding followed by splitting. The first advantages and improves performance wafers with hybrid crystal orientation industrial implementation of the Smart of monolithically integrated passive (SOI and DSB).—Traditional (100) Si Cut technology is SOI manufacturing. components, such as inductors. substrate orientation serves well NMOS The simplicity of the concept is SOI technology provides complete transistors as electron mobility is schematically illustrated in Fig. 2. oxide isolation, cutting off direct near its peak in such a configuration. First, a thermal oxide is formed on paths of substrate injection noise and However hole mobility in the (110) the donor wafer followed by hydrogen a high resistivity substrate reduces plane is approximately double of that implantation with doses typically in the the capacitive coupling, thus further for the (100) surface plane. Substrate mid 1016cm-2 range. The implantation reducing the substrate related RF loss. engineering permits optimizing energy determines the thickness of the Because of the SOI-inherent isolation NMOS and PMOS performance transferred layer; the thermal oxide of the high impedance substrate, simultaneously by means of using thickness defines thickness of the device latchup is not an issue. composite substrates that contain buried oxide (BOX) in the final SOI Patterned ground shields (PGS) are both crystal orientations. Hybrid structure. After cleaning and surface used in Si bulk wafers to manufacture orientation composite SOI is fabricated activation, the donor and handle wafers high quality factor Q inductors. In by transferring a (110) Si layer onto a are bonded together. By splitting at SOI these can be avoided and better (100) handle wafer as schematically the H+ implanted region, a thin film Q factors are achieved even at higher shown in Fig. 3. Another variation is a is transferred to the handle substrate. frequencies. Typically 50% greater Q is (100) film on a (110) substrate. Subsequent steps remove the post- achieved with high resistivity SOI (SOI For 40 nm long p-MOSFETs splitting surface roughness. Since the HR) as compared to bulk.23 Coplanar fabricated on a (110) surface a current thickness removed from the donor wafer transmission line measurements on drive increase of 45% is achieved, but is negligible compared to the total wafer SOI HR show that a loss better than 0.5 in contrast, the n-MOSFET on the thickness, the donor wafer can be reused dB/mm at 40 GHz and 1 dB/mm at 80 (110) plane is degraded by 35%.20,30 many times. A range of thicknesses from GHz can be achieved. At these values To overcome this problem, windows 10 nm up to a few 103 nm for both top integrated passive components in SOI corresponding to the n channel Si and BOX films is easily covered by HR become comparable to what can be regions are etched in the substrate this technology with standard industrial achieved on InP. through the buried oxide down to implanters and furnaces. the (100) handle substrate. Then Si
34 The Electrochemical Society Interface • Winter 2006 selective epitaxial growth follows after a spacer formation. A strong overgrowth is required to drive defects out of the active area with facet formation above the substrate plane. A final CMP step planarizes the topography and a composite wafer with (110) and (100) regions embedded in the same surface are obtained.20 The obvious drawback of this approach is that one of the devices is fabricated on bulk. Although SOI structures provide many advantages, circuits that are specifically designed for bulk silicon can also utilize hybrid orientation substrates. In such cases the composite wafers also contain Fig. 4. (a) XTEM image of the DSB wafer and (b) XRTEM image of the bonding interface two crystal orientations as described (from Ref. 31). above, but the intervening buried oxide (BOX) is eliminated as shown for the n-MOSFETs, resulting in an result of this work is that it shows that in TEM cross sections of Fig. 4.31 increase of 40% in the current drive. even for super-critical thicknesses the Such wafers, known as DSB for If the concentration of Ge is increased strained Si film does not relax after Direct Silicon Bonding, are another up to 40%, the same level of mobility patterning and device fabrication if example of enhancements that are enhancement is also achieved for p- appropriate care is given. The strain possible because of layer transfer. channels.16,39,40 Currently, substrates in the active areas is monitored In order to access both orientations originating from 20%Ge template, electrically through a threshold voltage at the wafer surface, the same with strained silicon directly on VT shift that is a result of the smaller approach as for hybrid SOI wafers insulator (sSOI) are commercially band gap of the strained Si film. The can be taken. However, a simpler available and are being evaluated by threading dislocations defectivity of and potentially more cost-effective the IC industry. sSOI has been improved to <104 cm-2. method of selective amorphization Fabrication of sSOI13 has many steps For moderately strained Si, such and templated re-gr owth has been in common with the SOI process flow as obtained by Si epitaxy on 20% described recently.32,33 shown in Fig. 2. Device processing Ge SiGe, the dilemma is that simple Some enhancement in CMOS in sSOI substrates can be done with biaxial tensile strain is beneficial performance can be obtained by a less for n-MOSFETs but somewhat complex but also less effective PMOS detrimental for p-MOSFETs. To mobility enhancing substrate that is fully exploit the potential of sSOI obtained simply by rotating the top substrates, strain hybridization (100) Si film with respect to the (100) is essential. Figure 5 shows the substrate by 45°.18,19 preferred strain configurations for Strained SOI (sSOI).—A powerful n-MOS and p-MOS. In an n-NMOS technique for increasing carrier device (Fig. 5a), biaxial tensile mobility and current drive in CMOS strain as provided in sSOI is shown. involves introducing strain into This enhances current drive. Any transistor channels. Uniaxial local additional process-induced uniaxial strain—obtained, for example, by tensile strain can be superimposed using recessed SiGe stressors in p- on the substrate level strain for even MOSFETs34 or compressive and tensile greater performance boost. This is nitride encapsulation for p- and n- demonstrated in data from Thean et channels, respectively,35 is presently a al.42 in Fig. 6, where adding uniaxial well established technology. Another strain to conventional SOI increases approach that we will describe here the drive current by 9% but adding is based on biaxial tensile wafer-level Fig. 5. Ideal strain configurations for n-MOS the same tensile etch stop (tESL) layer strain. The biaxial tensile strain lifts and p-MOS transistors (after Ref. 42). to sSOI gives a total boost of 9%+18% the conduction band degeneracy as compared to SOI alone. In other between the in-plane and the out-of- conventional thermal budgets, as there words, everything else being equal, plane valleys, and as a consequence it is no strain relaxation up to 1100°C if sSOI improves the current by 18%. enhances carrier mobility by means proper surface passivation is applied. Figure 5b shows the ideal of reduced intervalley scattering and Typical strained Si film thickness strain configuration for p-MOS a smaller in-plane electron effective varies from 10-20 nm for FD devices as determined from piezoelectric mass.36 A similar effect is achieved for architectures and up to 70 nm for full coefficients of silicon—uniaxial holes for significantly higher levels of compatibility with existing PD designs. compression along the current flow strain that lifts the heavy and light Typical stress values are 1.3 GPa ±20 and tension in the direction normal hole degeneracy. MPa, one sigma variation.17 to it. This configuration cannot be The final mobility and current The scalability of sSOI has been obtained by either substrate level drive increase of n- and p-channel thoroughly investigated for ultrathin or process-induced strain alone. devices depend on the Ge content body sSOI14,15 with the fabrication of Compression along the current flow of the SiGe template used to create short channel devices. More recently, axis can be produced by strained the strain.16,37 For a strained Si film the impact of 40 to 50 nm thick sSOI nitride etch stop layers and/or by grown on a fully relaxed SiGe (20% on PD MOSFETs has been reported,41 SiGe epitaxial layers embedded in the Ge) template, a biaxial stress level of showing a 30% reduction in gate oxide source/drain regions. STI (shallow 1.3 GPa is achieved.13,17,38 This leads leakage and a 60% improvement of the to a mobility enhancement of 80% SRAM write margins. An important (continued on next page)
The Electrochemical Society Interface • Winter 2006 35 Fig. 6. Drive current IDsat vs. Ioff for n-MOS devices with various Fig. 7. Drive current IDsat vs. Ioff for p-MOS devices with various stressors (from Ref. 42). stressors (from Ref. 42).
trench isolation) can produce Germanium on Insulator (GeOI) technology progresses is the impact of compression along one or both lateral the narrow band gap of Ge (0.66 eV) axes, depending on device geometry. GeOI45-47 is the newest development on junction leakage and band-to-band However, to obtain the desired among the mobility enhancing tunneling. configuration as shown in Fig. 5b, substrates. It is of interest for high 48 it is necessary to combine an sSOI performance CMOS ICs as well as for SOI with Alternate Dielectrics substrate with process-induced photodetectors and solar cells.49 The strain, for example with cESL. Ge donor wafer can be an epitaxially The thermal conductivity of the For best results, during device grown Ge layer on a Si substrate or buried oxide is almost 100 times processing on sSOI an additional a Ge bulk wafer. Ge bulk wafers are smaller than that of Si. Therefore, step of Selective Uniaxial Relaxation heavier than Si and brittle. GeOI helps local self-heating in SOI can be a (SUR) is implemented to eliminate overcome these issues and makes Ge concern for devices that are used tensile strain parallel to the device MOSFET technology compatible with in the on-state most of the time, axis, while preserving the transverse Si processing facilities. The epitaxial for circuits with a high duty cycle, tensile strain. Subsequently, approach to the Ge donor is easily and for bipolar ICs. Scaling the Si conventional uniaxial compressive scalable to 300 mm but suffers from film thickness degrades the thermal stressors are applied. The finished p- high crystal defectivity. Processing a conductivity and increases the MOS devices have the most desired Ge surface is a difficult task because thermal resistance, with thin Si configuration (Fig. 5b) with uniaxial the typical Si cleaning solutions etch and thick BOX as the worst case.51 tension perpendicular to the current and roughen the Ge surface. Although A simple countermeasure is to scale and uniaxial compression along the GeOI processing in a Si facility and down the BOX thickness. A factor current. Data in Fig. 7 show that cESL the fabrication of 0.15 µm devices of three improvement in thermal 50 alone improves IDsat by 30%, but sSOI has been demonstrated, MOSFET conductance can be achieved by with SUR adds another 6%. Further Ion/Ioff ratios are poor and mobility reducing the BOX thickness from optimization is expected to yield values need to be improved. MOSFET 150 nm to 20 nm.52 The tradeoff is, much greater enhancements. quality on Ge surfaces is an issue that of course, increasing the parasitic To summarize, by combining needs to be addressed for Ge and GeOI capacitances and reducing the uniaxial stressors with a biaxially substrates alike. The main question overall device performance. Another tensile starting sSOI substrate, both that will have to be addressed as GeOI approach is to introduce a high n-MOS and p-MOS devices are improved beyond what would be possible with process-induced strain alone. Si (strained) Band-gap engineering - dual channel Ec MOSFETs.—The combination of Si0.4Ge0.6 (strained) epitaxy and layer transfer opens Relaxed Si0.7Ge0.3 (relaxed) up a multitude of possibilities to Si1-xGex modify the band structure and take SiO2 the mobility enhancement beyond Ev the present sSOI.43,44 Dual channel is an example of a band structure Si Sub engineered by epitaxy. Figure 8 shows Strained-Si1-yGey the results for a composite top layer of Gate Strained-Si strained Si/strained Si0.4Ge0.6/relaxed Oxide Si0.7Ge0.3. A hole mobility increase by a factor of 2-3 can be obtained, even at high carrier densities, as compared Fig. 8. Schematic layer structure and band diagram for a dual channel device that is based on 43 to SOI or SGOI substrates. strained Si deposited on top of strained SiGe (after Ref. 43 and 44) .
36 The Electrochemical Society Interface • Winter 2006 thermal conductivity material as the buried dielectric. There are several options52 but silicon nitride appears to be the most attractive one. It is an industrially mature material, it exhibits an order of magnitude higher thermal conductivity than SiO2, and it is a well-characterized insulator. Si (240 nm) It has been shown that a composite nitride/oxide buried dielectric, as shown in Fig. 9, is a viable approach for an improved thermal conductivity Si N (400 nm) substrate.53 3 4 In contrast, if the focus is low power consumption, ultra-thin BOX is very advantageous. It offers the possibility to easily form buried n and SiO (400 nm) p regions in the handle substrate as 2 a back gate for low voltage operation and also for improved SRAM stability.
Self-organized Nano-Patterns Facilitated by Wafer Bonding
Precise misalignment of two Fig. 9. SEM micrograph of a composite nitride/oxide buried dielectric under a silicon film. crystalline lattices leads to formation of controlled and regular networks of dislocations. Figure 10 shows an The generation of excess negative or ψ =ψ =0.445±0.005°0.445±0.005° example of a 2D dislocation array positive charge in the body can be obtained by bonding two Si (100) used to store data states as illustrated wafers with a small twist angle between in Fig. 11.57 In an n-channel device an the top and bottom wafer.54 The excess of positive charges leads to an dislocation arrays induce 2D periodic increase of the current drive, defining strain fields at the surface of ultra thin state “1”. The removal of positive Si bonded layer and can be used as charges from the body decreases the template for nano-organization of the channel current, defining subsequent processes, e.g., nanogrowth state “0”.56- 60 The strong industrial of Ge quantum dots, memory crystals, potential of the floating body cell DNA cells. It is important to notice that (FBC) comes from the fact that very layer transfer is a unique technique that dense embedded memory blocks allows nano-scale self-organization over can be realized with a standard SOI wafer-size surface areas. process, with a memory cell footprint that is approximately one half of that ≈≈1µm Some Unique Devices Enabled by SOI of an embedded DRAM.61 1µm Taking into account that embedded SOI substrates are used in memory occupies more than 70% high volume manufacturing of of today’s microprocessors10,55 FBC Fig. 10. A two-dimensional dislocation array obtained by bonding two Si (100) microprocessors and “smart power” wafers with a small twist angle Ψ between devices, are utilized in high voltage (continued on next page) the top and bottom wafer (from Ref. 54). circuits, ultra-low power circuits, MEMS devices, and are entering the RF and photonics area. In addition there are some applications that would be 90 nm Vg = 1V almost impossible without SOI. We 0.003 describe two such cases below. “1” Capacitor-less one transistor SOI DRAM.—Floating body effects result “0” from the generation of excess charge 0.002
in the SOI body, which change [mA] 0.8 s the channel potential. During I “1” high frequency operation, device charging and discharging leads to “0” memory effects and, because of its 0.001 iterative nature, to history effects. IC 0.6 designers put special attention on the “1” management of floating body effects “0” to avoid noise and threshold voltage instabilities.55 On the other hand, the 0 floating body effect if well controlled 0 0.5 1 1.5 can be used for data storing. V [V] Capacitor-less one transistor d DRAM cells are a new development which takes advantage of the floating Fig. 11. Electrical I-V curves of a floating-body SOI transistor depend on the charge that is present body effect in SOI MOSFETs.56-58 in the body. This can serve to store memory bits (from Ref. 57).
The Electrochemical Society Interface • Winter 2006 37 embedded memory will allow for a are growing. High resistivity SOI J. Gautier, and J. M. Hode, IEDM Tech. reduction of the overall die area or substrates gain interest for RF and SOC Dig. Int. Electron Devices Meet., 808 the addition of significantly more applications. The ultra thin buried oxides (1984). memory at constant die area. are a feature that allows the integration 5. S. Cristoloveanu and S. S. Li, Electrical FinFETs and other multigate of a back-gate for dynamic threshold Characterization of Silicon on Insulator Materials and Devices, Kluwer Academic transistors.—Multiple-gate FD voltage control. Integration of embedded Publishers, Boston (1995). transistors provide better electrostatic one-transistor floating body memories 6. J.-P. Colinge, Silicon-on-Insulator control in the device channel than is on SOI will result in ICs that will Technology: Materials to VLSI, 2nd ed., possible with traditional single gates. have speed and power advantages at a Springer, New York (1997). Three-dimensional structures known significantly lower cost. When transition 7. G. K. Celler and S. Cristoloveanu, J. as FinFETs after the “fin” like shape to fully depleted multi-gate devices Appl. Phys., 93, 4955 (2003). of the silicon channel are a major occurs, SOI will be the key element 8. G. Shahidi, A. Ajmera, F. Assaderaghi, innovation in the device architecture. in ensuring that these 3D structures, E. Leobandung, D. Sankus, W. Rausch, There are several types of FinFETs such as FinFETs, are manufacturable. D. Schepis, L. Wagner, K. Wu, and B. Davari; in Technical Digest of as schematically shown in Fig. 12. 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About Authors
Carlos Mazuré is Chief Technical Officer two doctorates in physics, one from the a Ph.D. in solid-state physics from Purdue of Soitec. In this role, he drives the University of Grenoble, France, and the University. In addition to his long-term identification and development of next- other from the Technical University of interest in silicon-on-insulator structures generation engineered substrates for the Munich, Germany. Fluent in several and their applications, he also investigated microelectronic industry as well as for languages, Mazuré is the author of more laser annealing and rapid thermal emerging applications that help define than 150 technical papers and holds more processing of semiconductors, diffusion the future business directions for the than 70 patents worldwide. He may be phenomena, and x-ray lithography. He company. He works closely with Soitec’s reached at [email protected]. published about 200 articles, edited six customers, suppliers and academia to books, and was issued 15 U.S. patents. help support and open new applications George K. Celler, Chief Scientist at Soitec He is a fellow of the APS and of the ECS. for Soitec’s Smart Cut™ technology. USA, is responsible for company’s technical He has received the 1994 Electronics Prior to joining Soitec, Mazuré served interactions in the U.S. Before joining Division Award of the ECS, and two Bell as director of business development at Soitec, he was a Distinguished Member of Labs President’s Gold Awards. He may be Infineon Technologies AG, where he was Tebchnical Staff and Technical Manager reached at [email protected]. involved with the IBM/Infineon DRAM at Bell Laboratories. He received his M.Sc. Development Alliance. Mazuré holds degree from the University of Warsaw and
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40 The Electrochemical Society Interface • Winter 2006