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Advanced Electronic Substrates for the Nanotechnology

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Advanced Electronic Substrates for the Nanotechnology way presents its own set of technical advantages and challenges. For advanced RF SOCs, high Advanced Electronic Substrates impedance SOI substrates with a high resistivity handle wafer provide Volume 1–LOS ANGELES, CALIFORNIA significant advantages,23 while SOI for the Nanotechnology Era with ultra thin buried oxide (<50 FROMTHE%#3,OS!NGELESMEETING /CTOBER nm) will enable IC architectures where n and p regions are defined 4HEFOLLOWINGISSUESOF%#34RANSACTIONSAREFROMSYMPOSIAHELDDURINGTHE,OS!NGELESMEETING!LLISSUESAREAVAILABLEIN by Carlos Mazuré and George K. Celler in the handle substrate for back ONLINEEDITIONS WHICHMAYBEPURCHASEDBYVISITINGHTTPWWWELECTROCHEMORGDLECST3OMEISSUESAREALSOAVAILABLEINHARD bias generation through the buried COVEREDITIONS0LEASEVISITTHE%#3WEBSITEFORALLISSUEPRICINGANDORDERINGINFORMATION oxide.24 Since attaining the highest or the last few decades the in order to boost carrier mobility. Wafer performance is not the focus here, performance of silicon integrated level tensile biaxial strain will further these SOI CMOS solutions will target !VAILABLE)SSUES(ARD#OVER/NLINE Fcircuits has steadily progressed, as enhance the channel engineering the lowest power consumption and anticipated by Moore’s law, primarily possibilities. Three-dimensional devices longest battery lifetime. Low standby 6OL 0HYSICSAND#HEMISTRYOF3I/ 6OL #ORROSIONAND%LECTROCHEMISTRY 6OL 3OLID 3TATE)ONIC$EVICES)6 through scaling of all critical device like FinFETs21,22 may supplement and low operating power devices .O ANDTHE3I 3I/)NTERFACE .O OF!DVANCED-ATERIALS IN(ONOROF .O %DITORS%$7ACHSMAN &('ARZON dimensions.1 This classical scaling is and eventually replace planar device will be built by taking full advantage %DITORS(:-ASSOUD *(3TATHIS +OJI(ASHIMOTO %4RAVERSA 2-UNKUNDAN 6"IRSS either no longer possible (for example structures.1 SOC applications will of dielectric isolation, while high 4(ATTORI $-ISRA AND)"AUMVOL %DITORS3&UJIMOTO ((ABAZAKI (ARD COVER - .- gate SiO2 thickness has reached its push PD SOI and high impedance resistivity substrates will substantially (ARD COVER- .- %!KIYAMA "-AC$OUGALL /NLINE - .- limit) or does not allow achieving the SOI designs, possibly transitioning improve performance of passive /NLINE- .- (ARD COVER- .- targeted device performance increase over to FD designs for very low power components such as inductors that are /NLINE - .- 6OL $URABILITYAND2ELIABILITYOF,OW per technology node. Starting with applications. Figure 1 is also a good placed directly on the silicon chip. 6OL 3TATE OF THE !RT0ROGRAMON .O 4EMPERATURE&UEL#ELLS3YSTEMS the 90 nm technology, innovations illustration of some of the engineered .O #OMPOUND3EMICONDUCTORS 6OL 0HYSICSAND4ECHNOLOGY %DITORS4$*ARVI ('ASTEIGER other than simple scaling are the main substrate options being evaluated for SOI Substrate Fabrication 3/4!0/#38,))) AND .ITRIDEAND .O OF(IGH K'ATE$IELECTRICS))) 3#LEGHORN contributors to better performance. the 65, 45, and 32 nm nodes. Substrate engineering2,3 has enabled The high performance path will Silicon on Insulator (SOI) 7IDE"ANDGAP3EMICONDUCTORSFOR %DITORS3+AR $-ISRA ()WAI (ARD COVER - .- 3ENSORS 0HOTONICS AND%LECTRONICS6) -(OUSSA $,ANDHEER 74SAI /NLINE - .- the industry to overcome many continue to be the driver for the technology was initiated in the 1960s %DITORS**7ANG &2EN 3$E'ENDT of the limitations encountered by most advanced substrates and the by the demands of radiation-hard AND2#&ITCH traditional scaling. As a result, device material innovation. Ultra-thin (UT) circuits. During 1970s and ‘80s several (ARD COVER - .- architecture and engineered substrates SOI, mobility enhancing substrates SOI materials and structures were /NLINE- .- (ARD COVER- .- have become strongly coupled, a like strained SOI (sSOI), in addition conceived for dielectrically separating /NLINE - .- 6OL 0ROTON%XCHANGE-EMBRANE coupling that is growing stronger as to local strain techniques, as well the thin, active device volume from the IC industry moves to the 65 nm as improved thermal dissipation to the silicon substrate.5- 7 The background 6OL #LEANING4ECHNOLOGYIN3EMICONDUCTOR .O &UEL#ELLS6 IN(ONOROF technology node and beyond. Substrate 3UPRAMANIAM3RINIVASAN .O $EVICE-ANUFACTURING)8 engineering started in earnest with %DITORS*2UZYLLO 4(ATTORI %DITORS4&ULLER #,AMY #"OCK the industry transition to SOI wafers AND2%.OVAK (ARD COVER- .- in the late ‘90s.4-7 SOI substrates (ARD COVER - .- /NLINE- .- made possible increasing the drive /NLINE - .- current while simultaneously reducing parasitic leakage, thus improving IC performance and reducing power !VAILABLE)SSUES/NLINE/NLYSEETHE%#3WEBSITEFORPRICINGANDORDERINGINFORMATION consumption. SOI has allowed the IC industry to develop superb solutions for high performance logic, 6OL #ORROSION0ROTECTIVE#OATINGSAND 6OL -OLECULAR3TRUCTURE%FFECTS 6OL #ORROSION0OSTERS'ENERAL including the latest gaming-dedicated .O )NHIBITORS%DITORS-+ENDIG .O IN(ETEROGENEOUS%LECTRON .O %DITOR*7EIDNER microprocessors.8-10 Other highly 2'RANATA '/)LEVBARE 3+URODA 4RANSFER+INETICS 6OL competitive designs address “smart %DITORS'"RISARD $IELECTRICSANDTHE$IELECTRIC 6OL .O power” for automotive,11 and very low !TOMIC,AYER$EPOSITION 27&AWCETT $%VANS %LECTROLYTE)NTERFACEIN"IOLOGICAL .O %DITORS!2,ONDERGAN AND"IOMEDICAL!PPLICATIONS power ICs for consumer applications.12 '3-ATHAD (':OLLA 40#HIANG 6OL 0HYSICAL%LECTROCHEMISTRY'ENERAL %DITOR*7EIDNER In more recent advances beyond .O %DITOR'"RISSARD 6OL #OPPER)NTERCONNECTS .EW#ONTACT 6OL 4HERMALAND0LASMA conventional SOI, new substrates like 13-17 .O AND"ARRIER-ETALLURGIES3TRUCTURES 6OL !COUSTIC7AVE"ASED .O #6$OF.ANOSTRUCTURES strained SOI and hybrid bonding AND,OW K)NTER LEVEL$IELECTRICS))) .O 3ENSORSAND3ENSOR3YSTEMS %DITOR*7EIDNER SOI18-20 have increased the number of %DITORS'3-ATHAD -%NGLEHARDT %DITOR'(UNTER options for enhancing device mobility. 6OL ++ONDO (32ATHORE 3OLID 3TATE0OSTERS'ENERAL 6OL 4HREE $IMENSIONAL-ICRO AND .O %DITOR*7EIDNER While the 90 nm node is 6OL %LECTRODEPOSITIONOF.ANOENGINEERED .O .ANOSCALE"ATTERY!RCHITECTURES characterized by the adoption of SOI 6OL 8- 10 .O -ATERIALSn%DITORS.6-YUNG %DITOR*7EIDNER 3CIENCE 4ECHNOLOGY AND4OOLSFOR for high performance applications, .O %LECTRODEPOSITIONFROM,ABTO&ACTORY 2-0ENNER .*4AO $ 90ARK the future nodes are driving numerous Fig. 1. Device architectures that are either already in use or are anticipated in future 6OL 3ENSORS !CTUATORS AND-ICROSYSTEMS %DITOR*7EIDNER substrate solutions. The device 6OL 'REEN%LECTRODEPOSITION .O %DITOR'(UNTER :!GUILAR 3!KBAR technology nodes. 6OL development of the future technology .O %DITORS32OY ':ANGARI #"RUCKNER ,EA -*OSOWICZ %NERGY4ECHNOLOGY .O 2-UKUNDUN AND*23ETTER AND"ATTERIES'ENERAL nodes appears to be marked by two reduce the impact of hot spots on idea is that in a bulk silicon MOS 6OL %NERGYFOR#LEANER4RANSPORTATION %DITOR*7EIDNER distinct technical strategies, one MOSFET performance, are among the transistor, only a superficial layer, .O %DITORS+:AGHIB *0RAKASH 6OL 3ENSORS"ASEDON.ANOTECHNOLOGY)) 6OL focused on high performance, and most obvious engineered substrate typically <100 nm thick, is actually 2$-C#ONNELL &2-C,ARNON .O %DITOR'(UNTERAND*23ETTER 0HOTOVOLTAICSFORTHEST#ENTURY))) .O %DITOR*7EIDNER one driven by system-on-chip (SOC) solutions. Device architectures are useful for electron transport, whereas 6OL %LECTROCHROMICSFOR%NERGY%FFICIENCY 6OL 3TUDENT0OSTERS'ENERAL applications, including low power, likely to remain planar at least for the the substrate causes undesirable effects. 6OL .O &ROMTHE-ATERIALTOTHE3YSTEM .O %DITOR*7EIDNER 0HYSICSAND#HEMISTRYOF .O portable RF applications. Figure 1 is next two generations, with non-planar The overwhelming success of bulk- %DITORS+:AGHIB *8U ,UMINESCENT-ATERIALS8)6 6OL a tentative device roadmap for logic FinFETs on the horizon for the 32 nm Si CMOS confined SOI technology to #-*ULIEN &$3OUZA "ATTERY3AFETYAND!BUSE4OLERANCE %DITOR*7EIDNER .O %DITOR*7EIDNER applications. Today’s partially depleted node for the most aggressive IC players. niche applications until late 1990s. 6OL 6OL -ULTISCALE3IMULATIONSOF /RGANICAND"IOLOGICAL (PD) transistor architecture may evolve Partially depleted approaches will push Then several factors have increased 6OL .O .O %LECTROCHEMICAL3YSTEMS 0RIMARYAND3ECONDARY %LECTROCHEMISTRY0OSTERS'ENERAL into a fully depleted (FD) approach. the mobility enhancing substrates the interest in SOI: invention of .O #OMPUTATIONAL!SPECTS !QUEOUS"ATTERIES %DITOR*7EIDNER High performance logic utilizes while others may switch to ultra-thin new fabrication methods for SOI %DITOR*7EIDNER %DITORS623UBRAMANIAN uniaxial tensile strain for n channels fully depleted SOI in order to improve ''"OTTE 2#!LKIRE 6OL 2ECHARGEABLE,ITHIUM and compressive strain for p channels electrostatic device characteristics. Each (continued on next page) *3T0IERRE *-EYERS +2(EBERT .O AND,ITHIUM )ON"ATTERIES %DITOR*7EIDNER The Electrochemical Society Interface • Winter 2006 33 FIG. 2. A schematic process flow for SOI wafer fabrication by Smart FIG. 3. Crystalline plane orientations and directions within the planes that Cut technology. improve electron and/or hole mobility in Si MOSFETs. materials and their optimization, need The Smart Cut technology is a Substrates with Enhanced Charge for lower power and higher speed powerful tool that applies to many Carrier Mobility circuits, emerging limitations of bulk materials, making it possible to create CMOS scaling. SOI transistors are a wide range of composite substrates Mobility
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